16-bit with Kbyte Flash memory Kbyte High performance 16-bit with
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ST10F273M
16-bit with Kbyte Flash memory Kbyte
High performance 16-bit with functions 50ns instruction cycle time clock Multiply/accumulate unit (MAC) 16-bit multiplication, 40-bit accumulator Enhanced boolean manipulations Single-cycle context switching support Memory organization Kbyte on-chip Flash memory single voltage with erase/program controller (full performance, 32-bit fetch) 100K erasing/programming cycles. Mbyte linear address space code data Mbytes with I2C) Kbyte on-chip internal (IRAM) Kbyte on-chip extension (XRAM) Programmable external configuration characteristics different address ranges programmable chip-select signals Hold-acknowledge arbitration support Interrupt 8-channel peripheral event controller single cycle interrupt driven data transfer 16-priority-level interrupt system with sources, sampling rate down 25ns Timers multifunctional general purpose timer units with timers 16-channel capture compare units 4-channel unit 4-channel XPWM
PQFP144 3.4mm) (Plastic Quad Flat Package)
LQFP144 1.4mm) (Low Profile Quad Flat Package)
24-channel converter 16-channel 10-bit, accuracy +/-2 8-channel 10-bit, accuracy +/-5 4.85µs Minimum conversion time Serial channels synch. asynch. serial channels high-speed synchronous channels standard interface 2.0B interfaces operating buses 2x32 messages, C-CAN version) Fail-safe protection Programmable watchdog timer Oscillator watchdog On-chip bootstrap loader Clock generation On-chip oscillator Direct prescaled clock input Real time clock on-chip oscillator general purpose lines Individually programmable input, output special function Programmable threshold (hysteresis) Idle, power down standby modes Single voltage supply: ±10% (embedded regulator 1.8V core supply) Temperature range: +125
July 2007
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Contents
ST10F273M
Contents
Introduction
Description Special characteristics
1.2.1 1.2.2 X-Peripheral clock gating Improved supply ring
data Functional description Memory organization Internal Flash memory
Overview Functional description
5.2.1 5.2.2 5.2.3 Structure Module structure power mode
Write operation Flash control registers description
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.4.10 5.4.11 5.4.12 Flash control register (FCR0L) Flash control register high (FCR0H) Flash control register (FCR1L) Flash control register high (FCR1H) Flash data register (FDR0L) Flash data register high (FDR0H) Flash data register (FDR1L) Flash data register high (FDR1H) Flash address register (FARL) Flash address register high (FARH) Flash error register (FER) XFlash interface control dummy register (XFICR)
Protection strategy
5.5.1 Protection registers
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ST10F273M 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.5.10 5.5.11
Contents Flash non-volatile write protection register (FNVWPIRL) Flash non-volatile write protection register high (FNVWPIRH) Flash non-volatile write protection register Mirror (FNVWPIRL-m) Flash non-volatile write protection register high Mirror (FVWPIRH-m) Flash non-volatile access protection register (FNVAPR0) Flash non-volatile access protection register (FNVAPR1L) Flash non-volatile access protection register high (FNVAPR1H) Access protection Write protection Temporary unprotection
Write operation examples Write operation summary
Bootstrap loader
Selection among user-code, standard selective bootstrap Standard bootstrap loader Alternate selective boot mode (ABM SBM)
6.3.1 6.3.2 6.3.3 Activation User mode signature integrity check Selective boot mode
Central processing unit (CPU)
Multiplier-accumulator unit (MAC) Instruction summary co-processor specific instructions
External controller Interrupt system
X-Peripheral interrupt Exception error traps list
Capture compare (CAPCOM) units General purpose timer unit
11.1 GPT1
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Contents
ST10F273M
11.2
GPT2
modules Parallel ports
13.1 13.2 Introduction I/O's special features
13.2.1 13.2.2 Open drain mode Input threshold control
13.3
Alternate port functions
converter Serial channels
15.1 15.2 15.3 15.4 Asynchronous synchronous serial interfaces ASCx asynchronous mode ASCx synchronous mode High speed synchronous serial interfaces
interface modules
17.1 17.2 Configuration support configurations
17.2.1 17.2.2 17.2.3 Single Multiple Parallel mode
Real time clock Watchdog timer System reset
20.1 20.2 20.3 Input filter Asynchronous reset Synchronous reset (warm reset)
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ST10F273M
Contents
20.4 20.5 20.6 20.7 20.8 20.9
Software reset Watchdog timer reset Bidirectional reset Reset circuitry Reset application examples Reset summary
Power reduction modes
21.1 21.2 Idle mode Power-down mode
21.2.1 21.2.2 Protected power-down mode Interruptible power-down mode
21.3
Standby mode
21.3.1 21.3.2 21.3.3 21.3.4 Entering standby mode Exiting standby mode Real time clock standby mode Power reduction modes summary
Programmable output clock divider Register
23.1 23.2 23.3 23.4 Special function registers X-registers Flash registers ordered name Identification registers
Electrical characteristics
24.1 24.2 24.3 24.4 24.5 24.6 24.7 Absolute maximum ratings Recommended operating conditions Power considerations Parameter interpretation characteristics Flash characteristics converter characteristics
24.7.1 Conversion timing control
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Contents 24.7.2 24.7.3 24.7.4
ST10F273M conversion accuracy Total unadjusted error Analog reference pins
24.8
characteristics
24.8.1 24.8.2 24.8.3 24.8.4 24.8.5 24.8.6 24.8.7 24.8.8 24.8.9 Test waveforms Definition internal timing Clock generation modes Prescaler operation Direct drive Oscillator watchdog (OWD) Phase locked loop (PLL) Voltage controlled oscillator jitter
24.8.10 lock unlock 24.8.11 Main oscillator specifications 24.8.12 oscillator specifications 24.8.13 External clock drive XTAL1 24.8.14 Memory cycle variables 24.8.15 External memory timing 24.8.16 Multiplexed 24.8.17 Demultiplexed 24.8.18 CLKOUT READY 24.8.19 External arbitration 24.8.20 High-speed synchronous serial interface (SSC) timing
Package information
25.1 25.2 ECOPACK® Mechanical data package dimensions
Ordering information Revision history
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ST10F273M
List tables
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table description Summary IFlash address range Flash module address space Flash module sectorization (read operations). Flash module sectorization (write operations, ROMS1 `1') Flash control registers summary. FCR0L register description FCR0H register description FCR1L register description FCR1H register description Bank (BxS) sectors (BxFy) status bits meaning. FDR0L register description FDR0H register description FDR1L register description FDR1H register description FARL register description FARH register description. register bits XFlash interface control register FNVWPIRL register bits FNVWPRIH register bits FNVAPR0 register bits FNVAPR1L register bits FNVAPR1H register bits Summary access protection level Flash write operations. ST10F273M boot mode selection Standard instruction summary instruction summary Interrupt sources X-Interrupt detailed mapping Trap priorities Compare modes CAPCOM timer input frequencies, resolutions periods GPT1 timer input frequencies, resolutions periods MHz. GPT2 timer input frequencies, resolutions periods MHz. unit frequencies resolutions clock asynchronous baudrates reload value deviation errors synchronous baudrates reload value deviation errors synchronous baudrate reload values WDTREL reload value Reset event definition Reset event. PORT0 latched configuration different reset events Power reduction modes summary List special function registers List XBus registers List Flash control registers
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List tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
ST10F273M
IDMANUF register description IDCHIP register description IDMEM register description IDPROG register description Absolute maximum ratings Recommended operating conditions Thermal characteristics. Package characteristics characteristics. Flash characteristics Flash data retention characteristics converter characteristics converter programming On-chip clock generator selections. Internal divider mechanism characteristics (VDD 10%, -40°C +125°C) Main oscillator characteristics Main oscillator negative resistance (module) oscillator characteristics Minimum values negative resistance (module) oscillator External clock drive XTAL1 timing Memory cycle variables Multiplexed timings Demultiplexed timings CLKOUT READY timings External arbitration timings master mode timings slave mode timings. Order codes Document revision history
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ST10F273M
List figures
List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure ST10F273M Logic symbol configuration (top view) Block diagram ST10F273M memory mapping (XADRS3 800Bh reset value) ST10F273M memory mapping (XADRS3 E009h user programmed value) Flash structure Write operation control flow block diagram (MAC unit included) unit architecture X-Interrupt basic structure Block diagram GPT1. Block diagram GPT2. Block diagram module Connection single separate transceivers Connection single common transceivers. Connection different buses (for example gateway application) Connection with internal parallel mode enabled. Asynchronous power-on RESET Asynchronous power-on RESET Asynchronous hardware RESET Asynchronous hardware RESET Synchronous short long hardware RESET Synchronous short long hardware RESET Synchronous long hardware RESET Synchronous long hardware RESET unidirectional RESET unidirectional RESET bidirectional RESET bidirectional RESET bidirectional RESET followed RESET Minimum external reset circuitry System reset circuit Internal (simplified) reset circuitry Example software watchdog bidirectional reset Example software watchdog bidirectional reset PORT0 bits latched into different registers after reset External circuitry Port2 test mode structure Supply current versus operating frequency (RUN IDLE modes) conversion characteristics converter input pins scheme Charge-sharing timing diagram during sampling phase Anti-aliasing filter conversion rate Input/output waveforms Float waveform Generation mechanisms clock ST10F273M jitter Crystal oscillator resonator connection diagram
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List figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
ST10F273M
crystal oscillator connection diagram External clock drive XTAL1. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. External memory cycle: Multiplexed bus, with/without delay, normal ALE, External memory cycle: Multiplexed bus, with/without delay, extended ALE, External memory cycle: Demultiplexed bus, with/without delay, normal External memory cycle: Demultiplexed bus, with/without delay, extended External memory cycle: Demultipl. bus, with/without delay, normal ALE, External memory cycle: Demultiplexed bus, without delay, extended ALE, CLKOUT READY External arbitration (releasing bus) External arbitration (regaining bus) master timing slave timing PQFP144 mechanical data package dimensions LQFP144 mechanical data package dimensions
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ST10F273M
Introduction
Introduction
Description
ST10F273M device derivative STMicroelectronics ST10 family 16-bit single-chip CMOS microcontrollers. ST10F273M combines high performance million instructions second) with high peripheral functionality enhanced capabilities. also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, clock generation PLL. ST10F273M processed 0.18mm CMOS technology. core logic supplied with 1.8V on-chip voltage regulator. part supplied with single supply I/Os work ST10F273M optimized version ST10F273E, upward compatible with following differences:
Maximum frequency single bank IFlash been implemented programming interface been kept compatible with ST10F273E Identification registers: IDMEM register reflects Flash type difference allows differentiate devices software Improved behavior thanks introduction internal filter ballast transistors clock X-Peripherals gated: X-Peripheral used will clock order reduce power consumption.
1.2.1
Special characteristics
X-Peripheral clock gating
This feature have been implemented ST10F273M: Once EINIT instruction been executed, only X-Peripherals enabled XPERCON register will clocked. feature allows reduce power consumption also should improve emissions avoids propagate useless clock signals across device.
1.2.2
Improved supply ring
filter been introduced power supply ring ballast transistor. addition, supply rings internal voltage regulators have been split. These modifications should improve behavior device regarding conducted emissions.
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Introduction Figure ST10F273M Logic symbol
ST10F273M
XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT VAREF VAGND VSTBY READY Port 16-bit Port 16-bit Port 16-bit Port 16-bit Port 15-bit ST10F273M Port 8-bit Port 8-bit Port 8-bit Port 8-bit
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ST10F273M
data
data
Figure configuration (top view)
XTAL4 XTAL3 RSTOUT RSTIN XTAL1 XTAL2 P1H.7 CC27I P1H.6 CC26I P1H.5 CC25I P1H.4 CC24I P1H.3 P1H.2 P1H.1 P1H.0 P1L.7 AN23 P1L.6 AN22 P1L.5 AN21 P1L.4 AN20 P1L.3 AN19 P1L.2 AN18 P1L.1 AN17 P1L.0 AN16 P0H.7 AD15 P0H.6 AD14 P0H.5 AD13 P0H.4 AD12 P0H.3 AD11 P0H.2 AD10 P0H.1
P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 HOLD SCLK1 P6.6 HLDA MTSR1 P6.7 BREQ MRST1 P8.0 XPOUT0 CC16IO P8.1 XPOUT1 CC17IO P8.2 XPOUT2 CC18IO P8.3 XPOUT3 CC19IO P8.4 CC20IO P8.5 CC21IO P8.6 RxD1 CC22IO P8.7 TxD1 CC23IO P7.0 POUT0 P7.1 POUT1 P7.2 POUT2 P7.3 POUT3 P7.4 CC28IO P7.5 CC29IO P7.6 CC30IO P7.7 CC31IO P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9
ST10F273M
P0H.0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 VSTBY READY WR/WRL P4.7 CAN2_TxD P4.6 CAN1_TxD CAN2_TxD P4.5 CAN1_RxD CAN2_RxD P4.4 CAN2_RxD P4.3 P4.2 P4.1 P4.0 P3.15 CLKOUT P3.13 SCLK0 P3.12 P3.11 RxD0 P3.10 TxD0 P3.9 MTSR0 P3.8 MRST0 P3.7 T2IN P3.6 T3IN
VAREF VAGND P5.10 AN10 T6EUD P5.11 AN11 T5EUD P5.12 AN12 T6IN P5.13 AN13 T5IN P5.14 AN14 T4EUD P5.15 AN15 T2EUD P2.0 CC0IO P2.1 CC1IO P2.2 CC2IO P2.3 CC3IO P2.4 CC4IO P2.5 CC5IO P2.6 CC6IO P2.7 CC7IO P2.8 CC8IO EX0IN P2.9 CC9IO EX1IN P2.10 CC10IO EX2IN P2.11 CC11IO EX3IN P2.12 CC12IO EX4IN P2.13 CC13IO EX5IN P2.14 CC14IO EX6IN P2.15 CC15IO EX7IN T7IN P3.0 T0IN P3.1 T6OUT P3.2 CAPIN P3.3 T3OUT P3.4 T3EUD P3.5 T4IN
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data Table
Symbol
ST10F273M description
Type Function 8-bit bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL CMOS). following Port pins have alternate functions: P6.0 P6.4 P6.5 HOLD SCLK1 P6.6 HLDA MTSR1 P6.7 BREQ MRST1 Chip select output Chip select output External master hold request input SSC1: master clock output slave clock input Hold acknowledge output SSC1: master-transmitter slave-receiver request output SSC1: master-receiver slave-transmitter
P6.0 P6.7
8-bit bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL CMOS). following Port pins have alternate functions: P8.0 CC16IO XPWM0 P8.3 CC19IO XPWM0 P8.4 P8.5 P8.6 CC20IO CC21IO CC22IO RxD1 P8.7 CC23IO TxD1 CAPCOM2: CC16 capture input compare output PWM1: channel output CAPCOM2: CC19 capture input compare output PWM1: channel output CAPCOM2: CC20 capture input compare output CAPCOM2: CC21 capture input compare output CAPCOM2: CC22 capture input compare output ASC1: Data input (Asynchronous) (Synchronous) CAPCOM2: CC23 capture input compare output ASC1: Clock Data output (Asynchronous/Synchronous)
9-16
P8.0 P8.7
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ST10F273M Table
Symbol
data description (continued)
Type Function 8-bit bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL CMOS). following Port pins have alternate functions: P7.0 P7.3 P7.4 P7.7 POUT0 POUT3 CC28IO CC31IO PWM0: channel output PWM0: channel output CAPCOM2: CC28 capture input compare output CAPCOM2: CC31 capture input compare output
19-26
P7.0 P7.7
27-36 39-44
16-bit input-only port with Schmitt-Trigger characteristics. pins Port analog input channels converter, where P5.x equals (Analog input channel they timer inputs. input threshold Port selectable (TTL CMOS). following Port pins have alternate functions: P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 T6EUD T5EUD T6IN T5IN T4EUD T2EUD GPT2: timer external up/down control input GPT2: timer external up/down control input GPT2: timer count input GPT2: timer count input GPT1: timer external up/down control input GPT1: timer external up/down control input
P5.0 P5.9 P5.10 P5.15
47-54 57-64
16-bit bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL CMOS). following Port pins have alternate functions: P2.0 P2.7 P2.8 CC0IO CC7IO CC8IO EX0IN CC15IO P2.15 EX7IN T7IN CAPCOM: capture input/compare output CAPCOM: capture input/compare output CAPCOM: capture input/compare output Fast external interrupt input CAPCOM: CC15 capture input/compare output Fast external interrupt input CAPCOM2: timer count input
P2.0 P2.7 P2.8 P2.15
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data Table
Symbol
ST10F273M description (continued)
65-70, 73-80, Type Function 15-bit (P3.14 missing) bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL CMOS). following Port pins have alternate functions: P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15 SCLK0 CLKOUT External memory high byte write strobe SSC0: master clock output slave clock input System clock output (programmable divider clock) T0IN T6OUT CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST0 MTSR0 TxD0 RxD0 CAPCOM1: timer count input GPT2: timer toggle latch output GPT2: register CAPREL capture input GPT1: timer toggle latch output GPT1: timer external up/down control input GPT1; timer input count/gate/reload/capture GPT1: timer count/gate input GPT1: timer input count/gate/reload capture SSC0: SSC0: ASC0: clock data output (asynchronous/synchronous) ASC0: data input (asynchronous) (synchronous) External memory high byte enable signal
P3.0 P3.5 P3.6 P3.13, P3.15
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ST10F273M Table
Symbol
data description (continued)
Type Function Port 8-bit bidirectional port. bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. input threshold selectable (TTL CMOS). Port 4.4, 4.5, outputs configured push-pull open drain drivers. case external configuration, Port used output segment address lines: P4.0 P4.1 P4.2 P4.3 P4.4 CAN2_RxD P4.5 CAN1_RxD CAN2_RxD P4.6 CAN1_TxD CAN2_TxD P4.7 CAN2_TxD Segment address line Segment address line Segment address line Segment address line Segment address line CAN2: receive data input Interface: serial clock Segment address line CAN1: receive data input CAN2: receive data input Segment address line CAN1: transmit data output CAN2: transmit data output Most significant segment address line CAN2: transmit data output Interface: serial data
85-92
P4.0 -P4.7
External memory read strobe. activated every external instruction data read access. External memory write strobe. WR-mode this activated every external data write access. mode this activated byte data write accesses 16-bit bus, every data write access 8-bit bus. WRCFG SYSCON register mode selection. Ready input. active level programmable. When ready function enabled, selected inactive level this pin, during external memory access, will force insertion waitstate cycles until returns selected active level. Address latch enable output. case external addressing multiplexed mode, this signal latch command address lines.
WR/WRL
READY/ READY
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data Table
Symbol
ST10F273M description (continued)
Type Function External access enable pin. level applied this during after Reset forces ST10F273M start program from external memory space. high level forces ST10F273M start internal memory space. This also used (when Standby mode entered, that ST10F273M under reset main turned off) bias oscillator amplifier circuit provide reference voltage low-power embedded voltage regulator which generates internal 1.8V supply module (when disabled) retain data inside Standby portion XRAM Kbyte). range from 5.5V reduced amount time during device life, 4.0V when on-chip oscillator amplifier turned off). running mode, this tied during reset without affecting oscillator, XRAM activities, since presence stable guarantees proper biasing those modules. 8-bit bidirectional ports P0H, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. input threshold Port selectable (TTL CMOS). case external configuration, PORT0 serves address address data (AD) multiplexed modes data demultiplexed modes. Demultiplexed modes
VSTBY
P0L.0 -P0L.7, 100-107, P0H.0 108, P0H.1 P0H.7 111-117
Data path width P0L.0 P0L.7: P0H.0 P0H.7:
8-bit
16-bit
Multiplexed modes Data path width P0L.0 P0L.7: P0H.0 P0H.7: 8-bit
16-bit
AD15
118-125 128-135 P1L.0 P1L.7 P1H.0 P1H.7
8-bit bidirectional ports P1H, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. PORT1 used 16bit address demultiplexed modes: least BUSCONx configured such demultiplexed mode selected, PORT1 available general purpose function. input threshold Port selectable (TTL CMOS). pins also serve additional analog input channels converter, where P1L.x equals (Analog input channel where 16). This additional function have higher priority demultiplexed function. following PORT1 pins have alternate functions: P1H.4 CC24IO P1H.5 CC25IO P1H.6 CC26IO P1H.7 CC27IO CAPCOM2: CC24 capture input CAPCOM2: CC25 capture input CAPCOM2: CC26 capture input CAPCOM2: CC27 capture input
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ST10F273M Table
Symbol XTAL1 XTAL2
data description (continued)
Type Function XTAL1 Main oscillator amplifier circuit and/or external clock input. XTAL2 Main oscillator amplifier circuit output. clock device from external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum maximum high rise fall times specified Characteristics must observed.
XTAL3 XTAL4
XTAL3 oscillator amplifier circuit input XTAL4 oscillator amplifier circuit output When oscillator amplifier used, avoid spurious consumption, XTAL3 shall tied ground while XTAL4 shall left open. Besides, OFF32 RTCCON register shall set. oscillator only driven external crystal, different clock source. Reset Input with CMOS Schmitt-Trigger characteristics. level this specified duration while oscillator running resets ST10F273M. internal pull-up resistor permits power-on reset using only capacitor connected VSS. bidirectional reset mode (enabled setting BDRSTEN SYSCON register), RSTIN line pulled duration internal reset sequence. Internal Reset Indication Output. This driven level during hardware, software watchdog timer reset. RSTOUT remains until EINIT (end initialization) instruction executed. Non-Maskable Interrupt Input. high transition this causes vector trap routine. PWDCFG SYSCON register, when PWRDN (power down) instruction executed, must order force ST10F273M into power down mode. high PWDCFG `0', when PWRDN executed, part will continue normal mode. used, should pulled high externally. converter reference voltage analog supply converter reference analog ground Timing return from interruptible power down mode synchronous asynchronous reset selection. Digital supply voltage during normal operation, idle power down modes. turned when Standby mode selected.
RSTIN
RSTOUT
VAREF VAGND
72,82,93, 109, 126, 18,45, 55,71, 83,94, 110, 127,
Digital ground
1.8V decoupling pin: decoupling capacitor (typical value 10nF, 100nF) must connected between this nearest pin.
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Functional description
ST10F273M
Functional description
architecture ST10F273M combines advantages both RISC CISC processors advanced peripheral subsystem. block diagram gives overview different on-chip components high bandwidth internal structure ST10F273M. Figure Block diagram
IFlash 512K CPU-core unit IRAM
XRAM1 (PEC) XRAM2 (16K STBY) XPWM XRTC XASC XI2C XSSC XCAN1 XCAN2
Watchdog Oscillator oscillator Interrupt controller 5V-1.8V voltage regulator
Port
GPT1 GPT2
External controller
CAPCOM2
Port
Port
Port
Port
Port
Port
Port
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Port
CAPCOM1
10-bit
ASC0
SSC0
ST10F273M
Memory organization
Memory organization
memory space ST10F273M configured unified memory architecture. Code memory, data memory, registers ports organized within same linear address space Mbytes. entire memory space accessed Bytewise Wordwise. Particular portions on-chip memory have additionally been made directly addressable. IFlash: Kbytes on-chip Flash memory implemented unique Bank (Bank0). Bank0 divided blocks (B0F0.B0F11).
Note:
Read-while-write operations allowed: Write commands must executed from IFlash memory area (on-chip external memory). When Bootstrap mode selected, Test-Flash Block B0TF Kbytes) appears address 00'0000h: Refer device User Manual more details memory mapping Bootstrap mode. summary address range IFlash following: Table Summary IFlash address range
Blocks B0TF B0F0 B0F1 B0F2 B0F3 B0F4 B0F5 B0F6 B0F7 B0F8 B0F9 B1F0 B0F10 B1F1 B0F11
User mode visible 00'0000h 00'1FFFh 00'2000h 00'3FFFh 00'4000h 00'5FFFh 00'6000h 00'7FFFh 01'8000h 01'FFFFh 02'0000h 02'FFFFh 03'0000h 03'FFFFh 04'0000h 04'FFFFh 05'0000h 05'FFFFh 06'0000h 06'FFFFh 07'0000h 07'FFFFh 08'0000h 08'FFFFh
Size (bytes)
Note:
single Flash bank implemented ST10F273M compared ST10F273E. last sectors (B0F10 B0F11) seen Bank1 ST10F273E order maintain compatibility with existing Flash programming drivers. this, control status blocks B0F10 B0F11 have been duplicated usable blocks B1F0 B1F1 ST10F273E. XFLASH Flash Control Registers: Address range 0E'0000h-0E'FFFFh reserved Flash Control Register other internal service memory space used Flash Program/Erase Controller. XFLASHEN XPERCON register must access Flash Control Register. Note that when Flash Control Registers accessible, program/erase operations possible. Flash Control Registers accessed 16-bit demultiplexed bus-mode without read/write delay. Byte word accesses allowed.
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Memory organization
ST10F273M
IRAM: Kbytes on-chip internal (dual-port) provided storage data, system stack, general purpose register banks code. register bank Wordwide R15) Bytewide (RL0, RH0, RL7, RH7) general purpose registers group. XRAM: Kbytes on-chip extension (single port XRAM) provided storage data, user stack code. XRAM divided into areas, first Kbytes named XRAM1 second Kbytes named XRAM2, connected internal XBUS accessed like external memory 16-bit demultiplexed bus-mode without wait state read/write delay (50ns access clock). Byte Word accesses allowed. XRAM1 address range 00'E000h 00'E7FFh XPEN (bit SYSCON register), XRAM1EN (bit XPERCON register) set. XRAM1EN XPEN cleared, then access address range 00'E000h 00'E7FFh will directed external memory interface, using BUSCONx register corresponding address matching ADDRSELx register. XRAM2 address range F'0000h F'7FFFFh XPEN (bit SYSCON register), XRAM2EN (bit XPERCON register) set. XPEN cleared, then access address range programmed XRAM2 will directed external memory interface, using BUSCONx register corresponding address matching ADDRSELx register. kbytes lower portion XRAM2 (address range F'0000h F'3FFFFh) represents also Standby RAM, which maintained biased through VSTBY when main supply turned off. XRAM appears like external memory, cannot used system stack register banks. XRAM provided single storage therefore addressable. SFR/ESFR: 1024 bytes bytes) address space reserved special function register (SFR) areas. SFRs Wordwide registers which used control monitor function different on-chip units. CAN1: Address range 00'EF00h 00'EFFFh reserved CAN1 Module access. CAN1 enabled setting XPEN SYSCON register setting CAN1EN XPERCON register. Accesses Module demultiplexed addresses 16-bit data (only word accesses possible). wait states give access time 100ns clock. tri-state wait states used. CAN2: Address range 00'EE00h 00'EEFFh reserved CAN2 Module access. CAN2 enabled setting XPEN SYSCON register setting CAN2EN XPERCON register. Accesses Module demultiplexed addresses 16-bit data (only word accesses possible). wait states give access time 100ns clock. tri-state wait states used. Note: modules used, Port cannot programmed output eight segment address lines. Thus, only four segment address lines used, reducing external memory space Mbytes Mbyte line). RTC: Address range 00'ED00h 00'EDFFh reserved Module access. enabled setting XPEN SYSCON register XPERCON register. Accesses Module demultiplexed addresses 16-bit data (only word accesses possible). waitstates give access time 100ns clock. tristate waitstate used.
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ST10F273M
Memory organization PWM1: Address range 00'EC00h 00'ECFFh reserved PWM1 Module access. PWM1 enabled setting XPEN SYSCON register XPERCON register. Accesses PWM1 Module demultiplexed addresses 16bit data (only word accesses possible). waitstates give access time 100ns clock. tristate waitstate used. Only word access allowed. ASC1: Address range 00'E900h 00'E9FFh reserved ASC1 Module access. ASC1 enabled setting XPEN SYSCON register XPERCON register. Accesses ASC1 Module demultiplexed addresses 16-bit data (only word accesses possible). waitstates give access time 100ns clock. tristate waitstate used. SSC1: Address range 00'E800h 00'E8FFh reserved SSC1 Module access. SSC1 enabled setting XPEN SYSCON register XPERCON register. Accesses SSC1 Module demultiplexed addresses 16-bit data (only word accesses possible). waitstates give access time 100ns clock. tristate waitstate used. I2C: Address range 00'EA00h 00'EAFFh reserved Module access. enabled setting XPEN SYSCON register XPERCON register. Accesses Module demultiplexed addresses 16-bit data (only word accesses possible). waitstates give access time 100ns clock. tristate waitstate used. X-Miscellaneous: Address range 00'EB00h 00'EBFFh reserved access XBUS additional features. They enabled setting XPEN SYSCON register XPERCON register. Accesses this additional features demultiplexed addresses 16-bit data (only word accesses possible). waitstates give access time 100ns clock. tristate waitstate used. following features provided:
CLKOUT programmable divider XBUS interrupt management registers multiplexing register Port1L digital disable register extra channels CAN2 multiplexing P4.5/P4.6 CAN1-2 main clock prescaler Main Voltage Regulator disable power-down mode CMOS threshold selection Port0, Port1 Port5
order meet needs designs where more memory required than provided chip, Mbytes external memory connected microcontroller.
Visibility XBUS peripherals
order keep ST10F273M compatible with ST10F168 ST10F269, XBUS peripherals selected visible external address data bus. Different bits X-Peripheral enabling XPERCON register must set. these bits cleared before global enabling with XPEN SYSCON register, corresponding address space, port pins interrupts occupied peripherals, thus peripheral visible available. Refer Chapter Register page 114.
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Memory organization
ST10F273M
XPERCON X-Peripheral clock gating
already mentioned, XPERCON register must programmed enable single XBus modules separately. XPERCON read/write ESFR register. feature Clock Gating been implemented means this register: Once EINIT instruction been executed, peripherals (except RAMs XMISC) enabled XPERCON register clocked. clock gating reduce power consumption improve when user does X-Peripherals. Note: When clock been gated disabled peripherals, Reset will raised once EINIT instruction been executed.
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ST10F273M Figure ST10F273M memory mapping (XADRS3 800Bh reset value)
Memory organization
Code Segment
FFFF
Data Code Page Segment 1023 FFFF
Data Page
0000 FFFF
0000 FFFF Reserved
FFFF FE00 FDFF
X-Peripherals (2Kbyte)
I-RAM XADRS3 800Bh (512K Default) F600 F5FF Reserved F200 F1FF F000 EFFF ESFR F000 EFFF XCAN1 EF00 EEFF XCAN2 EE00 EDFF XRTC ED00 ECFF EC00 EBFF XMiscellaneous EB00 EAFF EA00 E9FF XASC E000 DFFF E900 E8FF XSSC E800 E7FF XI2C XPWM
XRAM2
(StandBy)
0000 FFFF 0000 FFFF
Flash Control Registers
0000 FFFF
B3F1 Reserved (XFLASH)
0000 FFFF
Reserved
B3F0 (XFLASH)
0000 FFFF
B2F2 Reserved (XFLASH)
0000 FFFF
Reserved (XFLASH)
B2F1
0000 FFFF
Reserved (XFLASH) B0F11 (B1F1) B0F10 (B1F0) B0F9
B2F0
0000 FFFF
0000 FFFF
0000 FFFF
0000 FFFF
B0F8
0000 FFFF
B0F7
0000 FFFF
B0F6
0000 FFFF
B0F5 B0F4 Ext. Ext. B0F3 B0F2 B0F1 B0F0
0000 FFFF
0000
0000
XCAN1 XCAN2 XRTC XPWM XMiscellaneous XI2C XASC XSSC E800 E7FF XRAM1
Ext. Memory
Address Area defined XADRS3 default after reset
C000
Flash XRAM 1Mbyte
Data Page (Segment 16Kbyte
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Memory organization Figure ST10F273M memory mapping (XADRS3 E009h user programmed value)
ST10F273M
Code Segment
FFFF
Data Code Page Segment 1023 FFFF
Data Page
0000 FFFF
0000 FFFF
FFFF FE00 FDFF XADRS3 E009h
X-Peripherals (2Kbyte)
I-RAM F000 EFFF F600 F5FF Reserved F200 F1FF F000 EFFF ESFR XCAN1 EF00 EEFF XCAN2 EE00 EDFF XRTC ED00 ECFF EC00 EBFF XMiscellaneous EB00 EAFF XI2C XRAM1 EA00 E9FF XASC E000 DFFF E900 E8FF XSSC E800 E7FF XPWM
0000 FFFF
Reserved XRAM2
(StandBy)
0000 FFFF
Flash Control Registers
0000 FFFF
0000 FFFF
0000 FFFF
Memory
0000 FFFF
XCAN1 XCAN2 XRTC XPWM XMiscellaneous XI2C XASC XSSC E800 E7FF
0000 FFFF
0000 FFFF
B0F11 (B1F1) B0F10 (B1F0) B0F9
0000 FFFF
0000 FFFF
0000 FFFF
B0F8
0000 FFFF
B0F7
Ext. Memory
0000 FFFF
B0F6
0000 FFFF
B0F5 B0F4 B0F3 B0F2 B0F1 B0F0
0000 FFFF
Address Area defined XADRS3 after reprogramming Note: E009h defines 128K wide window starting from 0E'0000h C000
0000
0000
Flash XRAM 1Mbyte
Data Page (Segment 16Kbyte
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ST10F273M
Internal Flash memory
Internal Flash memory
Overview
on-chip Flash composed matrix module bank Kbytes, named Bank0, that read modified. This module called IFlash because ST10 Internal bus. Figure Flash structure
IFlash Control Section Ref. generator
Bank Kbyte program memory Kbyte Test-Flash
Program/erase controller Flash control registers
I-BUS interface
X-BUS interface
programming operations Flash managed embedded Flash Program/Erase Controller (FPEC). high voltages needed Program/Erase operations generated internally. Data 32-bit wide fetch accesses IFlash. Read/write accesses IFlash Control Registers area 16-bit wide.
5.2.1
Functional description
Structure
Table below shows address space reserved Flash module. Table Flash module address space
Description IFlash sectors Registers Flash internal reserved area Addresses 0x00 0000 0x08 FFFF 0x0E 0000 0x0E FFFF Size Kbytes Kbytes
5.2.2
Module structure
IFlash module composed bank (Bank Kbytes program memory divided sectors (B0F0.B0F11). Bank also contains reserved sector named TestFlash.
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Addresses from 0x0E 0000 0x0E FFFF reserved Control Register Interface other internal service memory space used Flash Program/Erase controller. following tables show memory mapping Flash when accessed read mode (Table Flash module sectorization (read operations)), when accessed write erase mode (Table Flash module sectorization (write operations, ROMS1 `1')). Note: With this second mapping, first four sectors remapped into code segment (same obtained setting ROMS1 SYSCON register). Table
Bank
Flash module sectorization (read operations)
Description Bank Flash (B0F0) Bank Flash (B0F1) Bank Flash (B0F2) Bank Flash (B0F3) Bank Flash (B0F4) Bank Flash (B0F5) Addresses 0x00 0000 0x00 1FFF 0x00 2000 0x00 3FFF 0x00 4000 0x00 5FFF 0x00 6000 0x00 7FFF 0x01 8000 0x01 FFFF 0x02 0000 0x02 FFFF 0x03 0000 0x03 FFFF 0x04 0000 0x04 FFFF 0x05 0000 0x05 FFFF 0x06 0000 0x06 FFFF
Size (bytes)
Bank Flash (B0F6) Bank Flash (B0F7) Bank Flash (B0F8) Bank Flash (B0F9) Bank Flash (B0F10 B1F0) Bank Flash (B0F11 B1F1)
0x07 0000 0x07 FFFF 0x08 0000 0x08 FFFF
single bank implemented last sectors seen Bank order maintain compatibility with Flash Programming routines developed ST10F273E (based ST10F276E). This means that Control Status flags blocks B0F10 B0F11 duplicated also accessible blocks B1F0 B1F1.
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ST10F273M Table
Bank
Internal Flash memory Flash module sectorization (write operations, ROMS1 `1')
Description Bank Test-Flash (B0TF) Bank Flash (B0F0) Bank Flash (B0F1) Bank Flash (B0F2) Bank Flash (B0F3) Bank Flash (B0F4) Bank Flash (B0F5) Bank Flash (B0F6) Bank Flash (B0F7) Bank Flash (B0F8) Bank Flash (B0F9) Bank Flash (B0F10 B1F0) Bank Flash (B0F11 B1F1)
Addresses 0x00 0000 0x00 0FFF 0x01 0000 0x01 1FFF 0x01 2000 0x01 3FFF 0x01 4000 0x01 5FFF 0x01 6000 0x01 7FFF 0x01 8000 0x01 FFFF 0x02 0000 0x02 FFFF 0x03 0000 0x03 FFFF 0x04 0000 0x04 FFFF 0x05 0000 0x05 FFFF 0x06 0000 0x06 FFFF 0x07 0000 0x07 FFFF 0x08 0000 0x08 FFFF
Size (bytes)
single bank implemented last sectors seen Bank order maintain compatibility with Flash Programming routines developed ST10F273E (based ST10F276E). This means that Control Status flags blocks B0F10 B0F11 duplicated also accessible blocks B1F0 B1F1.
Table above refers configuration when ROMS1 SYSCON register set. When Bootstrap mode entered:
Test-Flash seen available code fetches (address 0x00 0000) User IFlash only available read write accesses Write accesses must made with addresses starting segment from 0x01 0000, whatever ROMS1 SYSCON value Read accesses made segment segment depending ROMS1 value.
Bootstrap mode, default ROMS1 first Kbytes IFlash mapped segment Example: default configuration, program address user must value 0x01 0000 FARL FARH registers verify content address read 0x00 0000 must performed. next Table shows Control Register interface composition: This registers addressed
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Internal Flash memory Table
Name FCR1 FDR1 FVWPIR-mirror FVWPIR FVAPR0 FVAPR1 XFICR
ST10F273M Flash control registers summary
Description Addresses Size byte byte byte byte byte byte byte byte byte 16-bit (XBus) size
Flash control registers High 0x0E 0000 0x0E 0007 Flash data registers High Flash address registers Flash error register Flash non-volatile protection registers mirrored 0x0E 0008 0x0E 000F 0x0E 0010 0x0E 0013 0x0E 0014 0x0E 0015 0x0E DFB0 0x0E DFB3
Flash volatile protection registers 0x0E DFB4 0x0E DFB7 Flash volatile access protection register Flash non-volatile access protection register XFlash Interface Control register (dummy register) 0x0E DFB8 0x0E DFB9 0x0E DFBC 0x0E DFBF 0x0E E000 0x0E E001
Note:
FVWPIR-mirror mirror FVWPIR maintain software compatibility with ST10F273E handling last blocks B0F10/B1F0 B0F11/B1F1. XFICR dummy register that read written (for compatibility with ST10F273E) content effect XBus timings.
5.2.3
power mode
Flash module automatically switched executing PWRDN instruction. consumption drastically reduced, exiting this state require long time (tPD). Recovery time from Power-down mode Flash modules anyway shorter than main oscillator start-up time. avoid problem restarting fetch code from Flash, important size properly external circuit pin.
Note:
PWRDN instruction must executed while Flash program/erase operation progress.
Write operation
Flash module single register interface mapped XBus memory space 0x0E 0000 0x0E 0015. operations enabled through four 16-bit control registers: Flash Control Register High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers used store Flash Address Data Program operations (FARH/L FDR1H/LFDR0H/L) Write Operation Error flags (FER). registers accessible with 16-bit instructions (since they mapped XBus).
Note: Caution:
have access Flash Control Registers used program/erasing operations, (XFLASHEN) XPERCON register must set. During Flash write operation attempt read IFlash will output invalid data 009Bh (corresponding, code fetch, software trap 009Bh). This means that
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ST10F273M
Internal Flash memory IFlash fetchable when programming operation active: write operation commands must executed from another memory (one on-chip RAMs some external memory).
Warning:
During Write operation, when LOCK FCR0 set, forbidden write into Flash Control Registers.
Power supply drop
during write operation internal voltage supply drops below certain internal voltage threshold, write operation running suddenly interrupted module reset Read mode. following Power-on, interrupted Flash write operation must repeated.
5.4.1
Flash control registers description
Flash control register (FCR0L)
Flash Control Register (FCR0L), together with Flash Control Register High (FCR0H), used enable monitor write operations IFlash. user access write mode Test-Flash (B0TF). Moreover, Test-Flash block seen user Bootstrap mode only.
FCR0L (0x0E 0000)
Reserved
DBSY
Reset value: 0000h
LOCK
Reserved
Table
15:7
FCR0L register description
Function Reserved. These bits must left their reset value (0). Dummy Bank1 Busy replication BSY0 bit: whenever write operation on-going. This emulating BSY1 ST10F273E device. When write operations going B0F10 and/or B0F11 blocks ST10F273M, this will order indicate that their equivalent B1F0 B1F1 ST10F273E busy. Bank0 Busy This bits indicate that write operation running Bank0. automatically when set. When this every read access Bank0 will output invalid data (software trap 009Bh), while every write access will ignored. write operation during Program Erase Suspend this automatically reset Flash Bank returns read mode. After Program Erase Resume this automatically again.
Name
DBSY1
BSY0
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Internal Flash memory Table
ST10F273M FCR0L register description (continued)
Function Flash registers access locked When this set, means that access Flash Control Registers FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L locked FPEC: read access registers will output invalid data (software trap 009Bh) write access will ineffective. LOCK automatically when Flash set. This only user always access detect status Flash: once found low, rest FCR0L other Flash registers accessible user well. Note that content read when LOCK low, content updated only when also BSYx bits reset. Reserved. These bits must left their reset value (0).
Name
LOCK
Busy Non-Volatile Registers This indicate that write operation running corresponding "Nonvolatile registers". They automatically when set. When this BSYNVR every read access IFlash will output value 009Bh (software trap), while every write access IFlash will ignored. write operation during Program Suspend this automatically reset IFlash returns read mode. After Program this automatically again. Reserved. This must left reset value (0).
5.4.2
Flash control register high (FCR0H)
Flash Control Register High (FCR0H) together with Flash Control Register (FCR0L) used enable monitor write operations IFlash. user access write mode Test-Flash (B0TF). Moreover, Test-Flash block seen user Bootstrap mode only.
FCR0H (0x0E 0002)
Reset value: 0000h
Reserved
SUSP
DWPG
Reserved
Table
Name
FCR0H register description
Function Write mode start This must start every write operation Flash module. write operation during Suspend, this automatically reset. resume suspended operation, this must again. forbidden this high (the operation accepted). also forbidden start write (program erase) operation setting high) when SUSP FCR0 high. Resetting this software effect.
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ST10F273M Table
Name
Internal Flash memory FCR0H register description (continued)
Function Suspend This must suspend current Program (Word Double Word) Sector Erase operation order read data another part Flash. Suspend operation resets Bank0 normal read mode (automatically resetting bits BSYx). When Program Suspend, Flash module accepts only following operations: Read Program Resume. When Erase Suspend module accepts only following operations: Read, Erase Resume. resume suspended operation, must again, together with selection corresponding operation resume (WPG, DWPG, SER).(1) Word program This must select Word bits) Program operation Flash module. Word Program operation allows program place Flash Address programmed must written FARH/L registers, while Flash Data programmed must written FDR0H/L registers before starting execution setting WMS. automatically reset Word Program operation. Double word program This must select Double Word bits) Program operation Flash module. Double Word Program operation allows program place Flash Address which program (aligned with even words) must written FARH/L registers, while Flash Data words programmed must written FDR0H/L registers (even word) FDR1H/L registers (odd word) before starting execution setting WMS. DWPG automatically reset Double Word Program operation. Sector erase This must select Sector Erase operation. Sector Erase operation allows erase Flash locations value 0xFFFF. From Bank0's sectors (excluding Test-Flash) selected erased through bits BxFy FCR1H/L registers before starting execution setting WMS. necessary preprogram sectors because this done automatically. automatically reset Sector Erase operation. Reserved. This must left their reset value (0). protection This must select Protection operation. Protection operation allows program place Flash Non-Volatile Protection Registers. Flash Address which program must written FARH/L registers, while Flash Data programmed must written FDR0H/L before starting execution setting WMS. sequence error flagged SEQER address written FARH/L range 0x0E DFB00x0E DFBF. automatically reset Protection operation.
SUSP
DWPG
10:9
Dummy Select Module This dummy SMOD that maintaining software compatibility with DSMOD ST10F273E where must before every Write Operation IFlash. effect ST10F273M. Reserved. These bits must kept their reset value (0).
forbidden start Write operation with SUSP already set.
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5.4.3
Flash control register (FCR1L)
Flash Control Register (FCR1L), together with Flash Control Register High (FCR1H), used select sectors erase during write operation, monitor status each sector bank.
FCR1L (0x0E 0004) Reset value: 0000h
Reserved
Table
15:12
FCR1L register description
Name Function Reserved. These bits must kept their default value (0). Bank0 IFlash sector 11:10 status These bits copy bits B0F10 B0F11 FCR1H. possible these bits well bits B0F10/B1F0 B0F11/B1F1 FCR1H. preserve compatibility with ST10F273E, these bits must left their default value FCR1H register must used. Bank IFlash sector status These bits must during Sector Erase operation select sectors erase Bank Besides, during erase operation, these bits automatically give status first sectors Bank (B0F9B0F0). meaning B0Fy Sector Bank given Table Bank (BxS) sectors (BxFy) status bits meaning. These bits automatically reset Write operation errors detected.
11:10
B0F11 B0F10
B0F9 B0F0
5.4.4
Flash control register high (FCR1H)
Flash Control Register High (FCR1H), together with Flash Control Register (FCR1L), used select sectors erase during write operation, monitor status each sector bank.
FCR1H (0x0E 0006) DB1S Reset value: 0000h
Reserved
Reserved
B0F11 B0F10 /B1F1 /B1F0
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ST10F273M Table
15:10
Internal Flash memory FCR1H register description
Name Function Reserved. These bits must kept their default value (0). Dummy Bank1 status This replication bit. order maintain compatibility with ST10F273E where operations last sectors were flagged this position. Bank0 status During erase operation, this automatically modified gives status Bank meaning given next Table Bank (BxS) sectors (BxFy) status bits meaning. This automatically reset erase operation errors detected. Reserved. These bits must kept their default value (0).
DB1S
Bank0 IFlash sector 11:10 status Bank1 IFlash sector status These bits must during Sector Erase operation select last sectors Bank0. Besides, during erase operation, these bits automatically give status last sectors Bank0 B0F10/B1F0 (B0F11-B0F10). meaning B0Fy Sector Bank given next Table Bank (BxS) sectors (BxFy) status bits meaning. B0F11/B1F1 These bits automatically reset Write operation errors detected. Note: These bits also seen selecting sectors Bank1 compatibility with ST10F273E.
Table
Bank (BxS) sectors (BxFy) status bits meaning
meaning BxFy meaning
Operation Erase Suspend Erase error Erase suspended bank Don't care Erase error sector Erase suspended sector bank Don't care
5.4.5
Flash data register (FDR0L)
During program operations, Flash Address Registers (FARH/L) used store Flash address which program Flash Data Registers (FDR1H/L-FDR0H/L) used store Flash data program.
FDR0L (0x0E 0008) Reset value: FFFFh
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Internal Flash memory Table
ST10F273M FDR0L register description
Function
Name
Data input 15:0 These bits must written with Data program Flash during following 15:0 DIN[15:0] operations: Word Program (32-bit), Double Word Program (64-bit) Protection.
5.4.6
Flash data register high (FDR0H)
FDR0H (0x0E 000A) Reset value: FFFFh
Table
FDR0H register description
Function
Name
Data input 31:16 These bits must written with Data program Flash during following 15:0 DIN[31:16] operations: Word Program (32-bit), Double Word Program (64-bit) Protection.
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Internal Flash memory
5.4.7
Flash data register (FDR1L)
FDR1L (0x0E 000C) Reset value: FFFFh
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
Table
FDR1L register description
Function Data input 15:0 These bits must written with Data program Flash during following operations: Double Word Program (64-bit) Protection.
Name
15:0 DIN[15:0]
5.4.8
Flash data register high (FDR1H)
FDR1H (0x0E 000E) Reset value: FFFFh
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
Table
FDR1H register description
Function Data input 31:16 These bits must written with Data program Flash during following operations: Double Word Program (64-bit) Protection.
Name
15:0 DIN[31:16]
5.4.9
Flash address register (FARL)
FARL (0x0E 0010) Reset value: 0000h
ADD15ADD14ADD13ADD12ADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 Reserved
Table
FARL register description
Function
Name
Address 15:2 These bits must written with Address Flash location program 15:2 ADD[15:2] during following operations: Word Program (32-bit) Double Word Program (64-bit). Double Word Program ADD2 must written `0'. Reserved. These bits must kept their default value (0).
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5.4.10
Flash address register high (FARH)
FARH (0x0E 0012) Reserved Reset value: 0000h
Table
FARH register description
Name ADD20 ADD6 Function Address 20:16 These bits must written with Address Flash location program during following operations: Word Program Double Word Program. Reserved. These bits must kept their default value (0).
15:5
5.4.11
Flash error register (FER)
Flash error register, well other Flash registers, read only once LOCK register FCR0L low. Nevertheless, content updated after completion Flash operation, that when BSYx bits reset. Therefore, content only read once LOCK BSYx bits cleared.
(0xE 0014h)
Reserved
Reset value: 0000h
RESER SEQER
Reserved
10ER PGER ERER
Table
15:9
register bits
Name Function Reserved. These bits must kept their default value (0). Write protection flag This automatically when trying program erase sector write protected. case multiple Sector Erase, protected sectors erased, while protected sectors erased set. This must cleared software. Resume error This automatically when suspended Program Erase operation resumed correctly protocol error. this case suspended operation aborted. This must cleared software. Sequence error This automatically when control registers (FCR1H/L-FCR0H/L, FARH/L, FDR1H/L-FDR0H/L) correctly filled execute valid Write Operation. this case Write Operation executed. This must cleared software. Reserved. These bits must kept their default value (0).
RESER
SEQER
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ST10F273M Table
Internal Flash memory register bits (continued)
Name Function over error This automatically when trying program bits previously (this does happen when programming Protection bits). This error failure Flash cell, only flags that desired data been written. This must cleared software. Program error This automatically when Program error occurs during Flash write operation. This error real failure Flash cell, that more programmed. word where this error occurred must discarded. This must cleared software. Erase error This automatically when Erase error occurs during Flash write operation. This error real failure Flash cell, that more erased. This kind error fatal sector where occurred must discarded. This must cleared software. Write error This automatically when error occurs during Flash write operation when write operation setup done. Once error been discovered understood, must cleared software.
10ER
PGER
ERER
5.4.12
XFlash interface control dummy register (XFICR)
XFICR (0x0E E0000) Reset value: 0007h
Reserved
Table
XFlash interface control register
Name Function
Dummy Wait States ST10F273E, these bits were used configure number waitWS3.WS0 states access XFlash. there XFlash ST10F273M, these bits have effect. This register implemented software compatibility with ST10F273E. Reserved. These bits must kept their default value (0).
15:4
Protection strategy
protection bits stored Non-Volatile Flash cells that read once reset stored five Volatile registers. Before they read from Non-Volatile cells, available protections forced active during reset.
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Internal Flash memory Note:
ST10F273M
protection bits Non-Volatile registers programmable time this programing permanent. Temporary unprotection will handled with their Volatile equivalent. protections programmed using Protection operation (see Section 5.4: Flash control registers description) that must executed from on-chip RAMs from external memories. kind protections available:
write protections avoid unwanted writings access protections avoid piracy
next sections show different level protections highlight architecture limitations.
5.5.1
Protection registers
five Non-Volatile Protection Registers one-time programmable user. registers, FVWPIRL FVWPIRH, used store Write Protection fuses each sector IFlash module. other three registers (FNVAPR0 FNVAPR1L/H) used store Access Protection fuses.
Note:
On-going protection operations flagged with BSYNVR, FCR0L register.
5.5.2
Flash non-volatile write protection register (FNVWPIRL)
FNVWPIRL (0x0E DFB4) Delivery value: FFFFh
Reserved
Table
15:12
FNVWPIRL register bits
Name Function Reserved. These bits must left their default value when programming PVWPIRL. Read-Only Write protection Bank0 sectors These bits must left their default value when programming FVWPIRL (they used write protection sectors B0F11 B0F10). After protection command, these bits will reflect value FVWPIRH register (W0P11 W0P10). Write protection bank sectors These bits, programmed disable write access sectors Bank (IFlash).
11:10
W0P11 W0P10
W0P9 W0P0
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Internal Flash memory
5.5.3
Flash non-volatile write protection register high (FNVWPIRH)
FNVWPIRH (0x0E DFB6) Delivery value: FFFFh
Reserved
W0P11- W0P10W1P1 W1P0
Table
15:2
FNVWPRIH register bits
Name Function Reserved. These bits must left their default value `1'. Write protection Bank0 sectors 11:10 Write protection Bank1 sectors These bits, programmed disable write access selected sectors.
W0P11/W1P1 W0P10/W1P0
5.5.4
Flash non-volatile write protection register Mirror (FNVWPIRL-m)
FNVWPIRL-m (0x0E DFB0) Delivery value: FFFFh
Reserved
This register mirroring register FVWPIRL (address 0x0E DFB4). intended maintain software compatibility with ST10F273E. applications ported from ST10F273E, FVWPIRL-m register (address 0x0E DFB0) must used maintain existing Flash drivers. applications ported from ST10F272x, FVWPIRL register (address 0x0E DFB4) must used maintain existing drivers.
5.5.5
Flash non-volatile write protection register high Mirror (FVWPIRH-m)
FVWPIRH-m (0x0E DFB2 Delivery value: FFFFh
Reserved
W0P11- W0P10W1P1 W1P0
This register mirroring register FVWPIRH (address 0x0E DFB6). intended maintain software compatibility with ST10F273E. applications ported from ST10F273E, FVWPIRH-m register (address 0x0E DFB2) must used maintain existing Flash drivers. applications ported from ST10F272x, FVWPIRH register (address 0x0E DFB6) must used maintain existing drivers.
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Internal Flash memory
ST10F273M
5.5.6
Flash non-volatile access protection register (FNVAPR0)
FNVAPR0 (0x0E DFB8) Delivery value: ACFFh
Reserved
DBGP ACCP
Table
15:2
FNVAPR0 register bits
Name Description Reserved. These bits must left their default value. Debug protection This bit, erased allows bypass protections using Debug features through Test Interface. programmed contrary, debug features, Test Interface Flash Test modes disabled. Even STMicroelectronics will able access device eventual failure analysis. Access protection This bit, programmed disables access (read/write) data mapped inside IFlash Module address space, unless current instruction fetched from IFlash.
DBGP
ACCP
5.5.7
Flash non-volatile access protection register (FNVAPR1L)
FNVAPR1L (0x0E DFBC) Delivery value: FFFFh
PDS1 PDS1 PDS1 PDS1 PDS1 PDS1
Table
FNVAPR1L register bits
Function Protections disable15-0 PDSx programmed PENx erased action ACCP disabled. PDS0 programmed only both bits DBGP ACCP have already been programmed PDSx programmed only PENx-1 already been programmed
Name
15:0
PDS15 PDS0
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ST10F273M
Internal Flash memory
5.5.8
Flash non-volatile access protection register high (FNVAPR1H)
FNVAPR1H (0x0E DFBE)
Delivery value: FFFFh
PEN1 PEN1 PEN1 PEN1 PEN1 PEN1
Table
FNVAPR1H register bits
Function Protections enable 15-0 PENx programmed PDSx+1 erased action ACCP enabled again. PENx programmed only PDSx already been programmed
Name PEN15 PEN0
15:0
5.5.9
Access protection
IFlash module level access protection (access data both Reading Writing): ACCP FNVAPR0 programmed IFlash module becomes access protected, meaning data IFlash module read only current execution from IFlash module itself. Protection permanently disabled programming PDS0 FNVAPR1H (user operation before returning parts STMicroelectronics analysis). Protection permanently enabled again programming PEN0 FNVAPR1L. action disable enable again Access Protections permanent executed maximum times. Trying write into access protected Flash from internal external memories will unsuccessful. Trying read into access protected Flash from internal external memories will output dummy data (software trap 009Bh). When Flash module protected access, data access through peripheral also forbidden. read/write data mode from/to protected Bank, necessary first temporarily unprotect Flash module. following table summarizes possible Access Protection levels: particular, shows what possible possible when fetching from memory (see fetch location column) supposing possible access protections enabled. Table Summary access protection level
Read IFlash Jump IFlash Read XRAM external memory Jump XRAM external memory Read Flash registers Write Flash registers
Fetch location
Fetching from IFlash Fetching from IRAM
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Internal Flash memory Table Summary access protection level (continued)
Read IFlash Jump IFlash Read XRAM external memory Jump XRAM external memory Read Flash registers
ST10F273M
Fetch location
Write Flash registers
Fetching from XRAM Fetching from external memory
5.5.10
Write protection
Flash modules have level Write Protections: Each sector Software Write Protected programming related WyPx FNVWPIRL/H register.
5.5.11
Temporary unprotection
Bits WyPx FNVWPIRL/H temporarily unprotected executing Protection operation writing into these bits. ACCP temporarily unprotected executing Protection operation writing executed from IFlash. restore write access protection bits necessary reset microcontroller execute Protection operation write into desired bits. reality, when temporary unprotection operation executed, corresponding volatile register written while non-volatile registers bits previously written (for protection operation), will continue maintain this reason, user software must charge track current protection status (for instance using specific area), possible deduce reading non-volatile register content temporary unprotection cannot detected).
Write operation examples
following, examples each kind Flash write operation presented. examples showing sequence instructions needed start operation. Write operations should followed status check (FER register).
Note:
After write operation started, Flash control registers accessible short time. LOCK bit, FCR0L register, must polled order know when Flash control registers accessed again (LOCK `1': access Flash control registers). Write operation IBus registers bits wide.
Word program
Example: 32-bit Word Program data 0xAAAAAAAA address 0x025554 FCR0H|= FARL FARH FDR0L FDR0H 0x2000; 0x5554; 0x0002; 0xAAAA; 0xAAAA; /*Set FCR0H*/ /*Load FARL*/ /*Load FARH*/ /*Load Data FDR0L*/ /*Load Data FDR0H*/
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ST10F273M FCR0H|= 0x8000; /*Operation start*/
Internal Flash memory
Double word program
Example: Double Word Program (64-bit) data 0x55AA55AA address 0x035558 data 0xAA55AA55 address 0x03555C. FCR0H FARL FARH FDR0L FDR0H FDR1L FDR1H FCR0H 0x1000; 0x5558; 0x0003; 0x55AA; 0x55AA; 0xAA55; 0xAA55; 0x8000; /*Set DWPG FCR0H*/ /*Load FARL*/ /*Load FARH*/ /*Load Data FDR0L*/ /*Load Data FDR0H*/ /*Load Data FDR1L*/ /*Load Data FDR1H*/ /*Operation start*/
Double Word Program always performed Double Word aligned even Word: ADD2 FARL ignored.
Sector erase
Example: Sector Erase sectors B0F1 B0F0 Bank FCR0H FCR1L FCR0H 0x0800; 0x0003; 0x8000; /*Set FCR0H*/ /*Set B0F1, B0F0*/ /*Operation start*/
Suspend resume
Word Program, Double Word Program, Sector Erase operations suspended following way: FCR0H 0x4000; /*Set SUSP FCR0H*/
Then operation resumed following way: FCR0H FCR0H 0x0800; 0x8000; /*Set FCR0H*/ /*Operation resume*/
Before resuming suspended Erase, FCR1H/FCR1L must read check Erase already completed (FCR1H FCR1L 0x0000 Erase complete). Original setup Select Operation bits FCR0H/L must restored before operation resume, otherwise operation aborted RESER set.
protection
Example Enable Write Protection sectors B0F3-0 Bank FCR0H FARL FARH FDR0L FDR0H FCR0H 0x0100; 0xDFB4; 0x000E; 0xFFF0; 0xFFFF; 0x8000; /*Set FCR0H*/ /*Load register FNVWPIR FARL*/ /*Load register FNVWPIR FARH*/ /*Load Data FDR0L*/ /*Load Data FDR0H*/ /*Operation start*/
Example Enable Access Debug Protection. FCR0H 0x0100; /*Set FCR0H*/
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Internal Flash memory FARL FARH FDR0L FCR0H 0xDFB8; 0x000E; 0xFFFC; 0x8000;
ST10F273M /*Load register FNVAPR0 FARL*/ /*Load register FNVAPR0 FARH*/ /*Load Data FDR0L*/ /*Operation start*/
Example Disable permanent Access Debug Protection. FCR0H FCR0H FARL FARH FDR0L FCR0H 0x0100; 0x0100; 0xDFBC; 0x000E; 0xFFFE; 0x8000; /*Set FCR0H*/ /*Set FCR0H*/ /*Load register FNVAPR1L FARL*/ /*Load register FNVAPR1L FARH*/ /*Load Data FDR0L clearing PDS0*/ /*Operation start*/
Example Enable again permanent Access Debug Protection, after having disabled them. FCR0H|= 0x0100; /*Set FCR0H*/ FARL 0xDFBC; /*Load register FNVAPR1H FARL*/ FARH 0x000E; /*Load register FNVAPR1H FARH*/ FDR0H 0xFFFE; /*Load Data FDR0H clear PEN0*/ FCR0H 0x8000; /*Operation start*/ Disable re-enable Access Debug Protection permanent shown examples done maximum times.
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ST10F273M
Internal Flash memory
Write operation summary
general, each write operation started through sequence three steps: first instruction used select desired operation setting corresponding selection Flash Control Register second step definition Address Data programming sectors erase. last instruction used start write operation, setting start FCR0. This last instruction must executed from Flash.
Once selected, started, operation canceled resetting operation selection bit. Available Flash Module Write Operations summarized following Table Table Flash write operations
Operation Word Program (32-bit) Select Address data FARL/FARH FDR0L/FDR0H FARL/FARH FDR0L/FDR0H FDR1L/FDR1H FCR1L/FCR1H FDR0L/FDR0H None None Start
Double Word Program (64-bit) Sector Erase Protection Program/Erase Suspend
DWPG SUSP
Figure shows complete flow needed Write operation. Figure Write operation control flow
Start Write Operation
FCR0L.LOCK
Write Operation finished?
(Check related busy bit)
Check Error Status Error:
Error handler, Re-start operation
error:
Proceed with application
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Bootstrap loader
ST10F273M
Bootstrap loader
ST10F273M implements Boot capabilities order
Support bootstrap UART bootstrap standard bootstrap Support Selective Bootstrap Loader, manage bootstrap sequence different
Selection among user-code, standard selective bootstrap
boot modes triggered with special combination Port0L[5.4]. Those signals, other configuration signals, latched rising edge RSTIN pin.
Decoding reset configuration (P0L.5 P0L.4 selects normal mode (also called User mode) selects user Flash mapped from address 00'0000h. Decoding reset configuration (P0L.5 P0L.4 selects ST10 standard bootstrap mode (Test-Flash active overlaps user Flash code fetches from address 00'0000h; user Flash active available read accesses). Decoding reset configuration (P0L.5 P0L.4 activates additional verifications select which bootstrap software execute: User mode signature User Flash programmed correctly, then software reset sequence selected User code executed; User mode signature programmed correctly user Flash, then User location read again. value determines which communication channel will enabled bootstrapping. ST10F273M boot mode selection
P0.4 ST10 decoding User mode: User Flash mapped 00'0000h Standard Bootstrap Loader: User Flash mapped from 00'0000h, code fetches redirected Test-Flash 00'0000h Selective Boot mode: User Flash mapped from 00'0000h, code fetches redirected Test-Flash 00'0000h (different sequence execution compared Standard Bootstrap Loader) Reserved
Table
P0.5
Standard bootstrap loader
After entering standard mode respective initialization, ST10F273M scans RxD0 line CAN1_RxD line receive either valid dominant from interface start condition from UART line. Start condition UART RxD: ST10F273M starts standard bootstrap loader. This bootstrap loader identical that other ST10 devices (example: ST10F269, ST10F168). Valid dominant CAN1 RxD: ST10F273M start bootstrapping CAN1.
Caution:
both UART_RxD CAN1_RxD lines polled detect start communication, ensure stable level unused channel adding pull-up resistor.
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ST10F273M
Bootstrap loader
6.3.1
Alternate selective boot mode (ABM SBM)
Activation
Alternate boot activated with combination `01' Port0L[5.4] rising edge RSTIN.
6.3.2
User mode signature integrity check
behavior Selective Boot mode based computing signature between content memory locations comparison with reference signature. This requires that users Selective Boot have reserved programmed Flash memory locations.
6.3.3
Selective boot mode
When user signature correct, instead executing Standard Bootstrap Loader (triggered P0L.4 reset), additional check made. Depending value User location, following behavior occurs:
jump performed Standard Bootstrap Loader Only UART enabled bootstrapping Only CAN1 enabled bootstrapping device enters infinite loop
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Central processing unit (CPU)
ST10F273M
Central processing unit (CPU)
includes 4-stage instruction pipeline, 16-bit arithmetic logic unit (ALU) dedicated SFRs. Additional hardware been added separate multiply divide unit, bit-mask generator barrel shifter. Most ST10F273M's instructions executed instruction cycle which requires 50ns clock. example, shift rotate instructions processed instruction cycle independent number bits shifted. Multiple-cycle instructions have been optimized: branches carried cycles, 16-bit multiplication cycles 32-/16-bit division cycles. jump cache reduces execution time repeatedly performed jumps loop, from cycles cycle. uses bank word registers current context. This bank General Purpose Registers (GPR) physically stored within on-chip Internal (IRAM) area. Context Pointer (CP) register determines base address active register bank accessed CPU. number register banks only restricted available Internal space. easy parameter passing, register bank overlap others. system stack 2048 bytes provided storage temporary data. system stack allocated on-chip area, accessed stack pointer (SP) register. separate SFRs, STKOV STKUN, implicitly compared against stack pointer value upon each stack access detection stack overflow underflow. Figure block diagram (MAC unit included)
STKOV STKUN Mul./Div.-HW Bit-Mask Gen. General Purpose Registers
Kbyte Internal
Bank
Kbyte Flash memory
Exec. Unit Instr. 4-Stage Pipeline SYSCON BUSCON BUSCON BUSCON BUSCON BUSCON Data Ptrs
16-Bit Barrel-Shift ADDRSEL ADDRSEL ADDRSEL ADDRSEL Code Seg. Ptr.
Bank
Bank
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ST10F273M
Central processing unit (CPU)
Multiplier-accumulator unit (MAC)
co-processor specialized co-processor added ST10 Core order improve performances ST10 Family signal processing algorithms. standard ST10 been modified include addressing capabilities which enable supply co-processor with operands instruction cycle. This co-processor (so-called MAC) contains fast multiply-accumulate unit repeat unit. co-processor instructions extend ST10 instruction with multiply, multiplyaccumulate, 32-bit signed arithmetic operations. Figure unit architecture
Operand Operand
Pointers IDX0 pointer IDX1 pointer offset register offset register offset register offset register
Concatenation
signed/unsigned multiplier
Sign Extend Repeat unit Interrupt controller ST10 Flags Control Unit 8-bit left/right shifter Scaler 08000h
40-bit signed arithmetic unit
Shared with standard
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Central processing unit (CPU)
ST10F273M
Instruction summary
Table lists instructions ST10F273M. detailed description each instruction found ST10 Family Programming Manual. Table Standard instruction summary
Description word (byte) operands word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct direct (16-/16-bit) (Un)Signed divide register direct (16-/16-bit) (Un)Signed long divide reg. direct (32-/16-bit) Complement direct word (byte) Negate direct word (byte) Bitwise AND, (word/byte operands) Bitwise (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct direct Move (negated) direct direct AND/OR/XOR direct with direct Compare direct direct Bitwise modify masked high/low byte bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data decrement Compare word data increment Determine number shift cycles normalize direct word store result direct word Shift left/right direct word Rotate left/right direct word Arithmetic (sign bit) shift right direct word Move word (byte) data Move byte operand word operand with sign extension Move byte operand word operand with zero extension Jump absolute/indirect/relative condition Jump absolute code segment Bytes
Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS
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ST10F273M Table
Central processing unit (CPU) Standard instruction summary (continued)
Description Jump relative direct (not) Jump relative clear direct Jump relative direct Call absolute/indirect/relative subroutine condition Call absolute subroutine code segment Push direct word register onto system stack call absolute subroutine Call interrupt service routine immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle mode Enter Power-down mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes
Mnemonic J(N)B JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, SCXT RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R)
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Central processing unit (CPU)
ST10F273M
co-processor specific instructions
Table lists instructions ST10F273M. detailed description each instruction found ST10 Family Programming Manual. Note that instructions encoded bytes. Table instruction summary
Mnemonic CoABS CoADD(2) CoASHR(rnd) CoCMP CoLOAD(-,2) CoMAC(R,u,s,-,rnd) CoMACM(R)(u,s,-,rnd) CoMAX CoMIN CoMOV CoMUL(u,s,-,rnd) CoNEG(rnd) CoNOP CoRND CoSHL CoSHR CoSTORE CoSUB(2,R) Description Absolute value accumulator Addition Accumulator arithmetic shift right optional round Compare accumulator with operands Load accumulator with operands (Un)signed/(Un)Signed Multiply-Accumulate Optional Round (Un)Signed/(Un)signed multiply-accumulate with parallel data move optional round maximum minimum operands accumulator Memory memory move (Un)signed/(Un)signed multiply optional round Negate accumulator optional round No-operation Round accumulator Accumulator logical shift left right Store unit register Subtraction
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ST10F273M
External controller
External controller
external memory accesses performed on-chip external controller. programmed single chip mode when external memory required, four different external memory access modes:
24-bit addresses 16-bit data, demultiplexed 24-bit addresses 16-bit data, multiplexed 24-bit addresses 8-bit data, multiplexed 24-bit addresses 8-bit data, demultiplexed
demultiplexed modes addresses output PORT1 data input output PORT0 P0L, respectively. multiplexed modes both addresses data PORT0 input output. Timing characteristics external interface (memory cycle time, memory tri-state time, length read write delay) programmable giving choice wide range memories external peripherals. four independent address windows defined (using register pairs ADDRSELx BUSCONx) access different resources characteristics. These address windows arranged hierarchically where BUSCON4 overrides BUSCON3 BUSCON2 overrides BUSCON1. accesses locations covered these four address windows controlled BUSCON0. five external signals (four windows plus default) generated order save external glue logic. Access very slow memories supported `Ready' function. HOLD HLDA protocol available arbitration which shares external resources with other masters. arbitration enabled setting HLDEN register PSW. After setting HLDEN once, pins P6.7.P6.5 (BREQ, HLDA, HOLD) automatically controlled EBC. master mode (default after reset) HLDA output. setting DP6.7 slave mode selected where HLDA switched input. This directly connects slave controller another master controller without glue logic. applications which require less external memory space, address space restricted Mbyte, Kbytes Kbytes. Port outputs eight address lines address space Mbytes used, otherwise four, address lines. Chip select timing made programmable. default (after reset), lines change half clock cycle after rising edge ALE. With CSCFG SYSCON register lines change with rising edge ALE. active level READY RDYPOL BUSCONx registers. When READY function enabled specific address window, each cycle within window must terminated with active level defined RDYPOL associated BUSCON register.
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Interrupt system
ST10F273M
Interrupt system
interrupt response time internal program execution from 125ns 300ns clock. ST10F273M architecture supports several mechanisms fast flexible response service requests that generated from various sources (internal external) microcontroller. these interrupt requests serviced Interrupt Controller Peripheral Event Controller (PEC). contrast standard interrupt service where current program execution suspended branch interrupt vector table performed, just cycle `stolen' from current activity perform service. service implies single Byte Word data transfer between memory locations with additional increment either source destination pointer. individual transfer counter implicitly decremented each service except when performing continuous transfer mode. When this counter reaches zero, standard interrupt performed corresponding source related vector location. services very well suited perform transmission reception blocks data. ST10F273M eight channels, each them offers such fast interrupt-driven data transfer capabilities. interrupt control register which contains interrupt request flag, interrupt enable flag interrupt priority bit-field dedicated each existing interrupt source. Thanks related register, each source programmed sixteen interrupt priority levels. Once starting processed CPU, interrupt service only interrupted higher prioritized service request. standard interrupt processing, each possible interrupt sources dedicated vector location. Software interrupts supported means `TRAP' instruction combination with individual trap (interrupt) number. Fast external interrupt inputs provided service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge both edges). Fast external interrupts also have interrupt sources selected from other peripherals; example CANx controller receive signals (CANx_RxD) serial clock signal used interrupt system. Table shows available ST10F273M interrupt sources corresponding hardware-related interrupt flags, vectors, vector locations trap (interrupt) numbers. Table Interrupt sources
Request flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR Enable flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE Interrupt vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT Vector location 00'0040h 00'0044h 00'0048h 00'004Ch 00'0050h 00'0054h Trap number
Source interrupt service request CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register
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ST10F273M Table Interrupt sources (continued)
Request flag CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR T1IR T7IR T8IR T2IR T3IR T4IR T5IR Enable flag CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE T1IE T7IE T8IE T2IE T3IE T4IE T5IE Interrupt vector CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT T1INT T7INT T8INT T2INT T3INT T4INT T5INT
Interrupt system
Source interrupt service request CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Timer CAPCOM Timer CAPCOM Timer CAPCOM Timer GPT1Timer GPT1 Timer GPT1 Timer GPT2Timer
Vector location 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h 00'00C8h 00'00CCh 00'00D0h 00'00D4h 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00F0h 00'0110h 00'0114h 00'0118h 00'0080h 00'0084h 00'00F4h 00'00F8h 00'0088h 00'008Ch 00'0090h 00'0094h
Trap number
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Interrupt system Table Interrupt sources (continued)
Request flag T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR Enable flag T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE Interrupt vector T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT Vector location 00'0098h 00'009Ch 00'00A0h 00'00A4h 00'00A8h 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch
ST10F273M
Source interrupt service request GPT2 Timer GPT2 CAPREL Register Conversion Complete Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error Transmit Receive Error Channel Section Section Section Section
Trap number
Hardware traps exceptions error conditions that arise during run-time. They cause immediate non-maskable system reaction similar standard interrupt service (branching dedicated vector table location). occurrence hardware trap additionally signified individual trap flag register (TFR). hardware trap will interrupt other program execution except when another higher prioritized trap service progress. Hardware trap services cannot interrupted standard interrupt interrupts.
X-Peripheral interrupt
limited number X-Bus interrupt lines present ST10 architecture, imposes some constraints implementation functionality. particular, additional XPeripherals SSC1, ASC1, I2C, PWM1 need some resources implement interrupt transfer capabilities. this reason, multiplexed structure interrupt management proposed. next Figure principle explained through simple diagram, which shows basic structure replicated each four X-interrupt available vectors (XP0INT, XP1INT, XP2INT XP3INT). based 16-bit registers XIRxSEL 0,1,2,3), divided portions each:
Byte High Byte
XIRxSEL[15:8] XIRxSEL[7:0]
Interrupt Enable bits Interrupt Flag bits
When different sources submit interrupt request, enable bits (Byte High XIRxSEL register) define mask which controls which sources will associated with unique
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ST10F273M
Interrupt system available vector. more than source enabled issue request, service routine will have take care identify real event serviced. This easily done checking flag bits (Byte XIRxSEL register). Note that flag bits also provide information about events which currently serviced interrupt controller (since masked through enable bits), allowing effective software management also absence possibility serve related interrupt request: periodic polling flag bits implemented inside user application. Figure X-Interrupt basic structure
Flag[7:0] Source Source Source Source Source Source Source Source Enable[7:0] XIRxSEL[15:8] XPxIC.XPxIR XIRxSEL[7:0]
Table summarizes mapping different interrupt sources which shares four Xinterrupt vectors. Table X-Interrupt detailed mapping
Interrupt source CAN1 Interrupt CAN2 Interrupt Receive Transmit Error SSC1 Receive SSC1 Transmit SSC1 Error ASC1 Receive ASC1 Transmit ASC1 Transmit Buffer ASC1 Error Unlock PWM1 Channel
XP0INT
XP1INT
XP2INT
XP3INT
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Interrupt system
ST10F273M
Exception error traps list
Table shows possible exceptions error conditions that arise during runtime. Table Trap priorities
Trap flag Trap vector RESET RESET RESET STKOF STKUF UNDOPC MACTRP PRTFLT ILLOPA ILLINA ILLBUS NMITRAP STOTRAP STUTRAP BTRAP BTRAP BTRAP BTRAP BTRAP BTRAP Vector location 00'0000h 00'0000h 00'0000h 00'0008h 00'0010h 00'0018h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [002Ch 003Ch] 0000h 01FCh steps Trap number [0Bh 0Fh] [00h 7Fh] Current Priority Trap priority(1)
Exception condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class Hardware Traps: Undefined Opcode Interruption Protected Instruction Fault Illegal word Operand Access Illegal Instruction Access Illegal External Access Reserved Software Traps TRAP Instruction
class traps have same trap number (and vector) same lower priority compared class traps resets. Each class trap dedicated trap number (and vector). They prioritized second priority level. resets have highest priority level same trap number. PSW.ILVL priority forced highest level (15) when these exceptions serviced.
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ST10F273M
Capture compare (CAPCOM) units
Capture compare (CAPCOM) units
ST10F273M 16-channel CAPCOM units which support generation control timing sequences channels with maximum resolution 200ns clock. CAPCOM units typically used handle high speed tasks such pulse waveform generation, pulse width modulation (PMW), digital analog (D/A) conversion, software timing, time recording relative external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide independent time bases capture/compare register array. input clock timers programmable several prescaled values internal system clock, derived from overflow/underflow timer module GPT2. This provides wide range variation timer period resolution allows precise adjustments application specific requirements. addition, external count inputs CAPCOM timers allow event scheduling capture/compare registers relative external events. Each capture/compare register arrays contain dual purpose capture/compare registers, each which individually allocated either CAPCOM timer respectively), programmed capture compare functions. Each registers associated port which serves input triggering capture function, output indicate occurrence compare event. When capture/compare register been selected capture mode, current contents allocated timer will latched (captured) into capture/compare register response external event port which associated with this register. addition, specific interrupt request this capture/compare register generated. Either positive, negative, both positive negative external signal transition selected triggering event. contents registers which have been selected five compare modes continuously compared with contents allocated timers. When match occurs between timer value value capture compare register, specific actions will taken based selected compare mode. input frequencies fTx, timer input selector determined function clocks. timer input frequencies, resolution periods which result from selected prescaler option when using clock listed Table numbers timer periods based reload value 0000h. Note that some numbers rounded three significant figures.
Table
Compare modes
Function Interrupt-only compare mode; several compare interrupts timer period possible toggles each compare match; several compare events timer period possible Interrupt-only compare mode; only compare interrupt timer period generated
Compare modes Mode Mode Mode
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Capture compare (CAPCOM) units Table Compare modes (continued)
Function
ST10F273M
Compare modes Mode Double Register mode
match; reset compare time overflow; only compare event timer period generated registers operate pin; toggles each compare match; several compare events timer period possible.
Table
CAPCOM timer input frequencies, resolutions periods
Timer input selection
fCPU 000b Prescaler fCPU Input frequency Resolution Period 200ns 13.1ms 001b 400ns 26.2ms 010b 1.25 0.8µs 52.4ms 011b 1.6µs 104.8ms 100b 101b 110b 111b 1024 39.1 25.6µs 1.678s
312.5 156.25 78.125 3.2µs 209.7ms 6.4µs 419.4ms 12.8µs 838.9ms
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ST10F273M
General purpose timer unit
General purpose timer unit
unit flexible multifunctional timer/counter structure which used time related tasks such event timing counting, pulse width duty cycle measurements, pulse generation, pulse multiplication. unit contains five 16-bit timers organized into separate modules GPT1 GPT2. Each timer each module operate independently several different modes, concatenated with another timer same module.
11.1
GPT1
Each three timers GPT1 module configured individually four basic modes operation: timer, gated timer, counter mode incremental interface mode. timer mode, input clock timer derived from clock, divided programmable prescaler. counter mode, timer clocked reference external events. Pulse width duty cycle measurement supported gated timer mode where operation timer controlled `gate' level external input pin. these purposes, each timer associated port (TxIN) which serves gate clock input. Table lists timer input frequencies, resolution periods each prescaler option clock. Incremental Interface mode, GPT1 timers (T2, directly connected incremental position sensor signals their respective inputs TxIN TxEUD. Direction count signals internally derived from these input signals that contents respective timer corresponds sensor position. third position sensor signal TOP0 connected interrupt input. Timer output toggle latches (TxOTL) which changes state each timer over flow underflow. state this latch output port pins (TxOUT) time monitoring external hardware components, used internally clock timers high resolution long duration measurements. addition their basic operating modes, timers configured reload capture registers timer
Table
GPT1 timer input frequencies, resolutions periods
Timer input selection
fCPU 000b Prescaler factor Input frequency Resolution Period maximum 200ns 13.1ms 001b 400ns 26.2ms 010b 1.25 0.8µs 52.4ms 011b 1.6µs 104.8ms 100b 101b 110b 111b 1024 39.1 25.6µs 1.678s
312.5 156.25 78.125 3.2µs 209.7ms 6.4µs 419.4ms 12.8µs 838.9ms
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General purpose timer unit Figure Block diagram GPT1
T2EUD clock T2IN GPT1 timer n=3.10
ST10F273M
mode control
Interrupt request
Reload Capture
clock T3IN T3EUD
n=3.10
mode control
T3OUT GPT1 timer Capture T3OTL
T4IN clock n=3.10
mode control
Reload
Interrupt request Interrupt request
GPT1 timer T4EUD
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ST10F273M
General purpose timer unit
11.2
GPT2
GPT2 module provides precise event control time measurement. includes timers (T5, capture/reload register (CAPREL). Both timers clocked with input clock which derived from clock programmable prescaler with external signals. count direction (up/down) each timer programmable software additionally altered dynamically external signal port (TxEUD). Concatenation timers supported output toggle latch (T6OTL) timer which changes state each timer overflow/underflow. state this latch used clock timer output port (T6OUT). overflow underflow timer additionally used clock CAPCOM timers cause reload from CAPREL register. CAPREL register capture contents timer based external signal transition corresponding port (CAPIN), timer optionally cleared after capture procedure. This allows absolute time differences measured pulse multiplication performed without software overhead. capture trigger (timer CAPREL) also generated upon transitions GPT1 timer inputs T3IN and/or T3EUD. This advantageous when operates Incremental Interface mode. Table lists timer input frequencies, resolution periods each prescaler option clock.
Table
GPT2 timer input frequencies, resolutions periods
Timer Input Selection
fCPU 000b Prescaler factor Input frequency Resolution Period maximum 100ns 6.55ms 001b 200ns 13.1ms 010b 400ns 26.2ms 011b 1.25 0.8µs 52.4ms 100b 1.6µs 104.8ms 101b 110b 111b
312.5 156.25 78.125 3.2µs 209.7ms 6.4µs 419.4ms 12.8µs 838.9ms
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General purpose timer unit Figure Block diagram GPT2
T5EUD clock T5IN n=2.9 mode control GPT2 timer Clear Capture CAPIN GPT2 CAPREL
ST10F273M
Interrupt request
Interrupt request
Reload
Interrupt request
T6IN clock T6EUD n=2.9
Toggle mode control GPT2 timer T60TL T6OUT CAPCOM timers
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ST10F273M
modules
modules
pulse width modulation modules available ST10F273M: standard PWM0 XBUS PWM1. They generate four output signals each, using edge-aligned center-aligned PWM. addition, modules generate burst signals single shot outputs. Table shows frequencies different resolutions. level output signals selectable modules generate interrupt requests. Figure Block diagram module
period register Match
Comparator
Clock Clock
Input control
16-bit up/down counter
Up/down/ clear control
Comparator
Match
Output control Enable
POUTx
Shadow register
Write control
pulse width register User readable writeable register
Table
Mode
unit frequencies resolutions clock
Resolution 25ns 1.6µs Resolution 25ns 1.6µs 8-bit 156.25 2.44 8-bit 78.12 1.22 10-bit 39.1 10-bit 19.53 305.17Hz 12-bit 9.77 152.6 12-bit 4.88 76.29 14-bit 2.44 38.15 14-bit 1.22 19.07 16-bit 9.54 16-bit 305.2 4.77
Clock/1 Clock/64 Mode Clock/1 Clock/64
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Parallel ports
ST10F273M
13.1
Parallel ports
Introduction
ST10F273M provides lines with programmable features. These capabilities permit this adapted wide range applications. ST10F273M lines organized nine groups:
Port time 8-bit port named (low less significant byte) (high most significant byte) Port time 8-bit port named Port 16-bit port Port 15-bit port (P3.14 line implemented) Port 8-bit port Port 16-bit port input only Port Port Port 8-bit ports
These ports used general purpose bidirectional input output, software controlled with dedicated registers. example, output drivers ports configured (bitwise) push-pull open drain operation using ODPx registers. input threshold levels programmable (TTL/CMOS) ports. logic level clocked into input latch once state time, regardless whether port configured input output. threshold selected with PICON XPICON registers control bits. write operation port configured input causes value written into port output latch, while read operation returns latched state itself. readmodify-write operation reads value pin, modifies writes back output latch. Writing configured output (DPx.y `1') causes output latch have written value, since output buffer enabled. Reading this returns value output latch. read-modify-write operation reads value output latch, modifies writes back output latch, thus also modifying level pin. lines support alternate function which detailed following description each port.
13.2
13.2.1
I/O's special features
Open drain mode
Some ports ST10F273M support open drain capability. This programmable feature used with external pull-up resistor, order wired logical function. This feature implemented ports (see respective sections) controlled through respective Open Drain Control Registers ODPx.
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ST10F273M
Parallel ports
13.2.2
Input threshold control
standard inputs ST10F273M determine status input signals according levels. order accept recognize noisy signals, CMOS input thresholds selected instead standard thresholds pins. These CMOS thresholds defined above thresholds feature higher hysteresis prevent inputs from toggling while respective input signal level near thresholds. Port Input Control registers PICON XPICON used select these thresholds each byte indicated ports, this means 8-bit ports P0L, P0H, P1L, P1H, controlled each while ports controlled bits each. options individual direction output mode control available each pin, independent selected input threshold.
13.3
Alternate port functions
Each port line associated programmable alternate input output function.
PORT0 PORT1 used address data lines when accessing external memory. Additionally, PORT1 provides: Input capture lines additional analog input channels converter
Port Port Port associated with capture inputs compare outputs CAPCOM units and/or with outputs PWM0 module, PWM1 module ASC1. Port also used fast external interrupt inputs timer input. Port includes alternate functions timers, serial interfaces, optional control signal system clock output (CLKOUT). Port outputs additional segment address A23.A16 systems where more than Kbytes memory access directly. addition, CAN1, CAN2 lines provided. Port used analog input channels converter timer control signals. Port provides optional arbitration signals (BREQ, HLDA, HOLD) chip select signals SSC1 lines.
alternate output function used, direction this must programmed output (DPx.y `1'), except some signals that used directly after reset configured automatically. Otherwise remains high-impedance state effected alternate output function. respective port latch should hold `1', because output ANDed with alternate output data (except output signals). alternate input function used, direction must programmed input (DPx.y `0') external device driving pin. input direction default after reset. external device connected pin, however, direction this also output. this case, reflects state port output latch. Thus, alternate input function reads value stored port output latch. This used testing purposes allow software trigger alternate input function writing port output latch. most port lines, user software responsible setting proper direction when using alternate input output function pin.
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Parallel ports
ST10F273M
This done setting clearing direction control DPx.y before enabling alternate function. There port lines, however, where direction port line switched automatically. instance, multiplexed external modes PORT0, direction must switched several times instruction fetch order output addresses input data. Obviously, this cannot done through instructions. these cases, direction port line switched automatically hardware alternate function such enabled. determine appropriate level port output latches, check alternate data output combined with respective port latch output. There basic structure port lines with only alternate input function. Port lines with only alternate output function, however, have different structures direction switched depending whether accessible user software alternate function mode. port lines that used these alternate functions used general purpose lines.
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ST10F273M
converter
converter
10-bit converter with multiplexed input channels sample hold circuit integrated on-chip. automatic self-calibration adjusts converter module process parameter variations each reset event. sample time (for loading capacitors) conversion time programmable adjusted external circuitry. ST10F273M multiplexed input channels Port Port respectively. selection between Port Port made XBus register. Refer User Manual detailed description. different accuracy guaranteed (Total Unadjusted Error) Port Port analog channels (with higher restrictions when overload conditions occur); particular, Port channels more accurate than Port channels. Refer Section Electrical characteristics details. converter input bandwidth limited achievable accuracy: Supposing maximum error 0.5LSB (2mV) impacting global (TUE depends also other causes), worst case temperature process, maximum frequency sine wave analog signal around kHz. course, reduce effect input signal variation accuracy down 0.05LSB, maximum input frequency sine wave must reduced static signal applied during sampling phase, series resistance shall greater than (this taking into account eventual input leakage). suggested connect capacitance analog input pins, order reduce effect charge partitioning (and consequent voltage drop error) between external internal capacitance: case filter necessary, external capacitance must greater than 10nF minimize accuracy impact. Overrun error detection protection controlled ADDAT register. Either interrupt request generated when result previous conversion been read from result register time next conversion complete, next conversion suspended until previous result been read. applications which require less than 16+8 analog input channels, rning channel inputs used digital input port pins. converter ST10F273M supports different conversion modes:
Single channel single conversion: analog level selected channel sampled once converted. result conversion stored ADDAT register. Single channel continuous conversion: analog level selected channel repeatedly sampled converted. result conversion stored ADDAT register. Auto scan single conversion: analog level selected channels sampled once converted. After each conversion result stored ADDAT register. data transferred interrupt software management using powerful Peripheral Event Controller (PEC) data transfer. Auto scan continuous conversion: analog level selected channels repeatedly sampled converted. result conversion stored ADDAT
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converter
ST10F273M register. data transferred interrupt software management using data transfer.
Wait ADDAT read mode: When using continuous modes, order avoid overwrite result current conversion next one, ADWR ADCON control register must activated. Then, until ADDAT register read, result stored temporary buffer conversion hold. Channel injection mode: When using continuous modes, selected channel converted between without changing current operating mode. 10-bit data conversion stored ADRES field ADDAT2. current continuous mode remains active after single conversion completed.
full calibration sequence performed after reset. This full calibration lasts 40630 clock cycles. During this time, busy flag ADBSY indicate operation. compensates capacitance mismatch, calibration procedure does need update during normal operation. conversion performed during this time: ADBSY shall polled verify when calibration over, module able start conversion.
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ST10F273M
Serial channels
Serial channels
Serial communication with other microcontrollers, microprocessors, terminals external peripheral components provided four serial interfaces: asynchronous synchronous serial channels (ASC0 ASC1) high-speed synchronous serial channel (SSC0 SSC1). Dedicated baudrate generators standard baudrates without requirement oscillator tuning. transmission, reception erroneous reception, separate interrupt vectors provided ASC0 SSC0 serial channel. more complex mechanism interrupt sources multiplexing implemented ASC1 SSC1 (XBUS mapped).
15.1
Asynchronous synchronous serial interfaces
asynchronous synchronous serial interfaces (ASC0 ASC1) provides serial communication between ST10F273M other microcontrollers, microprocessors external peripherals.
15.2
ASCx asynchronous mode
asynchronous mode, 9-bit data transfer, parity generation number stop bits selected. Parity framing overrun error detection provided increase reliability data transfers. Transmission reception data double-buffered. Fullduplex communication 1.25 Mbaud fCPU) supported this mode.
Table
asynchronous baudrates reload value deviation errors
S0BRS `0', fCPU S0BRS `1', fCPU Baudrate (baud) Deviation error 0.0% 0.0% +6.3% -7.0% +6.3% -0.8% +3.3% -1.4% +0.9% -1.4% +0.9% -0.2% +0.4% -0.2% +0.1% -0.2% +0.1% -0.1% +0.1% 0.0% 0.0% 0.0% 0.0% 0.0% Reload value (hex) 0000 0000 0006 0007 000D 000E 0014 0015 002A 002B 0055 0056 00AC 00AD 015A 015B 02B5 02B6 056B 056C 0AD8 0AD9 1FE8 1FE9
Baudrate (baud)
Deviation error 0.0% 0.0% +1.5% -7.0% +1.5% -3.0% +1.7% -1.4% +0.2% -1.4% +0.2% -0.6% +0.2% -0.2% +0.2% 0.0% 0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0%
Reload value (hex) 0000 0000 000A 000B 0015 0016 001F 0020 0040 0041 0081 0082 0103 0104 0207 0208 0410 0411 0822 0823 1045 1046 1FE8 1FE9
Note:
deviation errors given Table rounded off. avoid deviation errors baudrate crystal (providing multiple ASC0 sampling frequency).
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Serial channels
ST10F273M
15.3
ASCx synchronous mode
synchronous mode, data transmitted received synchronously shift clock which generated ST10F273M. Half-duplex communication Mbaud fCPU) possible this mode.
Table
synchronous baudrates reload value deviation errors
S0BRS `0', fCPU S0BRS `1', fCPU Baudrate (baud) Deviation error 0.0% 0.0% +2.6% -0.8% +0.9% -0.8% +0.9% -0.2% +0.4% -0.2% +0.1% -0.2% +0.1% -0.1% +0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% Reload value (hex) 0000 0000 001C 001D 003A 003B 0055 0056 00AC 00AD 015A 015B 02B5 02B6 056B 056C 0AD8 0AD9 15B2 15B3 1FFD 1FFE
Baudrate (baud)
Deviation error 0.0% 0.0% +1.5% -0.8% +0.3% -0.8% +0.2% -0.6% +0.2% -0.2% +0.2% 0.0% +0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0%
Reload value (hex) 0000 0000 002B 002C 0058 0059 0081 0082 0103 0104 0207 0208 0410 0411 0822 0823 1045 1046 15B2 15B3 1FE8 1FE9
Note:
deviation errors given rounded off. avoid deviation errors baudrate crystal (providing multiple ASC0 sampling frequency).
15.4
High speed synchronous serial interfaces
High-Speed Synchronous Serial Interfaces (SSC0 SSC1) provides flexible highspeed serial communication between ST10F273M other microcontrol
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