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Frequency Synthesizer ADF4108
bandwidth power supply Separate charge pump supply (VP) allows extended tuning voltage systems Programmable, dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog digital lock detect Hardware software power-down mode Loop filter design possible with ADIsimPLL 20-lead chip scale package
ADF4108 frequency synthesizer used implement local oscillators upconversion downconversion sections wireless receivers transmitters. consists noise digital (phase frequency detector), precision charge pump, programmable reference divider, programmable counters, dual-modulus prescaler (P/P (6-bit) (13-bit) counters, conjunction with dual-modulus prescaler (P/P implement divider addition, 14-bit reference counter counter), allows selectable REFIN frequencies input. complete phase-locked loop (PLL) implemented synthesizer used with external loop filter voltage controlled oscillator (VCO). very high bandwidth means that frequency doublers eliminated many high frequency systems, simplifying system architecture reducing cost.
APPLICATIONS
Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations wireless radio
AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
CPGND REFERENCE REFIN 14-BIT COUNTER COUNTER LATCH DATA 24-BIT INPUT REGISTER FUNCTION LATCH COUNTER LATCH 13-BIT COUNTER LOAD LOAD 6-BIT COUNTER SDOUT LOCK DETECT CURRENT SETTING CPI3 CPI2 CPI1 CURRENT SETTING CPI6 CPI5 CPI4 HIGH-Z AVDD MUXOUT PHASE FREQUENCY DETECTOR RSET
CHARGE PUMP
FROM SDOUT FUNCTION LATCH
RFINA RFINB
PRESCALER
ADF4108
06015-001
AGND DGND
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006-2007 Analog Devices, Inc. rights reserved.
ADF4108 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Revision History Specifications. Timing Characteristics Absolute Maximum Ratings. Caution. Configuration Function Descriptions. Typical Performance Characteristics Theory Operation Reference Input Stage. Input Stage. Prescaler (P/P Counters Counter Phase Frequency Detector Charge Pump. MUXOUT Lock Detect. Input Shift Register Latch Summary. Reference Counter Latch Map. Counter Latch Function Latch Map. Initialization Latch Function Latch. Initialization Latch Power Supply Considerations. Interfacing ADuC812 Interface ADSP-21xx Interface Design Guidelines Chip Scale Package. Outline Dimensions Ordering Guide
REVISION HISTORY
12/07-Rev. Rev. Removed TSSOP Package.Universal Changes Features. Changes Table Endnote Endnote Changes Table Deleted Figure Changes Table Changes Figure Figure Updated Outline Dimensions Deleted Figure Changes Ordering Guide 4/06-Revision Initial Version
Rev. Page
ADF4108 SPECIFICATIONS
AVDD DVDD AVDD AGND DGND CPGND RSET referred TMIN TMAX, unless otherwise noted. Table
Parameter CHARACTERISTICS Input Frequency (RFIN) Input Sensitivity Maximum Allowable Prescaler Output Frequency REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency CHARGE PUMP Sink/Source High Value Value Absolute Accuracy RSET Range Three-State Leakage Sink Source Current Matching Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH, Output High Current VOL, Output Voltage POWER SUPPLIES AVDD DVDD (AIDD DIDD) Power-Down Mode (AIDD DIDD) Version 1.0/8.0 -5/+5 20/250 0.8/VDD ±100 Chips (Typ) 1.0/8.0 -5/+5 20/250 0.8/VDD ±100 Unit min/max min/max min/max min/max Programmable; Figure 3.0/11 3.2/3.6 AVDD AVDD/5.5 3.0/11 3.2/3.6 AVDD AVDD/5.5 min/max min/max AVDD 25°C Open-drain output chosen; pull-up resistor CMOS output chosen With RSET With RSET Figure typical; 25°C VP/2 Test Conditions/Comments Figure input circuit lower frequencies, ensure slew rate (SR) MHz, ensure Biased AVDD/2
Rev. Page
ADF4108
Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor Phase Noise Performance 7900 Output Spurious Signals 7900 Output11
Version -219
Chips (Typ) -219
Unit dBc/Hz dBc/Hz
Test Conditions/Comments
output offset frequency offset frequency
Operating temperature range version) -40°C +85°C. chip specifications given typical values. This maximum operating frequency CMOS counters. prescaler value should chosen ensure that input divided down frequency that less than this value. AVDD DVDD coupling ensures AVDD/2 bias. Guaranteed design. Sample tested ensure compliance. 25°C; AVDD DVDD RFIN GHz, fPFD kHz, REFIN MHz. 25°C; AVDD DVDD 16,383; 891; RFIN GHz. This value used calculate phase noise application. formula -219 log(fPFD) logN calculate in-band phase noise performance seen output. value given lowest noise mode. phase noise measured with EVAL-ADF4108EB1Z evaluation board, with ZComm CRO8000Z VCO. spectrum analyzer provides REFIN synthesizer (fREFOUT dBm). fREFIN MHz; fPFD MHz; 7900 MHz; 7900; loop kHz, ZComm CRO8000Z.
Rev. Page
ADF4108
TIMING CHARACTERISTICS
AVDD DVDD AVDD AGND DGND CPGND RSET referred TMIN TMAX, unless otherwise noted. Table
Parameter
Limit Version)
Unit
Test Conditions/Comments DATA CLOCK setup time DATA CLOCK hold time CLOCK high duration CLOCK duration CLOCK setup time pulse width
Guaranteed design production tested. Operating temperature range Version) -40°C +85°C.
CLOCK
DATA DB23 (MSB) DB22
(CONTROL (LSB) (CONTROL
06015-002
Figure Timing Diagram
Rev. Page
ADF4108 ABSOLUTE MAXIMUM RATINGS
25°C, unless otherwise noted. Table
Parameter AVDD AVDD DVDD AVDD Digital Voltage Analog Voltage REFIN, RFINA, RFINB Operating Temperature Range Industrial Version) Storage Temperature Range Maximum Junction Temperature Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature sec) Time Peak Temperature Transistor Count CMOS Bipolar
Rating -0.3 +3.9 -0.3 +0.3 -0.3 +5.8 -0.3 +5.8 -0.3 -0.3 -0.3 -40°C +85°C -65°C +125°C 150°C 30.4°C/W
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. This device high performance integrated circuit with rating sensitive. Proper precautions should taken handling assembly.
CAUTION
260°C 6425
AGND DGND
Rev. Page
ADF4108 CONFIGURATION FUNCTION DESCRIPTIONS
RSET DVDD DVDD
CPGND AGND AGND RFINB RFINA
INDICATOR
ADF4108
VIEW (Not Scale)
AVDD AVDD REFIN DGND DGND
MUXOUT DATA
Figure Configuration
Table Function Descriptions
Mnemonic CPGND AGND RFINB RFINA AVDD REFIN DGND DATA MUXOUT DVDD RSET Description Charge Pump Ground. This ground return path charge pump. Analog Ground. This ground return path prescaler. Complementary Input Prescaler. This point must decoupled ground plane with small bypass capacitor, typically Figure Input Prescaler. This small signal input ac-coupled external VCO. Analog Power Supply. This voltage range from Decoupling capacitors analog ground plane should placed close possible this pin. AVDD must same value DVDD. Reference Input. This CMOS input with nominal threshold VDD/2 equivalent input resistance Figure This input driven from CMOS crystal oscillator ac-coupled. Digital Ground. Chip Enable. logic this powers down device puts charge pump output into three-state mode. Taking high powers device, depending status power-down bit, Serial Clock Input. This serial clock used clock serial data registers. data latched into 24-bit shift register rising edge. This input high impedance CMOS input. Serial Data Input. serial data loaded first with LSBs being control bits. This input high impedance CMOS input. Load Enable, CMOS Input. When goes high, data stored shift registers loaded into four latches, latch being selected using control bits. This multiplexer output allows either lock detect, scaled scaled reference frequency accessed externally. Digital Power Supply. This range from Decoupling capacitors digital ground plane should placed close possible this pin. DVDD must same value AVDD. Charge Pump Power Supply. This voltage should greater than equal VDD. systems where used drive with tuning range Connecting resistor between this CPGND sets maximum charge pump output current. nominal voltage potential RSET 0.66 relationship between RSET 25.5
with RSET Charge Pump Output. When enabled, this provides ±ICP external loop filter, which turn drives external VCO.
Rev. Page
06015-003
ADF4108 TYPICAL PERFORMANCE CHARACTERISTICS
FREQ UNIT: PARAM TYPE: DATA FORMAT: Freq 0.50000 0.60000 0.70000 0.80000 0.90000 1.00000 1.10000 1.20000 1.30000 1.40000 1.50000 1.60000 1.70000 1.80000 1.90000 2.00000 2.10000 2.20000 2.30000 2.40000 2.50000 2.60000 2.70000 2.80000 2.90000 3.00000 3.10000 3.20000 3.30000 3.40000 3.50000 3.60000 3.70000 3.80000 3.90000 4.00000 4.10000 4.20000 MAGS11 0.89148 0.88133 0.87152 0.85855 0.84911 0.83512 0.82374 0.80871 0.79176 0.77205 0.75696 0.74234 0.72239 0.69419 0.67288 0.66227 0.64758 0.62454 0.59466 0.55932 0.52256 0.48754 0.46411 0.45776 0.44859 0.44588 0.43810 0.43269 0.42777 0.42859 0.43365 0.43849 0.44475 0.44800 0.45223 0.45555 0.45313 0.45622 KEYWORD:
Freq 4.30000 4.40000 4.50000 4.60000 4.70000 4.80000 4.90000 5.00000 5.10000 5.20000 5.30000 5.40000 5.50000 5.60000 5.70000 5.80000 5.90000 6.00000 6.10000 6.20000 6.30000 6.40000 6.50000 6.60000 6.70000 6.80000 6.90000 7.00000 7.10000 7.20000 7.30000 7.40000 7.50000 7.60000 7.70000 7.80000 7.90000 8.00000 MAGS11 0.45555 0.46108 0.45325 0.45054 0.45200 0.45043 0.45282 0.44287 0.44909 0.44294 0.44558 0.45417 0.46038 0.47128 0.47439 0.48604 0.50637 0.52172 0.53342 0.53716 0.55804 0.56362 0.58268 0.59248 0.61066 0.61830 0.61633 0.61673 0.60597 0.58376 0.57673 0.58157 0.60040 0.61332 0.62927 0.63938 0.65320 0.65804 ANGS11 -159.680 -164.916 -168.452 -173.462 -176.697 178.824 174.947 170.237 166.617 162.786 158.766 153.195 147.721 139.760 132.657 125.782 121.110 115.400 107.705 101.572 97.5379 93.0936 89.2227 86.3300 83.0956 80.8843 78.0872 75.3727 73.9456 73.5883 74.1975 76.2136 77.1545 76.1122 74.8359 74.0546 72.0061 69.9926
06015-004
ANGS11 -17.2820 -20.6919 -24.5386 -27.3228 -31.0698 -34.8623 -38.5574 -41.9093 -45.6990 -49.4185 -52.8898 -56.2923 -60.2584 -63.1446 -65.6464 -68.0742 -71.3530 -75.5658 -79.6404 -82.8246 -85.2795 -85.6298 -86.1854 -86.4997 -88.8080 -91.9737 -95.4087 -99.1282 -102.748 -107.167 -111.883 -117.548 -123.856 -130.399 -136.744 -142.766 -149.269 -154.884
OUTPUT POWER (dBm)
3.3V, FREQUENCY 1MHz LOOP BANDWIDTH 30kHz BANDWIDTH 3kHz VIDEO BANDWIDTH 3kHz AVERAGES OUTPUT POWER -0.3dBm ZCOMM CRO8000Z
MARKER 1MHz -82.091dBc
CENTER 7.9GHz 24kHz
SPAN 2.5MHz 24kHz
Figure Parameter Data Input
Figure Reference Spurs
3.3V +85°C
(mA)
INPUT POWER (dBm)
SETTLING
+25°C -40°C
06015-005
INPUT FREQUENCY (GHz)
Figure Input Sensitivity
Figure Charge Pump Output Characteristics
PHASE NOISE (dBc/Hz)
MARKER 1kHz -82.51dBc/Hz
-120 -130
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130 -140
-140
-150
06015-010
10MHz FREQUENCY OFFSET
100k
100M
PHASE FREQUENCY DETECTOR (Hz)
Figure Phase Noise
Figure Phase Noise (Referred Output) Frequency
Rev. Page
06015-014
-150 100Hz
CARRIER POWER -5.23dBm 3.3V, FREQUENCY 1MHz LOOP BANDWIDTH 50kHz PHASE NOISE -82dBc/Hz 1kHz ZCOMM CRO8000Z
-160
-170
-180
06015-015
06015-011
-100
ADF4108 THEORY OPERATION
REFERENCE INPUT STAGE
reference input stage shown Figure normally closed switches. normally open. When power-down initiated, closed opened. This ensures that there loading REFIN power-down.
POWER-DOWN CONTROL
COUNTERS
CMOS counters combine with dual-modulus prescaler allow wide ranging division ratio feedback counter. counters specified work when prescaler output less. Thus, with input frequency GHz, prescaler value 16/17 valid value valid.
Pulse Swallow Function
REFIN COUNTER BUFFER 100k
counters, conjunction with dual-modulus prescaler, make possible generate output frequencies that spaced only reference frequency divided equation frequency follows:
REFIN
06015-016
Figure Reference Input Stage
INPUT STAGE
input stage shown Figure followed two-stage limiting amplifier generate clock levels needed prescaler.
BIAS GENERATOR 1.6V AVDD
where: fVCO output frequency external voltage controlled oscillator (VCO). preset modulus dual-modulus prescaler (8/9, 16/17, on.). preset divide ratio binary 13-bit counter 8191). preset divide ratio binary 6-bit swallow counter 63). fREFIN external reference frequency oscillator.
RFINA
13-BIT COUNTER FROM INPUT STAGE PRESCALER MODULUS CONTROL DIVIDER LOAD LOAD 6-BIT COUNTER
RFINB
06015-017
AGND
Figure Input Stage
PRESCALER (P/P
dual-modulus prescaler (P/P along with counters, enables large division ratio, realized dual-modulus prescaler, operating levels, takes clock from input stage divides down manageable frequency CMOS counters. prescaler programmable. software 8/9, 16/17, 32/33, 64/65. based synchronous core. minimum divide ratio possible contiguous output frequencies. This minimum determined prescaler value, given
Figure Counters
COUNTER
14-bit counter allows input reference frequency divided down produce reference clock phase frequency detector (PFD). Division ratios from 16,383 allowed.
Rev. Page
06015-018
ADF4108
PHASE FREQUENCY DETECTOR CHARGE PUMP
phase frequency detector (PFD) takes inputs from counter counter produces output proportional phase frequency difference between them. Figure simplified schematic. includes programmable delay element that controls width antibacklash pulse. This pulse ensures that there dead zone transfer function minimizes phase noise reference spurs. bits reference counter latch, ABP2 ABP1, control width pulse (see Figure 16). minimum antibacklash pulse width recommended.
CHARGE PUMP
consecutive cycles less than required lock detect. stays high until phase error greater than detected subsequent cycle. N-channel open-drain analog lock detect should operated with external pull-up resistor nominal. When lock been detected, this output high with narrow, going pulses.
DVDD
ANALOG LOCK DETECT DIGITAL LOCK DETECT COUNTER OUTPUT COUNTER OUTPUT SDOUT CONTROL
MUXOUT
DGND
PROGRAMMABLE DELAY ABP2 ABP1
Figure MUXOUT Circuit
INPUT SHIFT REGISTER
ADF4108 digital section includes 24-bit input shift register, 14-bit counter, 19-bit counter, comprising 6-bit counter 13-bit counter. Data clocked into 24-bit shift register each rising edge CLK. data clocked first. Data transferred from shift register four latches rising edge destination latch determined state control bits (C2, shift register. These LSBs, DB0, shown timing diagram Figure truth table these bits shown Table Figure shows summary latches programmed. Table Truth Table
Control Bits Data Latch counter counter Function latch (including prescaler) Initialization latch
CLR2 DOWN
06015-019
DIVIDER CPGND
Figure Simplified Schematic Timing Lock)
MUXOUT LOCK DETECT
output multiplexer ADF4108 allows user access various internal points chip. state MUXOUT controlled function latch. Figure shows full truth table. Figure shows MUXOUT section block diagram form.
Lock Detect
MUXOUT programmed types lock detect: digital lock detect analog lock detect. Digital lock detect active high. When lock detect precision (LDP) counter latch digital lock detect high when phase error three consecutive phase detector (PD) cycles less than With five
Rev. Page
06015-020
DIVIDER
CLR1
ADF4108
LATCH SUMMARY
REFERENCE COUNTER LATCH
LOCK DETECT PRECISION
RESERVED
TEST MODE BITS
ANTIBACKLASH WIDTH
14-BIT REFERENCE COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 ABP2 ABP1
COUNTER LATCH
GAIN
RESERVED
13-BIT COUNTER
6-BIT COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
FUNCTION LATCH
FASTLOCK MODE
FASTLOCK ENABLE
THREESTATE
POLARITY
PRESCALER VALUE
CURRENT SETTING
COUNTER RESET
POWERDOWN
POWERDOWN
CURRENT SETTING
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1
INITIALIZATION LATCH
FASTLOCK MODE
FASTLOCK ENABLE
THREESTATE
POLARITY
PRESCALER VALUE
CURRENT SETTING
CURRENT SETTING
COUNTER RESET
POWERDOWN
POWERDOWN
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1
06015-021
Figure Latch Summary
Rev. Page
ADF4108
REFERENCE COUNTER LATCH
LOCK DETECT PRECISION
RESERVED
TEST MODE BITS
ANTIBACKLASH WIDTH
14-BIT REFERENCE COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 ABP2 ABP1
DON'T CARE
DIVIDE RATIO 16380 16381 16382 16383
ABP2
ABP1
ANTIBACKLASH PULSE WIDTH 2.9ns 1.3ns TEST MODE ONLY. 6.0ns 2.9ns
TEST MODE BITS SHOULD NORMAL OPERATION.
OPERATION THREE CONSECUTIVE CYCLES PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT SET. FIVE CONSECUTIVE CYCLES PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT SET.
Figure Reference Counter Latch
Rev. Page
06015-022
BOTH THESE BITS MUST NORMAL OPERATION.
ADF4108
COUNTER LATCH
GAIN
RESERVED 13-BIT COUNTER 6-BIT COUNTER CONTROL BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DON'T CARE
COUNTER DIVIDE RATIO
COUNTER DIVIDE RATIO ALLOWED ALLOWED ALLOWED 8188 8189 8190 8191
(FUNCTION LATCH) FASTLOCK ENABLE
GAIN
OPERATION CHARGE PUMP CURRENT SETTING PERMANENTLY USED. CHARGE PUMP CURRENT SETTING PERMANENTLY USED. CHARGE PUMP CURRENT SETTING USED. CHARGE PUMP CURRENT SWITCHED SETTING TIME SPENT SETTING DEPENDENT WHICH FASTLOCK MODE USED. FUNCTION LATCH DESCRIPTION.
PRESCALER VALUE FUNCTION LATCH. MUST GREATER THAN EQUAL CONTINUOUSLY ADJACENT VALUES FREF OUTPUT, NMIN
06015-023
THESE BITS USED DEVICE DON'T CARE BITS.
Figure Counter Latch
Rev. Page
ADF4108
FUNCTION LATCH
FASTLOCK MODE FASTLOCK ENABLE THREESTATE POLARITY
PRESCALER VALUE CURRENT SETTING CURRENT SETTING
COUNTER RESET
POWERDOWN
POWERDOWN
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
COUNTER OPERATION NORMAL COUNTERS HELD RESET
CHARGE PUMP OUTPUT NORMAL THREE-STATE
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE FASTLOCK MODE
TIMEOUT (PFD CYCLES)
OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) DIVIDER OUTPUT DVDD DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND
CPI6 CPI3
CPI5 CPI2
CPI4 CPI1 1.06 2.12 3.18 4.24 5.30 6.36 7.42 8.50
(mA) 5.1k 0.625 1.25 1.875 3.125 3.75 4.375 0.289 0.580 0.870 1.160 1.450 1.730 2.020 2.320
MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN
PRESCALER VALUE
06015-024
16/17 32/33 64/65
Figure Function Latch
Rev. Page
ADF4108
INITIALIZATION LATCH
FASTLOCK MODE FASTLOCK ENABLE THREESTATE POLARITY
PRESCALER VALUE CURRENT SETTING CURRENT SETTING
COUNTER RESET
POWERDOWN
POWERDOWN
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
COUNTER OPERATION NORMAL COUNTERS HELD RESET
CHARGE PUMP OUTPUT NORMAL THREE-STATE
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE FASTLOCK MODE
TIMEOUT (PFD CYCLES)
OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) DIVIDER OUTPUT DVDD DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND
CPI6 CPI3
CPI5 CPI2
CPI4 CPI1 1.06 2.12 3.18 4.24 5.30 6.36 7.42 8.50
(mA) 5.1k 0.625 1.25 1.875 3.125 3.75 4.375 0.289 0.580 0.870 1.160 1.450 1.730 2.020 2.320
MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN
PRESCALER VALUE
06015-025
16/17 32/33 64/65
Figure Initialization Latch
Rev. Page
ADF4108
FUNCTION LATCH
on-chip function latch programmed with respectively. Figure shows input data format programming function latch. used. fastlock mode then Fastlock Mode selected; fastlock mode then Fastlock Mode selected.
Fastlock Mode
charge pump current switched contents Current Setting device enters fastlock having written gain counter latch. device exits fastlock having written gain counter latch.
Counter Reset
(F1) counter reset bit. When this counter counters reset. normal operation, this should Upon powering needs disabled (set Then, counter resumes counting close alignment with counter. (The maximum error prescaler cycle.)
Fastlock Mode
charge pump current switched contents Current Setting device enters fastlock having written gain counter latch. device exits fastlock under control timer counter. After timeout period determined value TC4:TC1, gain counter latch automatically reset device reverts normal mode instead fastlock. Figure timeout periods.
Power-Down
(PD1) DB21 (PD2) provide programmable powerdown modes. They enabled pin. When low, device immediately disabled regardless states PD1. programmed asynchronous power-down, device powers down immediately after latching into bit, with condition that been loaded with programmed synchronous power-down, device power-down gated charge pump prevent unwanted frequency jumps. Once power-down enabled writing into condition that also been loaded PD2), device goes into power-down occurrence next charge pump event. When power-down activated (either synchronous asynchronous mode, including activated power-down), following events occur: active current paths removed. timeout counters forced their load state conditions. charge pump forced into three-state mode. digital lock detect circuitry reset. RFIN input debiased. reference input buffer circuitry disabled. input register remains active capable loading latching data.
Timer Counter Control
user option programming charge pump currents. intent that Current Setting used when output stable system static state. Current Setting meant used when system dynamic state change (that when output frequency programmed). normal sequence events follows: user initially decides what preferred charge pump currents going example, choice Current Setting Current Setting same time, must decided long secondary current stay active before reverting primary current. This controlled timer counter control bits, DB14:DB11 (TC4:TC1) function latch. truth table given Figure Now, program output frequency, user simply programs counter latch with values same time, gain which sets charge pump with value CPI6:CPI4 period time determined TC4:TC1. When this time charge pump current reverts value CPI3:CPI1. same time, gain counter latch reset ready next time user wishes change frequency. Note that there enable feature timer counter. enabled when Fastlock Mode chosen setting fastlock mode (DB10) function latch
MUXOUT Control
on-chip multiplexer controlled ADF4108. Figure shows truth table.
Fastlock Enable
function latch fastlock enable bit. Fastlock enabled only when this
Fastlock Mode
DB10 function latch fastlock mode bit. When fastlock enabled, this determines which fastlock mode
Rev. Page
ADF4108
Charge Pump Currents
CPI3, CPI2, CPI1 program Current Setting charge pump. CPI6, CPI5, CPI4 program Current Setting charge pump. truth table given Figure When initialization latch loaded, following occurs: function latch contents loaded. internal pulse resets timeout counters load state conditions also three-states charge pump. Note that prescaler band reference oscillator input buffer unaffected internal reset pulse, allowing close phase alignment when counting resumes. Latching first counter data after initialization word activates same internal reset pulse. Successive loads trigger internal reset pulse unless there another initialization. Apply VDD. Bring device into power-down. This asynchronous power-down that happens immediately. Program function latch (10). Program counter latch (00). Program counter latch (01). Bring high take device power-down. counters will resume counting close alignment.
Prescaler Value
function latch prescaler values. prescaler value should chosen that prescaler output frequency always less than equal MHz. Thus, with frequency GHz, prescaler value 16/17 valid value valid.
Polarity
This sets phase detector polarity bit. Figure
Method
Three-State
This controls output pin. With high, output into three-state. With low, output enabled.
INITIALIZATION LATCH
initialization latch programmed when This essentially same function latch (programmed when However, when initialization latch programmed, additional internal reset pulse applied counters. This pulse ensures that counter load point when counter data latched device will begin counting close phase alignment. latch programmed synchronous power-down high; high; low), internal pulse also triggers this power-down. prescaler reference oscillator input buffer unaffected internal reset pulse close phase alignment maintained when counting resumes. When first counter data latched after initialization, internal reset pulse again activated. However, successive counter loads after this trigger internal reset pulse.
Note that after goes high, duration required prescaler band voltage oscillator input buffer bias reach steady state. used power device down check channel activity. input register does need reprogrammed each time device disabled enabled long been programmed least once after initially applied.
Counter Reset Method
Apply VDD. function latch load LSBs). part this, load bit. This enables counter reset. counter load LSBs). counter load LSBs). function latch load LSBs). part this, load bit. This disables counter reset.
Device Programming After Initial Power-Up
After initially powering device, there three ways program device.
Initialization Latch Method
Apply VDD. Program initialization latch LSBs input word). Make sure that programmed Next, function latch load LSBs control word), making sure that programmed Then load LSBs). Then load LSBs).
This sequence provides same close alignment initialization method. offers direct control over internal reset. Note that counter reset holds counters load point three-states charge pump, does trigger synchronous power-down.
POWER SUPPLY CONSIDERATIONS
ADF4108 operates over power supply range ADP3300ART-3.3 dropout linear regulator from Analog Devices, Inc. outputs with accuracy 1.4% recommended with ADF4108.
Rev. Page
ADF4108 INTERFACING
ADF4108 simple SPI-compatible serial interface writing device. CLK, DATA, control data transfer. When (latch enable) goes high, bits that have been clocked into input register each rising edge transferred appropriate latch. Figure timing diagram Table latch truth table. maximum allowable serial clock rate MHz. This means that maximum update rate possible device update every This certainly more than adequate systems that have typical lock times hundreds microseconds.
SCLOCK MOSI DATA MUXOUT (LOCK DETECT)
ADuC812
PORTS
ADF4108
Figure ADuC812 ADF4108 Interface
ADSP-21xx INTERFACE
Figure shows interface between ADF4108 ADSP-21xx digital signal processor. ADF4108 needs 24-bit serial word each latch write. easiest accomplish this using ADSP-21xx family autobuffered transmit mode operation with alternate framing. This provides means transmitting entire block serial data before interrupt generated. word length bits three memory locations each 24-bit word. program each 24-bit latch, store three 8-bit bytes, enable autobuffered mode, then write transmit register DSP. This last operation initiates autobuffer transfer.
SCLOCK MOSI DATA FLAGS MUXOUT (LOCK DETECT)
ADuC812 INTERFACE
Figure shows interface between ADF4108 ADuC812 MicroConverter®. Because ADuC812 based 8051 core, this interface used with 8051-based microcontroller. MicroConverter master mode with CPHA initiate operation, port driving brought low. Each latch ADF4108 needs 24-bit word. This accomplished writing three 8-bit bytes from MicroConverter device. When third byte been written, input should brought high complete transfer. first applying power ADF4108, needs four writes (one each initialization latch, function latch, counter latch, counter latch) output become active. port lines ADuC812 also used control powerdown input) detect lock (MUXOUT configured lock detect polled port input). When operating mode described, maximum SCLOCK rate ADuC812 MHz. This means that maximum rate which output frequency changed kHz.
ADSP-21xx
ADF4108
Figure ADSP-21xx ADF4108 Interface
Rev. Page
06015-027
06015-026
ADF4108 DESIGN GUIDELINES CHIP SCALE PACKAGE
lands chip scale package (CP-20-1) rectangular. printed circuit board these should longer than package land length 0.05 wider than package land width. land should centered pad. This ensures that solder joint size maximized. bottom chip scale package central thermal pad. thermal printed circuit board should least large this exposed pad. printed circuit board, there should clearance least 0.25 between thermal inner edges pattern. This ensures that shorting avoided. Thermal vias used printed circuit board thermal improve thermal performance package. vias used, they should incorporated thermal pitch grid. diameter should between 0.33 barrel should plated with copper plug via. user should connect printed circuit board thermal AGND.
Rev. Page
ADF4108 OUTLINE DIMENSIONS
4.00 0.60
0.60
INDICATOR
2.25 2.10 1.95
INDICATOR
3.75
0.50
(BOTTOM VIEW)
EXPOSED
VIEW 0.80 0.65
0.75 0.60 0.50
0.25
1.00 0.85 0.80 SEATING PLANE
COMPLIANT JEDEC STANDARDS MO-220-VGGD-1
Figure 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Body, Very Thin Quad (CP-20-1) Dimensions shown millimeters
ORDERING GUIDE
Model ADF4108BCPZ ADF4108BCPZ-RL1 ADF4108BCPZ-RL71 EVAL-ADF4108EBZ11
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C
Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
082207-B
0.30 0.23 0.18
0.05 0.02 COPLANARITY 0.08 0.20
Package Option CP-20-1 CP-20-1 CP-20-1
RoHS Compliant Part.
©2006-2007 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D06015-0-12/07(A)
Rev. Page

bandwidth power supply Separate charge pump supply (VP) allows extende

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