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EE-305
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Designing Debugging Systems with SHARC® Processors
Contributed Aseem Vasudev Prabhugaonkar Alberto Comaschi November 2006
Introduction
This EE-Note provides vital information related designing systems with SHARC® processors. These guidelines intended assist hardware engineers well firmware software engineers reducing design cycle times. Some recommendations below also described Hardware Reference manuals respective SHARC processors. This EE-Note divided three sections: hardware board design guidelines, software procedures tricks, debugging tips. tips apply SHARC processors unless specified otherwise.
Hardware Board Design Check Points
This section provides tips board designers.
Interface
Boot Interface ADSP-2126x ADSP-21362/3/4/5/6 ADSP-21367/8/9 ADSP-2137x SHARC Processors
SHARC processors listed above support boot-loading from memory device. When configured flash boot, they boot-load application image from on-board memory. Most commonly used flash devices require falling edge chip select (/CS) prior start instruction after power ADSP-2126x ADSP-21362/3/4/5/6 processors, pull flash chip select using 4.7k resistor. These SHARC processors actively provide logic-high logic-low transition absence internal pull-up this signal; therefore, flash select remain logic level undefined) before first instruction driven processor. pull-up resistor required designs with ADSP-21367/8/9 ADSP-2137x processors because they have internal pull-up resistor ensure falling edge requirement during flash boot-loading operation. example flash memory device that this requirement Microelectronics MP25P80 serial flash device.
MOSI MISO
interface requires that MOSI pins tied together MISO pins tied together. prevent contention possible damage pins, double-check that these pins have been interchanged. Connect MISO MISO, connect MOSI MOSI. peripheral names DOUT, connect them according their master slave function. Proper schematic signal names will reduce confusion.
Copyright 2006, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices applications development tools engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy topicality content provided Analog Devices' Engineer-to-Engineer Notes.
JTAG Design Booting Issues
Most systems initially designed JTAG connectivity, that prototypes pre-production units tested debugged with JTAG (in-circuit emulator). this case, JTAG /TRST signal (TAP reset) driven ICE. However, system runs standalone mode booting operation whenever used, connect /TRST signal board ground. Failing ground /TRST signal lead boot failures memory access failures during runtime. Furthermore, pull-down resistors /TRST recommended because SHARC processors already have on-chip pull-up resistor this signal. Refer Analog Devices JTAG Emulation Technical Reference (EE-68)[1] JTAG system design guidelines.
Two-Wire Interface (TWI)
on-chip two-wire interface I2C-compatible peripheral. Because open drain, both signals require pull-up resistors stated standard. (Refer standard I2Ccompatible device data sheets select pull-up resistor's value.)
Driving /RESET Input
Avoid (resistor/capacitor) circuitry drive SHARC processor's /RESET input signal. Analog Devices recommends power monitoring provide power-on manual /RESET processor. network combination with Schmitt trigger level gates also used drive /RESET input.
Bypass Capacitors
Appropriate bypass capacitors internal power supply become critical higher operating speeds. Unwanted parasitic inductance capacitors traces reduces effectiveness high frequency. things needed when processors operate above MHz. First, capacitors should physically small their leads should short reduce inductance. Surface mounted capacitors size 0402 will yield better results than larger sizes. Second, lower values capacitance will raise resonant frequency circuit. Although several capacitors work well below MHz, 0.1, 0.01, 0.001 even preferred 500-MHz range VDD_INT.
Filter Circuitry AVDD Supply
This section applies ADSP-2116x, ADSP-2126x, ADSP-21362/3/4/5/6 SHARC processors. data sheets these devices recommend filter circuitry AVDD supply used on-chip PLL. Older revisions data sheets suggested using series resistor; better noise immunity stability, this rating been updated high-impedance (600- 1000 @100 MHz) ferrite bead instead. These types ferrite beads have resistance less that
Unused Input Signals
Never leave unused processor inputs floating. Based active polarity inputs signal, pullup resistor pull-down resistor. recommended value resistors pull-up resistors pull-down resistors. Only those inputs that have internal pull-up/pull-down resistor left floating. Check device data sheet identify inputs that have internal pull-up/down resistors
Designing Debugging Systems with SHARC® Processors (EE-305)
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default. Leaving signals such un-used requests (/BRx) host bust request (/HBR) floating cause boot failures other issues during application runtime.
EZ-KIT Lite® Schematics
EZ-KIT Lite® evaluation system schematics good starting reference. Because EZ-KIT Lite board evaluation development, extra circuitry provided some cases. Read EZ-KIT Lite board schematic carefully, because sometimes component populated sometimes been added make easier access, etc. design database SHARC processor EZ-KIT Lite boards available online contains electronic information required design, layout, fabrication, assembly:
Test Points Signal Access
debug process aided prototype boards adding test points signals such CLKOUT/RSTOUT, SDRAM clock (SDCLK), /MSx memory bank selects, /BMS, /RESET. selection pins such boot mode (BOOTCFG) core clock rate (CLKCFG) connected directly power ground, they will inaccessible under BGA-package chip. debugging, helpful pull-up pull-down resistors instead tying power ground directly.
Signal Integrity Tips
Rapid signal rise times fall times primary cause signal integrity problems. These edge rates SHARC processors differ from pin. Likewise, some pins have greater sensitivity noise reflections than other pins. simple signal integrity methods prevent transmission-line reflections that cause extraneous clock sync signals. Short trace lengths series termination critical following peripherals signals: SPORT interface signals (TCLK, RCLK, RFS, TFS): Noise glitches these signals cause improper SPORT functionality. Symptoms such SPORT lock-up condition, channel swap, channel shift, data corruption appear glitches these signals. this reason, cases long traces simulation results that indicate reflections, termination resistors these lines.
CLKIN source: When using crystal source CLKIN, capacitors crystal,
recommended crystal manufacturer. fundamental mode crystal often possible. When using oscillator source CLKIN, leave XTAL processor (not connected). Refer data sheet XTAL/CLKIN circuitry design recommended component values. Avoid routing high-speed signals (for example SDRAM clock, external port data bus, address bus) close beneath) XTAL/CLKIN signal circuitry. Crosstalk induce noise, affecting performance. When using external oscillators drive CLKIN, spread spectrum oscillators reduce emissions clock source. low-skew clock buffers/drivers when designing systems with multiple SHARC processors, taking CLKIN from single clock oscillator. SDRAM clocks, control, address, data also benefit from short traces series termination prevent reflections reduce unwanted EMI. often possible, avoid using sockets such memory chips. Sockets degrade signal integrity performance adding unnecessary parasitic. cases where signals have multiple sources,
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difficult keep traces short, simulation appropriate. IBIS models that assist with signal simulation available from Analog Devices site.
General Guidelines Pointers
Powering SHARC processors: Power both power supplies (VDDINT [core power supply] VDDEXT power supply]) simultaneously. they brought simultaneously, time difference between stable power supplies should exceed specification data sheet (tIVDDEVDD [VDDINT before VDDEXT]). Multiplexed signals: Beware signals that multiplexed have functionality. These signals have default functionality after power /RESET; software programming necessary change functionality from default functionality desired functionality. From system design standpoint; this cause contention signals. Some examples described below. ADSP-21367/8/9 SHARC processors, /MS2 /MS3 strobes multiplexed with flag interrupt pins. After power these signals configured inputs. Therefore, pull-up resistor should used these signals these signals used memory select signals avoid external port contention. example, /MS1 (bank used perform boot-load from external flash memory. Memory devices interfaced /MS2 /MS3 misinterpret logic level their chip select start driving bus, causing contention. Another example RSTOUT/CLKOUT signal multiplexed with running reset functionality ADSP2137x SHARC processors (see Figure after power /RESET, this signal behaves RSTOUT signal. Execute software configure this signal input running reset signal. RSTOUT/CLKOUT signal ADSP-2137x processors should driven (open drain) output host when used achieve running reset functionality. During after power this signal configured output until software configures this input running reset signal. Connecting this active drain output host cause contention damage drivers. Boot memory chip select: ADSP-2106x ADSP-2116x SHARC processors have dedicated signal (/BMS [byte memory select]) drive parallel boot memory device. ADSP-2126x ADSP21362/3/4/5/6 processors, there dedicated boot memory select signal; therefore, memory selects must derived from parallel port address driven processor. ADSP-21367/8/9 ADSP-2137x processors, /MS1 (memory bank select) must used boot memory select signal. Booting occurs through bank There dedicated signal like /BMS ADSP-21367/8/9 ADSP-2137x SHARC processors.
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Figure Typical system block diagram showing running reset scheme
SDRAM address mapping signals: ADSP-21367/8/9 ADSP-2137x SHARC processors have different address mappings compared ADSP-21161 processors. When used 32-bit mode, connect ADDR1 ADSP-21367/8/9 ADSP-2137x processors ADDR0 SDRAM. When used 16-bit mode, connect ADDR0 ADDR0 SDRAM. Unlike ADSP-21161 processors, there support ADSP-21367/8/9 ADSP-2137x processors. Certain SDRAM devices have specific requirement during SDRAM power-up sequence. such SDRAM memories, signal must driven using processor's flag during SDRAM power-up sequence. details about SDRAM interface with ADSP-21367/8/9 processors, refer Interfacing SDRAM Memory ADSP-21367 SHARC Processors (EE-286) [2].
Software Procedures Tips
This section highlights recommended procedures certain peripherals units SHARC processors.
(Peripheral Clock Generator) Programming
This section deals with considerations taken account while using PCGs (Precision Clock Generators) generate signals SHARC SPORTs. When using PCGs generate signals such (frame sync LRCLK) SCLK (serial clock) SPORT configured mode, necessary program delay registers ensure that signal timings confirm with protocol timings. LRCLK signal must driven falling edge serial clock. when used generate signals SPORTs configured mode requires that frame sync remains active only serial clock cycle. Note that frame syncs mode level sensitive, edge sensitive. pulse width register (PCG_PW) should loaded with value frame sync active single serial clock cycle. this configuration, does matter when SPORT enabled re-enabled because frame sync active single serial clock
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cycle. SPORT enabled while frame sync inactive, will wait next active frame sync. system where configuration demands duty cycle, internal interrupt enable SPORT. Consider scenario where frame sync clock have started before SPORT enabled reenabled. serial ports enabled point time after frame sync clock have started, there could situations where serial port starts latching data case receiver) starts driving data case transmitter) whenever valid frame sync sampled. Note that frame sync level sensitive edge sensitive mode. This situation will repeat whenever serial port disabled re-enabled, causing loss synchronization. This cause symptoms such channel shift data loss. correct procedure before starting serial port would wait inactive edge frame sync then enable serial ports while frame sync still inactive. This ensures that serial port waits active frame sync level samples data. This procedure should also repeated when serial ports disabled re-enabled ensure that serial port does sample data middle active frame. This implemented using following procedure. frame sync mapped interrupt. inactive edge frame sync asserts interrupt. This indication that frame sync inactive some duration. serial port should enabled within this duration while frame sync inactive. Perform same procedure when serial port disabled re-enabled.
Enabling Using IDPs (Input Data Ports)
When IDPs used receive data from external devices, there sequence followed enable ports when configured receive data mode. Failing follow this sequence give rise channel shift swap. Connect frame sync internally using (Signal Routing Unit) interrupt. Configure interrupt inactive edge frame sync. Wait interrupt, enable port inside interrupt service routine. Clear interrupt reading interrupt latch register. This procedure will ensure that ports enabled correct time, avoiding issues like channel shift swap received data.
Interrupts
Unlike other interrupts, interrupt cleared automatically inside interrupt service routine. Once latched, interrupt remains latched until latch status cleared explicitly reading interrupt latch register. interrupts cleared reading interrupt latch register. this does occur, program will keep sequencing interrupt service routine every time after coming
Disabling Peripheral Inside Interrupt Service Routine
SHARC processor peripherals support mode data transfer. interrupt generated when transfer count expires. When peripheral configured receive data, count
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expires when entire data received moved internal memory. When peripheral configured transmit data out, data remains FIFO peripheral even though count expires generates interrupt. software intends disable peripheral inside ISR, should poll FIFO status first. When FIFO shows empty status, peripheral safely disabled; otherwise, data loss occur.
Double SPORT/SPI Interrupts
This section applies ADSP-21367/8/9 ADSP-2137x SHARC processors only. Consider scenario where used core mode transmit data. When core encounters transmit buffer empty condition, transmit interrupt generated. Inside transmit interrupt service routine, software writes value transmit buffer returns from interrupt. such situation, after returning from ISR, processor again detects transmit buffer empty condition sequences transmit ISR. This happens highly pipelined writes. After writing transmit buffer takes core clock cycles actual value written update transmit buffer status "not empty". Therefore, under such scenarios, delay return from interrupt routine least core clock cycles.
SHARC Programming
ADSP-2116x SHARC processors, external CLKCFG (clock configuration) signal configures (and core clock external port clock frequency). ADSP-2126x, ADSP-2136x, ADSP2137x SHARC processors, addition external CLKCFG signals, configured software. Thus, various programmable ratios possible software using multiplier divisor counts, which programmed power management control register (PMCTL). This also provides flexibility user change core frequency software. proper configuration, follow recommended sequence, described Managing Core ADSP-2136x SHARC Processors (EE-290)[3]. Ensure that DIVEN cleared before switching bypass mode before switching by-pass mode. EE-290 also provides code examples step-by-step procedure integrate configuration "C-callable" function library using elfar utility.
Interfacing SPORTs Gated Clock Devices
Certain system designs require interfacing SHARC SPORTs gated clock devices such data converters host processors. Guidelines ensure proper operation data transfer with gated clock devices with examples discussed Interfacing Gated Clocks ADSP-21065L SHARC Processors (EE-244)[4], Interfacing AD7676 ADCs ADSP-21065L SHARC Processors (EE-247)[5], Interfacing AD7676 ADCs ADSP-21365 SHARC Processors (EE-248)[6].
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Debugging Tips
often said that prevention better than cure! System design engineers software engineers should always consult anomaly documentation SHARC processor they plan use. This ensures awareness known silicon issues proposed workarounds, shortens design cycle time. issues that must dealt with hardware (such board design), helps avoid expensive timeconsuming board re-spins. This section considers commonly encountered issues provides tips debug them. These tips supplement your other debugging efforts. most commonly reported scenarios discussed, follows.
Boot Failure
These usually reported cases where user able load execute application using JTAG ICE, unable execute applications when boot-loaded. Consider following points while debugging: Check BOOTCFG pins processor ensure that they properly connected digital voltage level high level low. When resistors used provide flexibility change boot mode, ensure that right ones populated. best check voltage levels with oscilloscope processor pins. Ensure that /TRST signal JTAG connected board ground. leave this signal floating. Letting this signal float cause boot failures other memory access failures. Ensure that correct boot kernel used before generating loader (.LDR) file. using modified boot kernel, using default boot kernel supplied with VisualDSP++® together with example application (like flag toggle) confirm basic boot-loading. Ensure that have selected correct parameters while generating .LDR file. Selecting inappropriate parameter cause boot fail. Check whether code boot-loaded using (in-circuit emulator). Connect target open simulator session VisualDSP++. Turn target start boot-loading. Change session from "simulator" "emulator" look Disassembly window. This shows whether application boot-loaded from external source. expected code, there boot failure. also this method check whether processor downloaded initial instructions. Ensure correct power reset timings specified data sheet. Check CLKCFG signals ensure that overdriven. Ensure that ratio selected combination with CLKIN frequency does exceed core clock value greater than specified. Probe boot-related signal like /BMS (/MS1 ADSP-21367/8/9 ADSP-2137x processors), /RD, ADDR, DATA bus. Check integrity tracks board there open circuits short circuits board. also monitor RSTOUT confirm lock.
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Check whether there contention external during boot-load operation. example, ADSP-21367/8/9 ADSP-2137x processors, /MS2 /MS3 used) should have external pullup resistors. Otherwise, memory devices interfaced /MS2 /MS3 drive causing contention boot
Application Crash
Most time, this problem reported software crash while running application. There cases where processor simply hangs after sequencing unknown location restarts whole application. Several things cause this happen, including: Processor performing indirect accesses which cause corruption heap stack memory locations defined .LDF file. This cause corruption vital data needed during time therefore cause software crash. Ensure that application does perform such memory accesses, which give rise corruption. runtime, this debugged using hardware breakpoint feature VisualDSP++ using ICE. processor performs illegal access those regions, these accesses detected. Check whether application performs harmful/unintentional accesses system registers registers that cause application hang restart. example, check application setting soft-restart/re-boot mistake anywhere code. Check indirect jumps calls. Board designs with insufficient decoupling/bypass capacitors lead unpredictable behavior, often erroneously correlated with particular code execution. Ensure that board proper decoupling capacitors bulk capacitors (capacitors type/value placement critical) processor other devices provide sufficient switching current/power required during system runtime. Heavy core switching demands excessive switching currents; current provided, possible symptoms include system shutdown, application crash, incorrect execution specific code. good practice have check-sum validation boot-loaded applications ensure that entire data code downloaded correctly without errors. errors occur noisy environment. errors, processor might execute wrong illegal) instructions process data, giving rise unpredicted behavior. Ensure that length registers (Lx) DAGs (data address generators) explicitly initialized zero when used circular buffers. When used download code execute, symptoms related this noticed because would have initialized length registers zero hence symptoms would noticed only when code boot-loaded executed stand-alone system. Check known VisualDSP++ compiler bugs related specific tool version update). compiler generate code, causing unpredicted behavior. recommended that always latest version VisualDSP++. latest VisualDSP++ release notes located Analog Devices site:
Also, release notes older VisualDSP++ versions located
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Data Loss
This reported loss first words data while receiving over SPORTs, SPI, other serial interfaces. such cases, ensure that slave always enabled before enabling master. master generates signals such serial clock frame sync, slave takes these signals from master device.
Data Corruption
This reported corruption data when received over serial links like SPORTs, SPI, link ports, such cases, ensure signal integrity consider issues overshoots/undershoots noise spikes crosstalk other sources that induce noise. performing internal loopback wherever possible rule functional issues with processor. Look issues using oscilloscope infinite persistence mode. Under such cases, using terminations (preferably series termination) with serial clock, frame sync, Sometimes these issues show shift/swap received channels even when other functional recommendations have been implemented design.
VisualDSP++ Portability Issues
These usually reported issues seen when version update) VisualDSP++ changed. such cases, check differences compiler, known tools issues, etc. turning code optimization further pin-point compiler optimization-related issues. latest version/update VisualDSP++ available beginning project often possible.
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Appendix
Board Design Checklist Check size placement decoupling capacitors Check boot mode selection pins (BOOTCFG) Check core clock rate selection pins (CLKCFG) Check JTAG pins configurations. JTAG Emulation Technical Reference (EE-68) Check test points probe point accessibility. Unused pins very useful hardware software debug purposes (for example driving LEDs probe points). possible, signals through vias. Check reset circuitry. Reset should generated reset supervisory circuitry. network possible combination with Schmitt trigger gate drive RESET/ processor. Check power supply ratings thermal requirements. preferable able adjust core voltage simply changing resistor value. Check component placement, avoid long traces Check processor's data sheet errata up-to-date information
References
Analog Devices JTAG Emulation Technical Reference (EE-68), October 2004, Analog Devices, Inc. Interfacing SDRAM Memory ADSP-21367 SHARC Processors (EE-286), March 2006, Analog Devices, Inc. Managing Core ADSP-2136x SHARC Processors (EE-290), June 2006, Analog Devices, Inc. Interfacing Gated Clocks ADSP-21065L SHARC Processors (EE-244), September 2004, Analog Devices, Inc. Interfacing AD7676 ADCs ADSP-21065L SHARC Processors (EE-247), October 2004, Analog Devices, Inc. Interfacing AD7676 ADCs ADSP-21365 SHARC Processors (EE-248), October 2004, Analog Devices, Inc. Hardware Design Checklist Blackfin Processors (EE-281), October 2005, Analog Devices, Inc.
Document History
Revision November 2006 Alberto Comaschi Aseem Vasudev Prabhugaonkar Description Initial Release
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