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EE-179
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ADSP-TS20xS TigerSHARC® System Design Guidelines
Contributed Greg John August 2005 VDD_DRAM Power Supply VDD_DRAM power supply pins provide power internal embedded DRAM logic. Ground (VSS) Supply ADSP-TS20xS processor contains single ground supply VSS. pins ground returns VDD, VDD_A, VDD_DRAM VDD_IO supply pins. Power Supply Current VDD, VDD_A, VDD_DRAM VDD_IO power supply currents calculated with formulas specified application note Estimating Power ADSP-TS201S (EE-170) [5]. Power Supply Sequencing There power sequencing requirements other than VDD_DRAM voltage must occur last. Refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet more information.
Introduction
This EE-Note discusses specific hardware issues when implementing system design, which incorporates ADSP-TS20xS TigerSHARC® processors. This document provided hardware engineers designing systems using processors with silicon revisions higher. guidelines provided this EE-Note apply ADSP-TS201S, ADSP-TS202S, ADSP-TS203S TigerSHARC embedded processors.
Power Supplies
ADSP-TS20xS processor four power supply domains (Internal), VDD_A (Analog PLL), VDD_IO (External I/O) VDD_DRAM (DRAM) domain. VDD_A supply filtered version supply. Refer ADSP-TS20xS TigerSHARC Embedded Processor Data Sheet more specific details. Power Supply power supply pins used power internal logic except internal DRAM, I/O's PLL. VDD_A Power Supply VDD_A power supply pins used directly power PLL. These pins isolated from internal supply pins additional decoupling filtering circuits added reduce noise. multiprocessor designs recommends keeping VDD_A supplies separate each processor. Refer VDD_A supply decoupling section further details. VDD_IO Power Supply VDD_IO power supply pins provide power I/O's including link port LVDS pins.
Supply Bypass Capacitors
ADSP-TS20xS processor requires bypass capacitors each supply. many cases difficult place lots supply bypass capacitors close package pins, especially bottom side PCB. recommends that designers prioritize decoupling capacitor placement following order: VDD_A bypass capacitors bypass capacitors VDD_DRAM bypass capacitors VDD_IO bypass capacitors Low-ESR/low-ESL capacitors recommended proper bypassing. higher-frequency filtering, 0.01 0.001 capacitors also used
Copyright 2005, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy topicality content provided Analog Devices Engineer-to-Engineer Notes.
addition capacitors), provided their inductance small enough. Enough "bulk" capacitors must used prevent power supply ripple that exceeds max/min power supply tolerances (refer data sheet appropriate supply tolerances) caused current transients system. Several parallel electrolytic and/or tantalum capacitors preferred order minimize provide sufficient capacitance. Careful capacitor placement performing supply ripple analysis (SPICE analysis) power supplies (VDD, VDD_A, VDD_DRAM VDD_IO) recommended ensure adequate decoupling. VDD_A Supply Decoupling analog (VDD_A) supply pins power clock generator PLLs. produce good stable clock, systems must provide "clean" power supply VDD_A domain. Therefore, system designer must critical attention bypassing filtering VDD_A supply. decoupling capacitor placement VDD_A should given first priority over other supplies. Figure shows recommended design VDD_A filtering circuit. components used this circuit should placed close possible VDD_A pins minimize inductance stray capacitance.
Place close pins possible Place close pins possible
VDD_A plane exists, should placed directly above below VDD_IO /VDD planes layer stack-up. Supply Decoupling High frequency noise internal supplies adversely affect speed device. always important provide robust supply bypassing internal supplies especially products whose internal voltages less than recommended that many highfrequency capacitors possible connected supplies close package pins possible. minimum "bulk" (less than capacitors each processor connected supply recommended. These capacitors used reduce power supply ripple during high peak transient currents. Minimum high frequency bypass capacitors located close package pins possible. least bypass capacitor located close package pins possible. least four bypass capacitors located close package pins possible. minimum "bulk" (less than capacitors each processor connected supply recommended. These capacitors used reduce power supply ripple during high peak transient currents. Single Electrolytic: Panasonic Series Sanyo OS-CON series Single tantalum: series Multiple ganged capacitors: series Proper supply design critical ensure operation within data sheet specifications under operating conditions. Adhering data sheet specifications will ensure that time system errors will occur specification violations. VDD_DRAM Supply Decoupling Below minimal recommended bypass capacitor requirements single processor's VDD_DRAM supply. capacitors should duplicated each processor system. Minimum high frequency bypass capacitors located close package pins possible. least bypass capacitor located close package pins possible.
10uH
TS20xS VDD_A VDD_A
10uH
TS20xS VDD_A VDD_A
Figure VDD_A Supply Decoupling recommended that VDD_A decoupling circuit duplicated each processor multiprocessor systems. Place inductor capacitor together with good connections VDD, VSS, VDD_A. Place (minimum) capacitors close VDD_A package pins possible. Make sure that VDD_A trace isn't close noise-generating signals. Make sure that VDD_A trace isolated from other supply planes such VDD_IO minimize noise coupling that could affect sensitive analog circuits.
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least four bypass capacitors located close package pins possible. minimum "bulk" (less then capacitors each processor connected VDD_DRAM supply recommended. These capacitors used reduce power supply ripple during high peak transient currents. Single Electrolytic: Panasonic Series Sanyo OS-CON series Single tantalum: series Multiple ganged capacitors: series VDD_IO Supply Decoupling important provide proper decoupling VDD_IO supply. Enough bypass "bulk" capacitors recommended below must used ensure that VDD_IO supply specifications (max min) violated. Minimum high frequency bypass capacitors located close package pins possible. least bypass capacitor located close package pins possible. least four bypass capacitors located close package pins possible. minimum "bulk" (less than capacitors each processor connected VDD_IO supply recommended. These capacitors used reduce power supply ripple during high peak transient currents. Single Electrolytic: Panasonic Series Sanyo OS-CON series Single tantalum: series Multiple capacitors: series Figure Recommended VREF Circuit multiprocessor (cluster bus) designs VREF should shared between DSPs. important make sure that each processor least (preferably more) high speed decoupling capacitor located close VREF pin. also important keep noise sources from coupling into VREF signal.
SCLK_V
ADSP-TS20xS contains single SCLK_VREF voltage reference pin. This sets input reference voltage SCLK input pin. SCLK_VREF voltage should value specified data sheet with recommended circuit Figure resistor tolerances must (For values refer Figure ADSP-TS201S TigerSHARC Embedded Processor Data Sheet [1].)
ADSP-TS20xS contains single VREF voltage reference pin. This sets input reference voltage certain input pins. exact list pins whose threshold VREF refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet [1]. VREF voltage should value specified data sheet with recommended circuit Figure below. resistor tolerances must (For values refer Figure ADSP-TS201S TigerSHARC Embedded Processor Data Sheet [1].) Figure Recommended SCLK_VREF Circuit multiprocessor (cluster bus) designs, SCLK_VREF should shared between DSPs. important make sure that each processor least (preferably more) high frequency decoupling capacitor located close SCLK_VREF pin. also important keep noise source from coupling into SCLK_VREF signal.
No-Connect (NC) Pins
ADSP-TS20xS contains several No-Connect (NC) pins. These pins must connect supply ground (VDD, VDD_IO, VDD_A, VDD_DRAM, VSS) they must connect other pin. pins must left totally unconnected.
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Configuration Pins
ADSP-TS20xS configuration pins SCLKRAT2-0, ID2-0, CONTROLIMP1-0 DS2-0 used select various chip functions such clock ratio, chip-ID output impedance. These pins typically have either internal pull-up pull-down resistor. configuration pins must have constant value while ADSP-TS20xS powered. When using default configuration, external connection needed; should treated Connect). other configurations (non default), must connected VDD_IO directly through sufficiently strong resistor. multi-processor designs where configuration pins likely wired together (SCLKRAT2-0 connected several processor's) make sure that proper value resistor used override default pull-down/up. Note that total resistor value divided number processors. initial prototype designs advantageous have pads populating strap resistors change default setting SCLKRAT2-0, CONTROLIMP1-0 DS2-0 pins. Configuration pins, which have default pull-ups, should have resistor pads between default pull-downs should have resistor pads between VDD_IO. CONTROLIMP1-0 Configuration Pins CONTROLIMP0 internal pull-down resistor CONTROLIMP1 internal pull-up resistor. These pins control output driver impedance. Refer Table ADSP-TS201S TigerSHARC Embedded Processor Data Sheet more information CONTROLIMP1-0 values. designs recommended CONTROLIMP1-0 pins value "00" (Normal), since this only mode supported IBIS model simulation. DS2-0 Configuration Pins pins contain internal pull-up resistor. contains internal pull-down resistor. These pins control drive strength ADSP-TS20xS output drivers. further information refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet application note User Guide ADSP-TS201S TigerSHARC processor IBIS files (EE-198) [7]. ID2-0 (default) Multiprocessor SCLKRAT2-0 Configuration Pins SCLKRAT2-0 pins contain internal pull-down resistor. These pins multiplier, which generates core clock from SCLK input. more information maximum SCLK duty cycle specifications, max/min SCLK frequency specifications, refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet [1]. ID2-0 Configuration Pins ID2-0 pins have internal pull-down resistor. single processor systems multiprocessor designs where cluster connected other ADSPTS20xS device, pins should default value (000). This because internal pull-up/pull-downs certain pins, like memory interface arbitration enabled only when ID2-0 (000). Setting processor ID2-0 pins (000) eliminates need external resistors. Refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet more details. Note that ID2-0=[000] only processor which enable SDRAM start sequence. multiprocessor designs where cluster shared between TS20xS devices, each processor must programmed unique device starting with ID2-0 (000) incrementing upwards. table figures below describe various configurations ID2-0 assignments.
Table ID2-0 Configuration Options
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/BMS Strap (EBOOT) /BMS strap sets EEPROM (default) External boot mode. During reset, /RST_IN (low), pull-down resistor enabled /BMS chip's ID2-0 pins programmed (000). remaining DSPs ID2-0 programmed system, will have pull-downs pull-ups active /BMS. over-ride default setting, place sufficiently strong resistor (typically between /BMS VDD_IO. /BMS (default) Boot Mode EPROM Boot External Link port Boot Table /BMS Strap Options Strap (IRQEN) strap sets Interrupt disable (default) Interrupt enable /IRQ3-0. During reset, /RST_IN (low), internal pull-down resistor enabled. Figure Cluster Connection Between TS20x Processors. (All Processor ID's Must Unique) override default setting, place sufficiently strong resistor (typically between VDD_IO. (default) Interrupt Enable, (IRQ3-0) Type Disable interrupts, level-sensitive Enable interrupts, edge-sensitive Table Strap Options /BMS strap pins high, deassertion /RST_IN, processor starts running from memory address selected /IRQ3-0 signals (one /IRQ signals should asserted). table below shows starting memory address. Interrupt
/IRQ0 /IRQ1 /IRQ2 /IRQ3
Figure Cluster Connection Between TS20x Processors. (All Processor ID's Must
Strap Pins:
ADSP-TS20xS processor contains four dual-purpose strap pins /BMS, /BM, TMR0E /BUSLOCK. These strap pins select boot-mode, SYSCON/SDRCON write enable, link port width interrupt (edge/level). These strap pins also have additional functionality after reset. When default configuration used, external resistor needed. other configurations, sufficiently strong resistor (typically connected VDD_IO required. strap these pins directly supply other pin. designs which driving strap pins directly from FPGA, ASIC other device, refer data sheet timing details when strap pins sampled when FPGA, ASIC device should stop driving strap data value. four strap pins have internal pull-down resistor, pull-up resistor no-resistor (three-state) each pin. resistor type, which connected pad, depends whether /RST_IN active (low) /RST_IN deasserted (high). Refer Table ("Strap Internal Resistors") ADSP-TS201S TigerSHARC Embedded Processor Data Sheet more information.
Address
0x3000 0000 (External Memory, /MS0) 0x3800 0000 (External Memory, /MS1) 0x8000 0000 (External Memory, /MSH) 0x0000 0000 (Internal Memory)
Table Boot, From Memory Address
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TMR0E Strap (LINK_DWIDTH) TMR0E strap sets Link Port Data Width, 1-bit (default) 4-bit, Link Ports. During reset, /RST_IN (low), internal pull-down resistor enabled TMR0E pin. TMR0E (default) Link Port Input Data Width 1-Bit 4-bit Table TMR0E Strap Options override default setting, place sufficiently strong resistor (typically between TMR0E VDD_IO. /BUSLOCK Strap (/SYS_REG_WE) /BUSLOCK strap sets write enable always writable one-time writable (default) SYSCON SDRCON registers. During reset, /RST_IN (low), internal pull-down resistor enabled /BUSLOCK chip's processor programmed "0". remaining processor ID's (1-7), system, will have pulldowns pull-ups active /BUSLOCK. over-ride default, place sufficiently strong resistor (typically between /BUSLOCK VDD_IO. /BUSLOCK (default) SYSCON/SDRCON write enable One-time writable after reset Always writable Table /BUSLOCK Strap Options CCLK/4 /L0BCMPO SOCCLK/2 /L1BCMPO SCLK /L2BCMPO /RST_IN asserted (low). FPGA ASIC pull-up this Note that only link ports have special test mode straps. only link port requires connection FPGA ASIC, link port since this Link Port Block Completion signal doesn't have test mode straps associated with designs which driving Test Mode strap pins directly from FPGA, ASIC other device, refer data sheet timing details when Test Mode strap pins sampled when FPGA, ASIC device should stop driving strap data value. under circumstances, rising edge reset (deassertion edge), test mode Block Completion signals value other than logic-1 processor test mode will enabled. assist debugging recommend that designers include option placing three optional pull-down resistors (typically between Test Mode Strap pins VSS. also recommended that designers include option placing three optional pull-up resistors (typically between Test Mode Strap pins VDD_IO. These resistors added removed enable disable each specific test modes. Test Mode Description Strap /L1BCMPO /L2BCMPO /L3BCMPO
Test Mode Strap Pins (Link Port)
There three special test strap pins /L1BCMPO, /L2BCMPO /L3BCMPO, which enable test mode functions. These pins Link Port Block Completion signals. They normally outputs, however, when /RST_IN active (low) these pins three-stated internal pull-up resistor enabled. FPGAs some ASICs three-state their pins before they programmed. During this time, some FPGAs and/or ASICs typically turn internal pull-up pulldown resistor. These resistors used keep signals from floating mid-scale before programming. important make sure that FPGA ASIC which connects Link Port Block Completion pins don't have internal pull-down resistor active while
Table Link Port Test Mode Strap Options (ADSP-TS201/ADSP-TS202) Test Mode Description CCLK/4 /L0BCMPO SOCCLK/2 /L1BCMPO SCLK Strap /L1BCMPO
Table Link Port Test Mode Strap Options (ADSP-TS203)
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SCLK
After power-up SCLK signal should stop running unless reset signal (/RST_IN) asserted. SCLK needs stop following power-up sequence, /RST_IN must also asserted. When re-starting SCLK from this condition, follow same guidelines power-up sequence.
CLOCK SOURCE
more CLOCK BUFFERS
Matched Length
CLK#0 CLK#5
TigerSHARC ID=0 TigerSHARC ID=5 CLUSTER
CLK#6
TigerSHARC ID=6 Other Devices (Memory, Host)
CLK#8
Figure Recommended Clock Distribution
SCLK Distribution
single multiprocessor designs careful clock design distribution required ensure proper full-speed internal external operation. Listed below some guidelines clock distribution. connections should point-to-point from clock buffer output clock inputs. Trace lengths should matched (+/- mils) minimize skew. Capacitance clock signals should matched within Minimize number vias. Maintain same number vias each clock signal. clock signals close other signals same layer. Keep least minimum spacing other signals. signals directly above below clock signals. high quality low-jitter clock source generating clock reference. low-jitter clock buffer driver. output-to-output skew clock buffer driver. clock signals from clock buffer outputs SCLK inputs should carefully reviewed. single, multiple-output clock buffer should used drive clock signals devices including DSPs, FPGAs, ASICs Memories. Using multiple clock buffer chips increases clock-to-clock skew between clock signals recommended.
Single CLOCK BUFFER
Matched Length
SCLK Design Considerations
Careful analysis required when choosing components generating, buffering distributing SCLK signals PCB. Refer ADSP-TS20xS data sheet specification SCLK input jitter requirements. Single-stage dual-stage clock tree designs typically used create clock distribution network. Figure shows couple examples these types designs.
Dual-Stage Single-Stage
CLK1 CLKn CLKGEN
CLK1 CLKn
Figure Clock Generation Examples most instances single stage clock designs provide lower jitter specifications tighter duty-cycle control than dual multi-stage clock designs. very important simulate designs, however dual multi-stage designs require special attention when analyzing total jitter (OSC jitter jitter) duty cycle impact. some cases jitter additive, therefore jitter jitter could result total peak-to-peak jitter. some products, however, some input jitter filtered resulting only fraction input jitter being added inherent jitter. Designers should review manufacturer data sheets application notes before choosing Oscillators, Crystals clock driver components ensure they meet jitter, rise/fall time, duty cycle requirements SCLK ADSPTS20xS. important ensure that SCLK_VREF reference voltage complies with data sheet specification. important note that duty cycle SCLK dependent upon SCLK_VREF voltage setting. Other factors consider: When selecting components, output-to-output skew between various clock buffer outputs should small possible ensure high speed operation external interface. Make sure output rise fall times clock drivers symmetrical.
CLK#1 CLK#7 CLK#8
TigerSHARC ID=1
TigerSHARC ID=7 Other Devices (Memory, Host)
Figure Recommended Clock Distribution Method
ADSP-TS20xS TigerSHARC® System Design Guidelines (EE-179)
CLUSTER
CLOCK SOURCE
CLK#0
TigerSHARC ID=0
Page
Review power supply grid supply decoupling clock generation components. Signal integrity analysis should clock signals ensure external coupling they meet exceed SCLK specifications. strap test mode pins sampled SCLK cycles after /RST_IN de-asserted. Refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet exact timing when theses pins latched. Normal Reset Normal Reset defined chip reset (assertion /RST_IN) following initial Power-Up Reset. supplies, SCLK other signals must stable. Core Reset When setting SWRST register EMUCTL, processor core reset, external ports I/O. This sometimes referred software reset. /TRST Boundary Scan Emulator Reset /TRST reset only resets IEEE 1149.1 Boundary Scan port also provides reset signal Emulator interface. This signal requires special considerations Emulator Boundary Scan port being used. Refer application note Analog Devices JTAG Emulation Technical Reference (EE-68) more information.
Reset Pins
There four external pins /RST_IN, /RST_OUT, /POR_IN /TRST associated with reset circuitry ADSP-TS20xS. Three pins /RST_IN, /RST_OUT /POR_IN associated with resetting core internal DRAM. These pins must configured shown Figure below. /TRST JTAG Emulator reset pin. recommends designers place resistor between /RST_OUT /POR_IN. This provides useful place connecting trigger logic-analyzer oscilloscope debugging potential system problems.
RESET CIRCUIT
/RST_IN /RST_OUT
/RST_IN /RST_OUT
/POR_IN /POR_IN
Boundary Scan Emulator Pins
Figure Hardware Reset Connections /RST_IN chip hardware reset pin, /RST_OUT delayed synchronized internal version /RST_IN /POR_IN used reset internal DRAM. multiprocessor designs, /RST_IN signal must connected devices provide common reset sequence. Each processor should connect /RST_OUT /POR_IN pin. required that circuit supplying /RST_IN should hold signal asserted (low) when power supply ramping stable value. ADSP-TS20xS four types resets; Power-Up Reset, Normal Reset, Core Reset JTAG/Emulator Reset. Power-Up Reset Refer "Power-Up Reset Timing" "Normal Reset Timing" sections ADSP-TS201S TigerSHARC Embedded Processor Data Sheet specific timing /RST_IN SCLK pins. ADSP-TS20xS pins associated with Boundary Scan Emulator interface. pins, /EMU, TCK, TDI, TDO, /TRST should connected Boundary Scan connector ADSP-TS20xS emulator used. detailed updated information this subject, please refer engineering note Analog Devices JTAG Emulation Technical Reference (EE-68) [4].
Cluster Pins
single processor system, ID2-0 pins single processor must "000". multiprocessor system, processor must uniquely assigned starting from "000" "111"; single TigerSHARC cluster gluelessly support DSPs. both single multiple processor topologies, imperative include processor ID2-0 "000" system, since this processor supports following features upon reset: active internal pull-ups pull-downs certain external signals when ID2-0="000" (processor ADSP-TS201S TigerSHARC Embedded Processor Data Sheet details.
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default master, therefore provide active arbitration signals external host processor. on-chip SDRAM controller, which provides sequence external SDRAM present system. there external host cluster common data shared between host TigerSHARC processor(s), endianess both sides must matched each other. Note, TigerSHARC processor only little endian does support endian. TigerSHARC processor's addressing word-oriented (32-bit). Some host processors' addressing byteoriented. Therefore, connecting these processors least-significant TigerSHARC processor's address should connected third least-significant host processor's address bus, regardless 32-bit 64-bit width specified. address data busses float several cycles during bus-mastership transitions between TigerSHARC processor host. Floating this case means that these inputs driven source. ADSP-TS20xS contains internal pull-up resistors ensure busses don't float under these conditions. either host external memory widths configured 64-bits, then multiprocessing memory space must configured 64-bits well. external wait-state mode used, please ensure that contention signal occurs. transmit signal pair used, remaining transmit pairs should left unconnected. Name LxDATO3-0P/N LxCLKOUTP/N LxACKI /LxBCMPO Connection Link Partner Link Partner Link Partner Link Partner
Table 4-bit Transmit Link Port Name LxDATO3-1P/N LxDATO0P/N LxCLKOUTP/N LxACKI /LxBCMPO Connection Link Partner Link Partner Link Partner Link Partner*
Table 1-bit Transmit Link Port Refer Test Mode strap section information providing pads optional resistor placement system debug. Receive Link Port Connections receive link port connections should follow guidelines provided ADSP-TS20x data sheet. receive link port used, pins must connected with exception three unused data pairs when using 1-bit wide data port. These three unused data pairs should terminated explained data sheet. silicon revisions 1.1, each LVDS receive pair that connected link partner requires external terminating resistor. These resistors must placed close receiving link port pins possible.
1%External LVDSTerminating Resistor
Link Ports Pins
ADSP-TS201S ADSP-TS202S contain four full-duplex Link Ports, whereas ADSP-TS203S contains only full-duplex Link Ports. Each link port's receive transmit sections operate independently used connected other link partners. link ports used then link port pins must connected between link partners. only exception 1-bit data mode operation. Refer following sections connecting terminating transmit receive link port. Transmit Link Port Connections transmit link port connections should follow guidelines provided ADSP-TS20x data sheet. Note that /LxBCMPO pins transmit link ports alternately used test mode straps. Refer "Test Mode Strap Pins (Link Port)" section this document more details. cases where only
LVDS
Routing
LVDS
Link Transmitter
Link Receiver
Figure LVDS Receive Termination (For Silicon Revisions 1.1)
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silicon revisions newer with frequency link port operation below MHz, external terminating resistor required. Using FPGAs with Link Ports Some applications require initialization FPGA before initiating Link Port transmission. FPGA should drive /LxBCMPI input high processor until LxCLKIN stable logic high state. recommended include external pulldown design override pullup resistor internal FPGA that enabled during initialization.
Figure LVDS Receive Termination (For Silicon Revisions Newer with Frequency Link Port Operation Below 400MHz) Link Ports revision silicon incorporate internal terminating resistor across LVDS clock data pairs link port input pins (i.e. receiver pairs). silicon revision newer, system requires link port operating frequency above MHz, recommended include option external terminating resistors. These resistors allow design risk reduction applications with link port operating frequency above MHz, should therefore populated initially.
Link Port LVDS Guidelines
traces should optimized differential impedance. Connections should point-to-point from Link Port source Link Port destinations. Trace lengths should matched minimize skew. trace lengths should mils. This limits trace delays high-speed 4-bit Link Port operation, place Link Port clock signals between four sets LVDS data signals
Plane
Figure 4-Bit Link Port Clock Placement Minimize number vias. Vias reduce signal integrity. Additional stub length cause unwanted reflections. signals vias between LVDS pairs.
Supply/Gnd plane Supply/Gnd plane
Name LxDATI3-0P/N LxCLKINP/N LxACKO /LxBCMPI
Connection Link Partner Link Partner Link Partner Link Partner
Table 4-bit Receive Link Port Name LxDATI3-1P/N LxDATI0P/N LxCLKINP/N LxACKO /LxBCMPI Connection VDD_IO Link Partner Link Partner Link Partner Link Partner
LVDS PAIR SIGNAL Recommended
LVDS PAIR Recommended
Figure Signals Between LVDS Signal place closely spaced signals vias between adjacent LVDS pairs unless careful analysis done.
Table 1-bit Receive Link Port
ADSP-TS20xS TigerSHARC® System Design Guidelines (EE-179)
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Plane
Supply/Gnd Plane
ground Planes
LVDS PAIR
SIGNAL LVDS PAIR
LVDS PAIR
Recommended
"MicroStrip"
Figure Signals Between LVDS Pairs degrees angles LVDS routing. 45degree bends maintain constant width space between LVDS pairs spacing between adjacent LVDS pairs.
LVDS PAIR degrees recommended
Figure MicroStrip Example placement LVDS signals possible bottom layers PCB, acceptable sandwich LVDS layers between supply and/or ground planes. This configuration referred "StripLine".
Plane
"StripLine"
degrees recommended
LVDS PAIR
Figure 90-Deg Angles LVDS signals signals under above LVDS pairs.
Figure StripLine Example Although StripLine topology significantly reduces EMI, does have some drawbacks. Difficulty maintaining constant impedance Higher propagation delay times) require additional vias layers recommended that supply and/or ground plane extend past edges LVDS signals.
Supply/Gnd Plane
LVDS PAIR
SIGNAL
SIGNAL
LVDS PAIR
SIGNAL
Recommended
Recommended
LVDS PAIR
SIGNAL
LVDS PAIR
SIGNAL
Recommended
Recommended
Figure Signals Above/Below LVDS Signals Place LVDS differential signals bottom layer possible. solid supply ground plane directly underneath LVDS signals also required. This configuration typically referred "MicroStrip".
LVDS PAIR
Figure Supply Plane Overlap LVDS Signal Non-LVDS (single ended) signal must same plane LVDS signals, ground supply trace should inserted between LVDS signal Non-LVDS signal.
ADSP-TS20xS TigerSHARC® System Design Guidelines (EE-179)
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Supply/Gnd Plane
Booting
understand booting process each boot modes further detail, please refer TigerSHARC processor engineering note ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Operation (EE-200) [8]. After reset, ADSP-TS20xS four boot options beginning operation: EPROM Boot, Host Boot, Link Port Boot, Boot. EPROM Boot Master Boot Mode, TigerSHARC processor starts actively fetching externally.
LVDS PAIR
Figure LVDS Signal LVDS Distance Below some industry standard guidelines LVDS signal routing.
LVDS Pair LVDS Pair
ADSP-TS20xS processor defaults EPROM booting depending value /BMS strap pin. When processor configured boot from EPROM, /BMS active during boot sequence should connected chip select signal EPROM. additional information refer /BMS strap section. Host Boot Slave Boot Mode: TigerSHARC processor expects code placed internally. ADSP-TS20xS processor supports booting from external master (host another ADSP-TS20xS). master cluster boot ADSP-TS20xS through writes internal memory through auto DMA. host boot, place sufficiently strong resistor (typically between /BMS VDD_IO. Link Port Boot
Microstrip (Supply Ground Plane)
Figure MicroStrip Guidelines
(Supply Ground Plane)
Stripline (Supply Ground Plane)
Figure StripLine Guidelines Width trace Space between LVDS pair. Distance between LVDS pairs Space ground supply plane edge Distance neighboring supply trace Height between signal next layer Note: following Ratios also required. Optimize differential impedance
Slave Boot Mode: TigerSHARC processor expects code placed internally. four receive link port channels initialized after reset transfer 256-word block internal memory addresses through 255, issue interrupt block (similar external port DMA). corresponding interrupts address zero. additional information refer /BMS TMR0E strap sections. Link Port boot place sufficiently strong resistor (typically between /BMS VDD_IO. Boot Master mode: TigerSHARC processor will start from vector (externally internally) fetching data.
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ADSP-TS20xS processor will begin execution from memory address selected with /IRQ3-0 interrupt signals. Using boot' option, ADSPTS20xS will start running from memory when interrupts asserted. additional information refer /BMS strap sections. boot (boot from memory address) place sufficiently strong resistor (typically between VDD_IO place sufficiently strong resistor (typically between /BMS VDD_IO.
Miscellaneous Items
important signal integrity analysis signals single multiprocessor ADSP-TS20xS based systems.
References
ADSP-TS201S TigerSHARC Embedded Processor Data Sheet, Analog Devices, Inc. ADSP-TS202S TigerSHARC Embedded Processor Data Sheet, Analog Devices, Inc. ADSP-TS203S TigerSHARC Embedded Processor Data Sheet, Analog Devices, Inc. ADSP-TS201S TigerSHARC Processor Hardware Reference, Analog Devices, Inc. ADSP-TS201S TigerSHARC Processor Programming Reference, Analog Devices, Inc. Analog Devices JTAG Emulation Technical Reference (EE-68). Analog Devices, Inc. Estimating Power ADSP-TS201S (EE-170), Analog Devices, Inc. Thermal Relief Design ADSP-TS20xS TigerSHARC Processor (EE-182), Analog Devices, Inc. User Guide ADSP-TS201S TigerSHARC processor IBIS files (EE-198) ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Operation (EE-200), Analog Devices, Inc. Considerations Porting Code from ADSP-TS101S TigerSHARC Processor ADSP-TS201S TigerSHARC Processor (EE-205), Analog Devices, Inc.
Document History
Version August 2005 Greg Steve Description Added "Using FPGAs With Link Ports" section Modified "Supply Bypass Capacitors" section Modified "Link Port Pins" Section Modified "Transmit Link Port" section Modified "Receive Link Port" section Modified production silicon. Updated link port section silicon. Updated SCLK_Vref information data sheet spec Discussing Silicon
January 2005 Greg
2004 John Phil October 2003 Phil
Revised title from ADSP-TS201S TigerSHARC System Design Guidelines ADSP-TS20xS TigerSHARC System Design Guidelines First released version
October 2003 Greg John Phil
ADSP-TS20xS TigerSHARC® System Design Guidelines (EE-179)
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