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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Features
Just-in-time customization clock frequencies internal non-volatile 128-bit serial EEPROM I2CTM-bus serial interface Three on-chip PLLs with programmable reference feedback dividers Four independently programmable muxes post dividers Programmable power-down PLLs output clock drivers Tristate outputs board testing mux/post-divider combinations modified SEL_CD input 3.3V operation Accepts 5MHz 27MHz crystal resonators
Description
FS6370 CMOS clock generator designed minimize cost component count variety electronic systems. Three EEPROMprogrammable phase-locked loops (PLLs) driving four programmable muxes post dividers provide high degree flexibility. internal EEPROM permits just-in-time factory programming devices user requirements.
SEL_CD PD/SCL XOUT OE/SDA
CLK_A CLK_B CLK_C CLK_D MODE
FS6370
Figure Configuration
Semiconductor Rev. 2.0, Mar. www.amis.com
FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
XOUT
Reference Oscillator
Post Divider
CLK_A
MODE PD/SCL
Power Down Control I2C-bus Interface
Post Divider
CLK_B
OE/SDA EEPROM Post Divider CLK_C
SEL_CD
Post Divider
CLK_D
FS6370
Figure Block Diagram
Table Descriptions Type DIUO Name SEL_CD PD/SCL XOUT OE/SDA MODE CLK_D CLK_C CLK_B CLK_A Description Ground Selects programmed post divider combinations Power-down input (run mode) serial interface clock input (program mode) Ground Crystal oscillator feedback Crystal oscillator drive Output enable input (run mode) serial interface data input/output (program mode) Power supply 3.3V) Selects either program mode (low) mode (high) clock output Ground clock output clock output Power supply 3.3V) clock output Power supply 3.3V)
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active
Semiconductor Rev. 2.0, Mar. www.amis.com
FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Functional Block Description
Phase Locked Loops (PLLs) Each three on-chip PLLs standard phase- frequency-locked loop architecture that multiplies reference frequency desired frequency ratio integers. This frequency multiplication exact. shown Figure each consists reference divider, phase-frequency detector (PFD), charge pump, internal loop filter, voltage-controlled oscillator (VCO), feedback divider. During operation, reference frequency (fREF), generated on-board crystal oscillator, first reduced reference divider. divider value often referred modulus, denoted reference divider. divided reference into PFD. controls frequency (fVCO) through charge pump loop filter. provides high-speed, noise, continuously variable frequency clock source PLL. output back through feedback divider (the modulus denoted close loop.
LFTC
REFDIV[7:0]
Loop Filter
fREF Reference Divider
(NR)
PhaseFrequency Detector
Charge Pump
DOWN FBKDIV[10:0]
Voltage Controlled Oscillator
fVCO
Feedback Divider (NF)
Figure Block Diagram
will drive down frequency until divided reference frequency divided frequency appearing inputs equal. input/output relationship between reference frequency frequency
fVCO
3.1.1 Reference Divider
reference divider designed phase jitter. divider accepts output reference oscillator provides divided-down frequency PFD. reference divider 8-bit divider, programmed modulus from programming equivalent binary value. divide-by-256 also achieved programming eight bits 00h.
3.1.2 Feedback Divider
feedback divider based dual-modulus pre-scaler technique. technique allows same granularity fully programmable feedback divider, while still allowing programmable portion operate speed. high-speed pre-divider (also called pre-scaler) placed between programmable feedback divider because high speeds which operate. dual-modulus technique insures reliable operation speed that achieve reduces overall power consumption divider.
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
example, fixed divide-by-eight pre-scaler could have been used feedback divider. Unfortunately, divide-by-eight would limit effective modulus entire feedback divider multiples eight. This limitation would restrict ability achieve desired ratio without making both reference feedback divider values comparatively large. Generally, very large values undesirable they degrade bandwidth PLL, increasing phase jitter acquisition time. understand operation feedback divider, refer Figure M-counter (with modulus always equal cascaded with dualmodulus pre-scaler. A-counter controls modulus pres-caler. value programmed into A-counter pre-scaler will divide pre-scaler outputs. Thereafter, prescaler divides until M-counter output resets A-counter, cycle begins again. Note that N=8, binary numbers.
fVCO
Dual Modulus Prescaler
FBKDIV[2:0]
Counter
FBKDIV[10:3]
Counter
Figure Feedback Divider
Suppose that A-counter programmed zero. modulus pre-scaler will always fixed entire modulus feedback divider becomes MxN. Next, suppose that A-counter programmed one. This causes pre-scaler switch divide-by-N+1 first divide cycle then revert divide-by-N. effect, A-counter absorbs "swallows") extra clock during entire cycle feedback divider. overall modulus seen equal MxN+1. This example extended show that feedback divider modulus equal MxN+A, where A<M.
3.1.3 Feedback Divider Programming
proper operation feedback divider, A-counter must programmed only values that less than equal M-counter. Therefore, divider moduli below available use. This shown Table Above modulus feedback divider programmed value 2047.
Table Feedback Divider Modulus Under M-Counter: FBKDIV[10:3] 00000001 00000010 00000011 00000100 00000101 00000110 00000111 A-Counter: FBKDIV[2:0]
Feedback Divider Modulus
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Post Divider Muxes shown Figure front each post divider stage select from three frequencies reference frequency. selection controlled bits EEPROM control registers. input frequency four multiplexers (muxes Figure altered without reprogramming logic-level input SEL_CD pin. Post Dividers post divider performs several useful functions. First, allows operated narrower range speeds compared variety output clock speeds that device required generate. Second, changes basic equation
where post divider modulus. extra integer denominator permits more flexibility programming loop many applications where frequencies must achieved exactly. modulus four post dividers (post dividers Figure altered without reprogramming logic level SEL_CD pin.
Device Operation
FS6370 modes operation: Program mode: during which either EEPROM FS6370 control registers programmed directly with desired settings mode: where settings stored EEPROM transferred FS6370 control registers power-up, device then operates based those settings Note that EEPROM locations physically same registers used control FS6370. Direct access either EEPROM FS6370 control registers achieved program mode. EEPROM register contents automatically transferred FS6370 control registers normal device operation (run mode). MODE MODE controls mode operation. logic-low places FS6370 program mode. logic-high puts device mode. pull-up this defaults device into mode. Reprogramming either control registers EEPROM permitted time MODE logic-low. Note, however, that logic-high state MODE latched that only transfer EEPROM data FS6370 control registers occur. second transfer EEPROM data into FS6370 desired, power (VDD) must removed reapplied device. MODE also controls function PD/SCL OE/SDA pins. mode, these pins function power-down (PD) output enable (OE) controls. program mode, pins function interface clock (SCL) data (SDA). SEL_CD SEL_CD provides alter operation muxes post dividers without having reprogram device. logic-low SEL_CD selects control bits with "C1" "D1" notation, Table logic-high SEL_CD selects control bits with "C2" "D2" notation, Table Note that changing between running frequencies using SEL_CD produce glitches output, especially post-divider(s) is/are altered.
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Oscillator Overdrive applications where external reference clock provided (and crystal oscillator required), reference clock should connected XOUT must left unconnected (float). best results, make sure reference clock signal jitter-free possible, drive 40pF load with fast rise fall times, swing rail-torail. reference clock rail-to-rail signal, reference must coupled XOUT through 0.01µF 0.1µF capacitor. minimum peak-topeak signal required drive internal differential oscillator buffer.
Mode
MODE logic-high, device enters mode. high state latched (see MODE pin). FS6370 then copies stored EEPROM data into control registers begins normal operation based that data when self-load complete. self-load process takes about 89,000 clocks crystal oscillator. During self-load time, clock outputs held low. reference frequency 27MHz, self-load takes about 3.3ms complete. EEPROM empty (all zeros), crystal reference frequency provides clock four outputs. external programming access FS6370 possible mode. dual-function PD/SCL OE/SDA pins become power-down (PD) output enable (OE) control, respectively. Power-Down Output Enable logic-high PD/SCL powers down only those portions FS6370 which have their respective power-down control bits enabled. Note that PD/SCL internal pull-up. When post divider powered down, associated output driver forced low. When PLLs post dividers powered down crystal oscillator also powered down. forced low, XOUT pulled high. logic-low OE/SDA tristates output clocks. Note that this internal pull-up.
Program Mode
MODE logic-low, device enters program mode. internal registers cleared zero, delivering crystal frequency outputs. device allows programming either internal 128-bit EEPROM on-chip control registers control over PD/SCL OE/SDA pins. EEPROM FS6370 separate parallel devices same on-chip I2C-bus. Choosing either EEPROM device control registers done device address. dual-function PD/SCL OE/SDA pins become serial data (SDA) serial clock input (SCL) normal communications. Note that powerdown output enable control PD/SCL OE/SDA pins available.
EEPROM Programming Data must loaded into EEPROM most-significant-bit (MSB) least-significant-bit (LSB) order. register EEPROM noted Table device address EEPROM
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
6.1.1 Write Operation
EEPROM only written with random register write procedure (see Section 8.2.2). procedure consists device address, register address, bit, byte data. Following STOP condition, EEPROM initiates internally timed write cycle, commits data byte memory. acknowledge signals generated during EEPROM internal write cycle. stop transmitted before entire write command sequence complete, then command aborted data written memory. more than eight bits transmitted before stop sent, then EEPROM will clear previously loaded data byte will begin loading data buffer again.
6.1.2 Acknowledge Polling
EEPROM does acknowledge while internally commits data memory. This feature used increase data throughput determining when internal write cycle complete. process initiate random register write procedure with START condition, EEPROM device address, write command (R/W=0). EEPROM completed internal write cycle, EEPROM will acknowledge next clock, write command continue. EEPROM completed internal write cycle, random register write procedure must restarted sending START condition, device address bit. This sequence must repeated until EEPROM acknowledges.
6.1.3 Read Operation
EEPROM supports both random register read procedure sequential register read procedure (both outlined Section sequential read operations, EEPROM internal address pointer that increments each read operation. pointer directs EEPROM transmit next sequentially addressed data byte, allowing entire memory contents read operation. Direct Register Programming FS6370 control registers directly accessed simply using FS6370 device address read write operations. operation device will follow register values. register FS6370 identical that EEPROM shown Table FS6370 supports random read write procedures, well sequential read write procedures described Section device address FS6370
Cost Reduction Migration Path
FS6370 compatible with programmable register-based FS6377 fixed-frequency ROM-based clock generator. Attention should paid board layout migration path either these devices desired. Programming Migration Path design support programming overhead, cost reduction from EEPROM-based FS6370 register-based FS6377 possible. Figure shows five pins that compatible between various devices programming FS6370 FS6377 desired.
Semiconductor Rev. 2.0, Mar. www.amis.com.
FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
(FS6370)
(FS6377)
(FS6370)
(FS6377)
PD/SCL
(FS6370)
SEL_CD
CLK_A CLK_B CLK_C CLK_D MODE
(FS6370)
FS6370 FS6377
(FS6377)
OE/SDA
(FS6370)
XOUT
(FS6377)
ADDR
(FS6377)
Figure FS6370 FS6377
Non-Programming Migration Path design solidified particular EEPROM programming pattern, EEPROM pattern hard-coded into ROM-based device. highvolume requirements, ROM-based device offers significant cost savings over FS6370. Contact AMIS sales representative more detail.
I2C-bus Control Interface
This device read/write slave device meeting Philips I2C-bus specifications except "general call." controlled master device that generates serial clock SCL, controls access generates START STOP conditions while device works slave. Both master slave operate transmitter receiver, master device determines which mode activated. device that sends data onto defined transmitter, device receiving data receiver. I2C-bus logic levels noted herein based percentage power supply (VDD). logic-one corresponds nominal voltage VDD, while logiclow corresponds ground (VSS). Conditions Data transfer only initiated when busy. During data transfer, data line (SDA) must remain stable whenever clock line (SCL) high. Changes data line while clock line high will interpreted device START STOP condition. following conditions defined I2C-bus protocol.
8.1.1 Busy
Both data (SDA) clock (SCL) lines remain high indicate busy.
8.1.2 START Data Transfer
high transition line while input high indicates START condition. commands device must preceded START condition.
8.1.3 STOP Data Transfer
high transition line while held high indicates STOP condition. commands device must followed STOP condition. Semiconductor Rev. 2.0, Mar. www.amis.com.
FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
8.1.4 Data Valid
state line represents valid data line stable duration high period line after START condition occurs. data line must changed only during period signal. There clock pulse data bit. Each data transfer initiated START condition terminated with STOP condition. number data bytes transferred between START STOP conditions determined master device, continue indefinitely. However, data that overwritten device after first bytes will overflow into first register, then second, first-in, first-overwritten fashion.
8.1.5 Acknowledge
When addressed, receiving device required generate acknowledge after each byte received. master device must generate extra clock pulse coincide with acknowledge bit. acknowledging device must pull line during high period master acknowledge clock pulse. Setup hold times must taken into account. master must signal data slave generating acknowledge last byte that been read (clocked) slave. this case, slave must leave line high enable master generate STOP condition. programmable registers accessed randomly sequentially this bi-directional wire digital interface. device accepts following I2C-bus commands.
8.2.1 Device Address
After generating START condition, master broadcasts seven-bit device address followed bit. device address FS6370
eight possible addresses available EEPROM. least significant three bits don't care's.
8.2.2 Random Register Write Procedure
Random write operations allow master directly write register. initiate write procedure, that transmitted after sevenbit device address logic-low. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address written into slave's address pointer. Following acknowledge slave, master allowed write eight bits data into addressed register. final acknowledge returned device, master generates STOP condition. either STOP repeated START condition occurs during register write, data that been transferred ignored.
8.2.3 Random Register Read Procedure
Random read operations allow master directly read from register. perform read procedure, that transmitted after sevenbit address logic-low, register write procedure. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address then written into slave's address pointer. Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then transmits eight-bit word. master does acknowledge transfer does generate STOP condition.
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
8.2.4 Sequential Register Write Procedure
Sequential write operations allow master write each register order. register pointer automatically incremented after each write. This procedure more efficient than random register write several registers must written. initiate write procedure, that transmitted after seven-bit device address logic-low. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address written into slave's address pointer. Following acknowledge slave, master allowed write bytes data into addressed register before register address pointer overflows back beginning address. acknowledge device between each byte data must occur before next data byte sent. Registers updated every time device sends acknowledge host. register update does wait STOP condition occur. Registers therefore updated different times during sequential register write.
8.2.5 Sequential Register Read Procedure
Sequential read operations allow master read from each register order. register pointer automatically incremented after each read. This procedure more efficient than random register read several registers must read. perform read procedure, that transmitted after seven-bit address logic-low, register write procedure. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address then written into slave's address pointer. Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then transmits bytes data starting with initial addressed register. register address pointer will overflow initial register address larger than zero. After last byte data, master does acknowledge transfer does generate STOP condition.
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
DEVICE ADDRESS
REGISTER ADDRESS
DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
Data Acknowledge STOP Condition Acknowledge From device host
Figure Random Register Write Procedure
DEVICE ADDRESS
REGISTER ADDRESS
DEVICE ADDRESS
DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Data Acknowledge READ Command STOP Condition Acknowledge
Figure Random Register Read Procedure
DEVICE ADDRESS
REGISTER ADDRESS
DATA
DATA
DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
Data Acknowledge
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
From device host
Figure Sequential Register Write Procedure
DEVICE ADDRESS
REGISTER ADDRESS
DEVICE ADDRESS
DATA
DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Data Acknowledge READ Command Acknowledge
Data Acknowledge STOP Command
Figure Sequential Register Read Procedure
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Programming Information
Table Register (Note: register bits cleared zero power-up.) Address Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte MUX_A[1:0] PDPLL_A MUX_B[1:0] PDPLL_B MUX_C1[1:0] (selected SEL_CD PDPLL_C PDPOST_D PDPOST_C PDPOST_B PDPOST_A
MUX_D2[1:0] (selected SEL_CD
MUX_C2[1:0] (selected SEL_CD
POST_D2[3:0] (selected SEL_CD POST_D1[3:0] (selected SEL_CD POST_B[3:0] MUX_D1[1:0] (selected SEL_CD Reserved LFTC_C2 (SEL_CD=1) CP_C2 (SEL_CD=1)
POST_C2[3:0] (selected SEL_CD POST_C1[3:0] (selected SEL_CD POST_A[3:0] FBKDIV_C2[10:8] M-Counter (selected SEL_CD FBKDIV_C2[2:0] A-Counter (selected SEL_CD
FBKDIV_C2[7:3] M-Counter (selected SEL_CD REFDIV_C2[7:0] (selected SEL_CD LFTC_C1 (SEL_CD=0) CP_C1 (SEL_CD=0)
FBKDIV_C1[10:8] M-Counter (selected SEL_CD FBKDIV_C1[2:0] A-Counter (selected SEL_CD
FBKDIV_C1[7:3] M-Counter (selected SEL_CD REFDIV_C1[7:0] (selected SEL_CD
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter FBKDIV_B[2:0] A-Counter
FBKDIV_B[7:3] M-Counter REFDIV_B[7:0] LFTC_A CP_A
FBKDIV_A[10:8] M-Counter FBKDIV_A[2:0] A-Counter
FBKDIV_A[7:3] M-Counter REFDIV_A[7:0]
Control Assignments control altered during device operation, including those bits controlling reference feedback dividers, output frequency will slew smoothly glitch-free manner) frequency. slew rate related programmed loop filter time constant. However, programming changes post divider control bits will cause glitch operating clock output.
9.1.1 Power-Down
power-down functions controlled enable bits. That bits select which portions FS6370 power-down when input asserted. power-down contains one, related circuit will shut down high (run mode only). When low, power enabled circuits. power-down contains zero, related circuit will continue function regardless state.
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Table Power-Down Bits Name PDPLL_A (Bit PDPLL_B (Bit PDPLL_C (Bit Reserved (Bit PDPOST_A (Bit 120) Description Power-Down Power-Down Power-Down
Table Divider Control Bits Name Power Power Power Power Power Power FBKDIV_A[10:0] (Bits 18-8) REFDIV_A[7:0] (Bits 7-0) REFDIV_B[7:0] (Bits 31-24) REFDIV_C1[7:0] (Bits 55-48) REFDIV_C2[7:0] (Bits 79-72) Description Reference Divider (NR) Reference Divider (NR) Reference Divider (NR) selected when SEL-CD Reference Divider (NR) selected when SEL-CD Feedback Divider (NF) FBKDIV_A[2:0] FBKDIV_A[10:3] Feedback Divider (NF) FBKDIV_B[10:0] (Bits 42-32) FBKDIV_B[2:0] A-Counter value A-Counter value M-Counter value
these reserved bits zero Power-Down POST divider Power Power Power Power Power Power Power Power
Power-Down POST divider PDPOST_B (Bit 121)
Power-Down POST divider PDPOSTC (Bit 122)
FBKDIV_C1[10:0] (Bits 66-56)
FBKDIV_B[10:3] M-Counter value Feedback Divider (NF) selected when SEL-CD FBKDIV_C1[2:0] A-Counter value FBKDIV_C1[10:3] M-Counter value
Power-Down POST divider PDPOSTD (Bit 123) FBKDIV_C2[10:0] (Bits 90-80)
Feedback Divider (NF) selected when SEL-CD FBKDIV_C2[2:0] FBKDIV_C2[10:3] A-Counter value M-Counter value
Table Post Divider Control Bits Name POST_A[3:0] (Bits 99-96) POST_B[3:0] (Bits 103-100) POST_C1[3:0] (Bits 107-104) POST_C2[3:0] (Bits 115-112) POST_D1[3:0] (Bits 111-108) POST_D2[3:0] (Bits 119-116) Description POST divider (see Table POST divider (see Table POST divider (see Table selected when SEL_CD POST divider (see Table selected when SEL_CD POST divider (see Table selected when SEL_CD POST divider (see Table selected when SEL_CD
Table Post Divider Modulus Divide
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Table Tuning Bits Name Description Loop Filter Time Constant Short time constant: Long time constant: 20ms Loop Filter Time Constant Short time constant: Long time constant: 20ms Loop Filter Time Constant selected when SEL_CD Short time constant: Long time constant: 20ms Loop Filter Time Constant selected when SEL_CD Short time constant: Charge Pump CP_A (Bit Charge Pump CP_B (Bit Current Current 10mA Current Current 10mA Long time constant: 20ms
Table Select Bits Name Description Frequency Select MUX_A[1:0] (Bits 23-22) Reference frequency frequency frequency frequency
LFTC_A (Bit
LFTC_B (Bit
Frequency Select MUX_B[1:0] (Bits 47-46) Reference frequency frequency frequency frequency
LFTC_C1 (Bit
LFTC_C2 (Bit
Frequency Select selected when SEL_CD MUX_C1[1:0] (Bits 71-70) Reference frequency frequency frequency frequency
CP_C1 (Bit
Charge Pump selected when SEL_CD Current Charge Pump selected when SEL_CD Current Current 10mA
Frequency Select selected when SEL_CD MUX_C2[1:0] (Bits 125-124) Reference frequency frequency frequency frequency
CP_C2 (Bit
Current 10mA
Frequency Select selected when SEL_CD MUX_D1[1:0] (Bits 95-94) Reference frequency frequency frequency frequency
Frequency Select selected when SEL_CD MUX_D2[1:0] (Bits 127-126) Reference frequency frequency frequency frequency
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
10.0 Electrical Specifications
Table Absolute Maximum Ratings Parameter Supply Voltage, (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Re-Flow Solder Profile Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) Symbol
Min. VSS-0.5 VSS-0.5 VSS-0.5
Max. VDD+0.5 VDD+0.5
Units IPC/JEDEC J-STD-020B
Stresses above those listed under absolute maximum ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance Serial Data Transfer Rate Output Driver Load Capacitance Symbol 3.3V fXIN Parallel resonant, Standard mode kb/s Conditions/Description Min. Typ. Max. Units
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Table Electrical Specifications Parameter Overall Supply Current, Dynamic Supply Current, Write Supply Current, Read Supply Current, Static Dual Function (PD/SCL, OESDA) Symbol Conditions/Description 5.5V, fCLK 50MHz, 15pF Figure more information Additional operating current demand, EEPROM program mode, 5.5V Additional operating current demand, EEPROM program mode, 5.5V 5.5V, powered down 5.5V 3.6V 5.5V 3.6V 5.5V 3.6V 5.5V 3.6V 5.5V 3.6V 5.5V 3.6V 5.5V 3.6V 5.5V 3.6V 5.5V 3.6V 3.85 2.52 3.85 2.52 3.85 2.52 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 2.20 1.44 2.20 1.44 0.275 0.18 Min. Typ.
Max.
Units
IDD(write) IDD(read) IDDL
VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 1.65 1.08 1.65 1.08 1.65 1.08
mode (PD, High-Level Input Voltage Register program mode (SDA, SCL) EEPROM program mode (SDA, SCL) mode (PD, Low-Level Input Voltage Register program mode (SDA, SCL) EEPROM program mode (SDA, SCL) mode (PD, Hysteresis Voltage Vhys Register program mode (SDA, SCL) EEPROM program mode (SDA, SCL) High-Level Input Current Low-Level Input Current (pull-up) Low-Level Output Sink Current (SDA) Run/register program mode EEPROM program mode Run/register program mode, 0.4V EEPROM program mode, 0.4V 5.5V 3.6V 5.5V 3.6V
Mode Frequency Select Inputs (MODE, SEL_CD) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance* Input Loading Capacitance* Crystal Oscillator Drive (XOUT) High-Level Output Source Current Low-Level Output Sink Current Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current* Short Circuit Sink Current* 5.5V 3.6V 5.5V 5.5V, oscillator powered down VSS-0.3 VSS-0.3 VDD+0.3 VDD+0.3
CL(xtal) CL(XIN) ISCH ISCL
seen external crystal connected XOUT seen external clock driver XOUT; unconnected V(XIN) 5.5V, 5.5V, V(XIN) 5.5V 2.4V 0.4V 0.5VDD; output driving high 0.5VDD; output driving 5.5V, shorted 30s, 5.5V; shorted 30s,
-125 -150
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. Min. Max. characterization data from typical. Negative currents indicate current flows device.
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Voltage
Drive Current (mA) Min. Typ. Max.
Voltage
High Drive Current (mA) Min. Typ. -112 -110 -108 -104 Max. -150 -147 -144 -139
Output Current (mA)
-131 -121 -116 -108 -102
-100
-150
-200
Output Voltage
data this table represents nominal characterization data only.
Figure CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Dynamic Current (mA) Output Frequency (MHz)
outputs except output under test, outputs except output under test outputs 200MHz except output under test outputs 4MHz except output under test outputs same frequency outputs same frequency,
5.0V; Reference Frequency 27.00MHz; Frequency 200MHz, 17pF except where noted
Dynamic Current (mA) Output Frequency (MHz)
outputs except output under test outputs except output under test, outputs 100MHz except output under test outputs 2MHz except output under test outputs same frequency
outputs same frequency,
3.3V; Reference Frequency 27.00MHz; Frequency 100MHz, 17pF except where noted
Figure Dynamic Current Output Frequency
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Table Timing Specifications Parameter Overall EEPROM Write Cycle Time Output Frequency* Frequency* Gain* Loop Filter Time Constant* Rise Time* Fall Time* Tristate Enable Delay* Tristate Disable Delay* Clock Stabilization Time* tPZL, tPZH tPZL, tPZH tSTB Output active from power-up, mode After last register written, register program mode also Table also Table
Ratio pulse width measured from rising edge next falling edge 2.5V) clock period rising edges 500ms apart 2.5V relative ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, other PLLs active
Symbol Conditions/Description fVCO AVCO LFTC LFTC 0.5V 0.3V 4.5V 3.0V 4.5V; 3.0V; 0.5V; 0.3V; 15pF 15pF 15pF 15pF 5.5V 3.6V 5.5V 3.6V
Clock (MHz)
Min.
Typ.
Max.
Units MHz/V
Divider Modulus Feedback Divider Reference Divider Post Divider Clock Outputs (PLL clock CLK_A pin) Duty Cycle* Jitter, Long Term (sy(t))* tj(LT)
2047
rising edges 500ms apart 2.5V relative ideal clock, CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, other PLLs active From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, other PLLs active (B=60MHz, C=40MHz, D=14.318MHz)
Jitter, Period (peak-peak)*
tj(DP)
Clock Outputs (PLL clock CLK_B pin) Duty Cycle* Jitter, Long Term (sy(t))* Tj(LT)
Ratio pulse width measured from rising edge next falling edge 2.5V) clock period rising edges 500ms apart 2.5V relative ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active rising edges 500ms apart 2.5V relative ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active (A=50MHz, C=40MHz, D=14.318MHz)
Jitter, Period (peak-peak)*
TJ(DP)
Clock Outputs (PLL_C clock CLK_C pin) Duty Cycle* Jitter, Long Term (sy(t))* Tj(LT)
Ratio pulse width measured from rising edge next falling edge 2.5V) clock period rising edges 500ms apart 2.5V relative ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active rising edges 500ms apart 2.5V relative ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active (A=50MHz, B=60MHz, D=14.318MHz)
Jitter, Period (peak-peak)*
TJ(DP)
Clock Outputs (Crystal Oscillator CLK_D pin) Duty Cycle* Jitter, Long Term (sy(t))* Tj(LT)
Ratio pulse width measured from rising edge next falling edge 2.5V) clock period rising edges 500ms apart 2.5V relative ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, other PLLs active From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, other PLLs active (A=50MHz, B=60MHz, C=40MHz) From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, other PLLs active
14.318 14.318 14.318 14.318 14.318
Jitter, Period (peak-peak)*
TJ(DP)
From rising edge next rising edge 2.5V, CL=15pF, fXIN=14.318MHz, other PLLs active (A=50MHz, B=60MHz, C=40MHz)
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. Min. Max. characterization data from typical.
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Table Serial Interface Timing Specifications Standard Mode Parameter Clock Frequency Free Time Between STOP START Set-up Time, START (repeated) Hold Time, START Set-up Time, Data Input Hold Time, Data Input Output Data Valid From Clock Rise Time, Data Clock Fall Time, Data Clock High Time, Clock Time, Clock Set-up Time, STOP Symbol fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tsu:STO
Minimum delay bridge undefined region falling edge avoid unintended START STOP
Conditions/Description Min. 1000 Max.
Units
SDA, SDA,
tsu:STA thd:STA tsu:STO
START
ADDRESS DATA VALID
DATA CHANGE
STOP
Figure Timing Data
tsu:STA thd:STA thd:DAT tsu:DAT tsu:STO
tBUF
Figure Data Transfer Sequence
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
11.0 Package Information Both `Green' `Non-Green'
Table 16-pin SOIC (0.150") Package Dimensions Dimensions Inches Min. 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 Millimeters 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 Max. 1.73 0.249 1.55 0.49 0.249 9.98 3.99 1.27 6.20 0.41 0.89
0.050
Table 16-pin SOIC (0.150") Package Characteristics Parameter Thermal Impedance, Junction Free-Air 16-pin 0.150" SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Symbol Conditions/Description flow Corner lead Center lead lead adjacent lead lead Typ. Units °C/W
12.0 Ordering Information
Table Device Ordering Codes Ordering Code 11575-801-XTP -XTD) Device Number FS6370-01 Package Type 16-pin (0.150") SOIC (small outline package) 16-pin (0.150") SOIC (small outline package) 'Green' lead-free packaging Operating Temperature Range 70°C (Commercial) Shipping Configuration -XTP (Tape Reel) -XTD (Tube/Tray) -XTP (Tape Reel) -XTD (Tube/Tray)
11575-819-XTP XTD)
FS6370-01g
70°C (Commercial)
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
13.0 Demonstration Software
Windows 3.1x/95/98-based software available from AMIS that illustrates capabilities FS6370. software operate under Windows Contact your local sales representative more information. 13.1 Software Requirements running Windows 3.1x 95/98. Software also runs Windows calculation mode only. 1.8MB available space hard drive 13.2 Software Installation Instructions appropriate disk drive prompt (A:\) unzip compressed demo files directory your choice. setup.exe install software. 13.3 Demo Program Operation Launch fs6370.exe program. Note that parallel port accessed your machine running Windows warning message will appear stating: "This version demo program cannot communicate with FS6370 hardware when running Windows operating system. want continue anyway, using just calculation features this program?" Clicking starts program calculation only. FS6370 demonstration hardware longer available supported. opening screen shown Figure
Figure Opening Screen
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
13.3.1 Example Programming
Type value crystal resonator frequency reference crystal box. This frequency provides basis calculations that follow. Next, click box. pop-up screen similar Figure should appear. Type desired output clock frequency MHz, operating voltage (3.3V 5V), desired maximum output frequency error. Pressing calculate solutions generates several possible divider VCO-speed combinations.
Figure Screen
100MHz output, should ideally operate higher frequency, reference feedback dividers should small possible. this example, highlight solution Notice operates 200MHz with post divider obtain optimal percent duty cycle. choose which post divider (that choose output 100MHz output). Selecting places PostDiv value solution into post divider switches take output screen should disappear, value frequency chosen solution Note that been switched post divider chosen 100MHz output displayed. Repeat steps supports different output frequencies depending setting SEL_CD pin. Both also affected logic level SEL_CD pin, post dividers (see Section more detail).
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FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator
Figure Post Divider Menu
Click open screen. desired frequency, however, choose post divider output divider. Notice post divider split shown Figure 16). post divider shows that divider dependent setting SEL_CD long output. Clicking post divider reveals pull-down menu provided permit adjustment post divider value independently screen. typical menu shown Figure range possible post divider values also given Table EEPROM settings shown left screen shown Figure Clicking register location displays screen shown Figure Individual bits poked, entire register value changed.
Figure Register Screen
Production Technical Data information contained this document applies product production. Semiconductor subsidiaries ("AMIS") have made every effort ensure that information accurate reliable. However, characteristics specifications product subject change without notice information provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify that data being relied most current complete. AMIS reserves right discontinue production change specifications prices time without notice. Products sold AMIS covered warranty patent indemnification provisions appearing Terms Sale only. AMIS makes other warranty, express implied, disclaims warranties noninfringement, merchantability, fitness particular purpose. Semiconductor's products intended ordinary commercial applications. These products designed, authorized, warranted suitable lifesupport systems other critical applications where malfunction cause personal injury. Inclusion AMIS products such applications understood fully customer's risk. Applications requiring extended temperature range, operation unusual environmental conditions, high reliability, such military medical life-support, specifically recommended without additional processing AMIS such applications. Copyright ©2005 Semiconductor, Inc.
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Features Just-in-time customization clock frequencies internal no

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