SIIGX52001-2.3 Stratix® devices combine highly advanced 6.375-Gig

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SIIGX52001-2.3 Stratix® devices combine highly advanced 6.375-Gig

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Stratix Transceiver Block Overview
SIIGX52001-2.3
Stratix® devices combine highly advanced 6.375-Gigabits second (Gbps) four-channel gigabit transceiver blocks with industry's most advanced FPGA architecture. Stratix transceiver builds success Stratix family offering higher data rate support additional features that enable support wide variety standard custom protocols. Each self-contained Stratix gigabit transceiver block variety embedded functions implement commonly required tasks. Stratix transceivers structured into duplex four-channel groups called transceiver blocks. configure each channel within transceiver block either single-width double-width mode. Single-width mode 8-bit/10-bit SERDES data path through transceiver supports data rates from Mbps 3.125 Gbps. Double-width mode 16-bit/20-bit SERDES data path through transceiver supports data rates from Gbps 6.375 Gbps. blocks transceiver operate double-width mode, except deskew first-in first-out (FIFO), which available only single-width mode. options blocks available transceiver differ depending which mode (single double) use. This documentation uses terminology inter-transceiver block routing instead inter-quad (IQ) routing, seen Quartus software.
Building Blocks
addition custom (BASIC) modes, Stratix transceivers support following protocols:
Physical Interface Express (PIPE) single lane four lane eight lane XAUI Gigabit Attachment Unit Interface) GIGE (Gigabit Ethernet) SONET (Synchronous Optical NETwork) OC-12, OC-48, OC-96 (OIF) (Common Electrical I/O)
Altera Corporation August 2007
Transmitter Channel Overview
Figure shows block diagram gigabit transceiver block single-width mode. enable disable various optional modules based functional mode select. sections that follow Figure give brief description each block.
detailed information about each block, refer Stratix Transceiver Architecture Overview chapter volume Stratix Device Handbook.
Figure 1-1. Stratix Gigabit Transceiver Block Diagram
Transmitter Digital Logic Phase Compensation FIFO Transmitter Analog Circuits
PIPE Interface
Byte Serializer
8B/10B Encoder
Serializer
Logic Array
Reset Logic
State Machines
Reference Clocks
Receiver Digital Logic
Receiver Analog Circuits
PIPE Interface
Phase Compensation FIFO
Byte Ordering
Byte Deserializer
8B/10B Decoder
Rate Match FIFO
Deskew FIFO
Word Aligner
Deserializer
Clock Recovery Unit Refernce Clocks
Receiver
Transmitter Channel Overview
This section provides brief description about various components within transmitter block (Figure 1-2). modules listed order from parallel logic array transmit buffer transmitter. Figure 1-2. Stratix Transmitter Block Diagram
Transmitter Digital Logic Phase Compensation FIFO Transmitter Analog Circuits
Byte Serializer
8B/10B Encoder
Serializer
Reference Clocks
Stratix Device Handbook, Volume
Altera Corporation August 2007
Stratix Transceiver Block Overview
Clock Multiplier Unit
Each gigabit transceiver block clock multiplier unit (CMU) provide clocking flexibility support range incoming data streams. Each contains transmitter phase-locked loops (PLLs) that generate required clock frequencies based upon synthesis input reference clock. Each transmitter supports multiplication factors allow various input clock frequencies. Both transmitter PLLs identical support data ranges from Mbps 6.375 Gbps. However, each configured support different data rates. Each transmitter drives four channels non-PIPE mode. PIPE mode, only transmitter active drives eight channels. This block active both single- double-width modes powered down when use.
Phase Compensation FIFO Buffer
transmitter data path dedicated phase compensation FIFO buffer that decouples phase variations between FPGA transceiver clock domains. This block active both single double-width modes cannot bypassed.
Byte Serializer
byte serializer allows programmable logic device (PLD) half rate transmit data path allow core lower frequency. Without byte serializer, maximum data rate 6.375 Gbps with 20-bit serialization factor, runs 318.75 MHz. With byte serializer, runs 159.375 MHz. This block available both single- double-width modes. single-width mode, interface either bits when byte serializer used. double-width mode, using byte serializer creates interface bits bits, depending serialization factor.
8B/10B Encoder
Many protocols 8B/10B encoding. Stratix devices have dedicated 8B/10B encoders each transmitter channel. This encoding technique ensures sufficient data transitions DC-balanced stream within data signal successful data recovery receiver. This block available single- double-width modes. single-width mode, 8B/10B encoders active. double-width mode, both 8B/10B encoders active operate cascade mode. 8B/10B encoder follows IEEE 802.3 1998 edition standard 8B/10B encoding.
Altera Corporation August 2007
Stratix Device Handbook, Volume
Receiver Channel Overview
Serializer
serializer converts incoming lower speed parallel signal from transceiver's physical coding sublayer (PCS) high-speed serial signal transmit side. serializer supports variety conversion factors, ensuring implementation flexibility. serializer supports 10-bit serialization factor single-width mode 20-bit serialization factor double-width mode. serializer block also performs clock synthesis slow-speed clock parallel transmitter logic transceiver PLD.
Transmitter Differential Output Buffers
gigabit transceiver block differential output buffers support 1.5-V PCML 1.2-V PCML standards have variety features that improve system signal integrity. Programmable pre-emphasis helps compensate high frequency losses. variety programmable settings allow noise margin tuning capabilities. Additionally, on-chip termination provides appropriate transmitter buffer termination 100-, 120-, 150- transmission lines. transmitter buffer circuit also contains receiver-detect circuit with Express protocol detect receiver connected. buffer tri-stated reduce electromagnetic interference (EMI) power consumption when use. PIPE mode, tri-state feature generates Electrical Idle.
Receiver Channel Overview
This section provides brief description about various components within receiver block. modules originate from serial receiver buffer parallel FPGA interface (refer Figure 1-3).
Figure 1-3. Stratix Receiver Block Diagram
Receiver Digital Logic Receiver Analog Circuits
Phase Compensation FIFO
Byte Ordering
Byte Deserializer
8B/10B Decoder
Rate Match FIFO
Deskew FIFO
Word Aligner
Deserializer
Clock Recovery Unit
Receiver Clock
Reference
Stratix Device Handbook, Volume
Altera Corporation August 2007
Stratix Transceiver Block Overview
Receiver Differential Input Buffers
Stratix transceiver block differential input buffers support 1.5-V PCML 1.2-V PCML standards, have variety features that improve system signal integrity. Programmable equalization capabilities compensate signal degradation across transmission mediums. Additionally, on-chip termination provides appropriate receiver termination 100-, 120-, 150- transmission lines. signal detection block indicates there valid signal receiver input.
Receiver
receiver ramps voltage controlled oscillator (VCO) frequency reference clock. Once that occurs, clock recovery unit (CRU) controls VCO. Each receiver channel transceiver dedicated receiver that provide clocking flexibility supports range data rates. These PLLs generate required clock frequencies based upon synthesis input reference clock.
Clock Recovery Unit
Stratix transceiver block performs analog clock data recovery (CDR). recovers embedded clock data stream properly clock incoming data. recovered clock also clocks reset receiver logic clock (rx_digitalreset) available fabric.
Deserializer
deserializer block converts incoming data stream from high-speed serial signal lower-speed parallel signal that processed FPGA logic array receive side. deserializer supports variety conversion factors, ensuring implementation flexibility. deserializer supports 10-bit deserialization factor single-width mode 20-bit deserialization factor double-width mode. deserializer block also performs clock synthesis slow-speed clock from forwards recovered clock parallel receiver logic transceiver PLD.
Word Aligner
word aligner module contains fully programmable pattern detector identify specific patterns within incoming data stream. pattern detector includes recognition support control code groups 8B/10B encoded data A1A2 A1A1A2A2-type frame alignment patterns scrambled data. Custom alignment patterns also available. word aligner bypassed some functional modes.
Altera Corporation August 2007
Stratix Device Handbook, Volume
Receiver Channel Overview
single-width mode, following word-alignment options available:
Manual bit-slip mode Manual alignment 10-, 16-bit patterns Synchronization state machine that offers programmable hysteresis synchronization.
double-width mode, following word-alignment options available:
Manual bit-slip mode Manual alignment 10-, 16-, 20-, 32-bit patterns
Channel Aligner (Deskew)
embedded channel aligner aligns byte boundaries across multiple channels synchronizes data entering logic array from Gigabit transceiver block's four channels. Stratix channel aligner optimized 10-Gigabit Ethernet XAUI four-channel implementation. channel aligner includes control circuitry channel alignment character detection defined 10-Gigbit Attachment Unit Interface (XAUI) protocol. This block only available XAUI protocol disabled other protocols.
Rate Matcher
CDR-based systems, clock frequencies transmitting receiving devices often match. This mismatch cause data transmit rate slightly faster slower than receiving device interpret. Stratix rate matcher resolves frequency differences between recovered clock FPGA logic array clock inserting deleting removable characters from data stream, defined transmission protocol, without compromising transmitted data. rate matcher block available single- double-width Basic modes specific protocols-XAUI, Gigabit Ethernet (GIGE), Physical Interface Express (PIPE).
8B/10B Decoder
Various protocols 8B/10B decoding. Stratix devices have dedicated 8B/10B decoders each channel support high data rates. This decoding technique ensures fast disparity code group error detection. This block available single- double-width modes. single-width mode, only 8B/10B decoders active.
Stratix Device Handbook, Volume
Altera Corporation August 2007
Stratix Transceiver Block Overview
double-width mode, both 8B/10B decoders active operate cascade mode. current running disparity sent each decoded code group. 8B/10B decoder follows IEEE 802.3 1998 edition standard 8B/10B decoding.
Byte Deserializer
byte deserializer widens transceiver data path before interface reduce rate which received data must clocked logic. This byte deserializer block available both single- double-width modes. single-width mode, interface either bits when used. double-width mode, using byte deserializer creates interface bits, depending your serialization factor.
Byte Ordering
Each receiver optional byte ordering block that available some functional modes when byte deserializer used. This block restores expected word ordering byte deserialization data word does match expected word ordering after byte deserializer block. This block available when rate matcher used (single- double-width mode) because rate matcher alter byte order adding deleting bytes. also available when 8B/10B used single-width mode.
Receiver Phase Compensation FIFO Buffer
Each receiver data path dedicated phase compensation FIFO buffer that decouples phase variations between FPGA transceiver clock domains. This block always used cannot bypassed.
PIPE Interface
PIPE interface supports Express protocol. PIPE interface simplifies standardizes back-end interface Express physical layer. This block automatically enabled PIPE mode available other mode.
Loopback
There four available loopback modes diagnostic purposes. following loopback modes available:
Serial loopback Reverse serial loopback Built-in self test (BIST) incremental test parallel loopback Express PIPE reverse parallel loopback
Altera Corporation August 2007
Stratix Device Handbook, Volume
Built-In Self-Test
Figure shows available loopback modes. Figure 1-4. Loopback Modes
Transmitter Digital Logic
BIST Incremental Generator BIST PRBS Generator
Analog Receiver Transmitter Logic
Phase Compensation FIFO
Byte Serializer
8B/10B Encoder Express PIPE Reverse Parallel Loopback Parallel Loopback
Serializer
Reverse Serial Loopback
Serial Loopback
BIST Incremental Verify Phase Compensation FIFO Byte Deserializer Rate Match FIFO
BIST PRBS Verify Byte Ordering 8B/10B Decoder Deskew FIFO Word Aligner Deserializer Clock Recovery Unit
Receiver Digital Logic
Built-In Self-Test
gigabit transceiver block contains several features that simplify design verification. Embedded pattern generators pattern verifiers provide simple approach board verification without need design additional logic fabric. BIST pseudo-random binary sequence (PRBS) incremental pattern generators, along with their respective pattern verifiers, provide full self-test path. Stratix transceivers offer multiple reset signals control separate ports transceiver channels blocks. Each unused channel automatically powered down reduce power consumption. Additionally, there dynamic power-down signals each receiver transmitter block.
Reset Power Down
Stratix Device Handbook, Volume
Altera Corporation August 2007
Stratix Transceiver Block Overview
Document Revision History
Table shows revision history this chapter.
Table 1-1. Document Revision History Date Document Version
August 2007 v2.3
Changes Made
Minor text edits.
Summary Changes
February 2007 Changed Mbps Mbps v2.2 "Building Blocks" "Clock Multiplier Unit" Changed 3.125 Gbps Gbps "Building Blocks". Modified following: "Clock Multiplier Unit" "Byte Serializer" "8B/10B Encoder" "Loopback" Updated Figure 1-3. April 2006, v2.1 February 2006, v2.0
Minor change Figures 1-3. Updated "Building Blocks" section. Updated "Word Aligner" section. Updated "Byte Ordering" section. Updated "Loopback" section. Updated "Built-In Self-Test" section.
October 2005 v1.0
Added chapter Stratix Device Handbook.
Altera Corporation August 2007
Stratix Device Handbook, Volume
Reset Power Down
1-10 Stratix Device Handbook, Volume
Altera Corporation August 2007

SIIGX52001-2.3 Stratix® devices combine highly advanced 6.375-Gig

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