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Stratix Device Handbook, Volume
SIII5V1-1.1
Copyright 2007 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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Contents
Chapter Revision Dates xiii About this Handbook
Contact Altera Typographic Conventions
Section Device Core
Chapter Stratix Device Family Overview
Introduction Features Architecture Features Logic Array Blocks Adaptive Logic Modules MultiTrack Interconnect TriMatrix Embedded Memory Blocks Blocks Clock Networks PLLs Banks Structure External Memory Interfaces High Speed Differential Interfaces with 1-10 Socketing Power-On Reset 1-10 Configuration 1-11 Remote System Upgrades 1-11 IEEE 1149.1 (JTAG) Boundary Scan Testing 1-12 Design Security 1-12 Mitigation 1-12 Programmable Power 1-13 Signal Integrity 1-13 Reference Ordering Information 1-14 Software 1-14 Ordering Information 1-15 Document Revision History 1-16
Chapter Logic Array Blocks Adaptive Logic Modules Stratix Devices
Introduction Logic Array Blocks Interconnects Control Signals
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Adaptive Logic Modules Operating Modes Register Chain 2-20 Interconnects 2-22 Clear Preset Logic Control 2-23 Power Management Techniques 2-23 Conclusion 2-24 Document Revision History 2-24
Chapter MultiTrack Interconnect Stratix Devices
Introduction Interconnects Column Interconnects Memory Block Interface Block Interface 3-10 Block Connections Interconnect 3-13 Conclusion 3-14 Document Revision History 3-15
Chapter TriMatrix Embedded Memory Blocks Stratix Devices
Introduction Overview TriMatrix Memory Block Types Parity Support Byte Enable Support Packed Mode Support Address Clock Enable Support Mixed Width Support Asynchronous Clear Error Correction Code (ECC) Support Memory Modes Single Port 4-10 Simple Dual-Port Mode 4-12 True Dual-Port Mode 4-15 Shift-Register Mode 4-17 Mode 4-18 FIFO Mode 4-19 Clocking Modes 4-19 Independent Clock Mode 4-19 Input/Output Clock Mode 4-20 Read/Write Clock Mode 4-20 Single Clock Mode 4-20 Design Considerations 4-20 Selecting TriMatrix Memory Blocks 4-20 Conflict Resolution 4-21 Read During Write 4-21 Power-Up Conditions Memory Initialization 4-24
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Power Management 4-24 Conclusion 4-24 Document Revision History 4-25
Chapter Blocks Stratix Devices
Introduction Block Overview Simplified Operation Operational Modes Overview Block Resource Descriptions 5-10 Input Registers 5-11 Multiplier First-Stage Adder 5-15 Pipeline Register Stage 5-16 Second-Stage Adder 5-16 Round Saturation Stage 5-17 Second Adder Output Registers 5-17 Operational Mode Descriptions 5-18 Independent Multiplier Modes 5-18 18-Bit Multiplier 5-18 36-Bit Multiplier 5-22 Double Multiplier 5-23 Two-Multiplier Adder Mode 5-25 Complex Multiply 5-29 Four-Multiplier Adder 5-31 Multiply Accumulate Mode 5-33 Shift Modes 5-34 Rounding Saturation Mode 5-36 Block Control Signals 5-39 Application Examples 5-41 Example 5-41 Example 5-48 Software Support 5-49 Conclusion 5-49 Document Revision History 5-50
Chapter Clock Networks PLLs Stratix Devices
Introduction Clock Networks Stratix Devices Clock Input Connections PLLs 6-12 Clock Output Connections 6-13 Clock Source Control PLLs 6-14 Clock Control Block 6-16 Clock Enable Signals 6-19 PLLs Stratix Devices 6-21 Stratix Hardware Overview 6-23 Stratix Software Overview 6-27 Clock Feedback Modes 6-30
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Clock Multiplication Division Post-Scale Counter Cascading Programmable Duty Cycle Control Signals Clock Switchover Programmable Bandwidth Phase-Shift Implementation Reconfiguration Spread-Spectrum Tracking Specifications Conclusion Document Revision History
6-36 6-37 6-38 6-38 6-39 6-45 6-48 6-50 6-62 6-62 6-62 6-62
Section Interfaces
Chapter Stratix Device Features
Introduction Stratix Standards Support Standards Voltage Levels Stratix Banks Modular Banks Stratix Structure 7-13 3.3-V Interface 7-15 External Memory Interfaces 7-16 High-Speed Differential with Support 7-16 Programmable Current Strength 7-17 Programmable Slew Rate Control 7-18 Programmable Delay 7-19 Open-Drain Output 7-19 Hold 7-19 Programmable Pull-Up Resistor 7-20 MultiVolt Interface 7-20 Support 7-21 LVDS Input On-Chip Termination (RD) 7-27 Calibration 7-28 Calibration Block Location 7-28 Calibration Block Architecture 7-33 Calibration Modes Operation 7-33 Termination Schemes Standards 7-35 Single-Ended Standards Termination 7-35 Differential Standards Termination 7-36 Design Considerations 7-43 Termination 7-43 Banks Restrictions 7-44
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Placement Guidelines 7-45 Conclusion 7-47 Document Revision History 7-47
Chapter External Memory Interfaces Stratix Devices
Introduction Memory Interfaces Support Data Data Clock/Strobe Pins Optional Parity, BWSn, QVLD Pins 8-18 Address Control/Command Pins 8-19 Memory Clock Pins 8-20 Stratix External Memory Interface Features 8-22 Phase-Shift Circuitry 8-22 Logic Block 8-33 Leveling Circuitry 8-36 Dynamic On-Chip Termination Control 8-39 Element (IOE) Registers 8-39 Features 8-43 8-45 Conclusion 8-45 Document Revision History 8-46
Chapter High-Speed Differential Interfaces Stratix Devices
Introduction Banks LVDS Channels Differential Transmitter Differential Receiver Receiver Data Realignment Circuit (Bit Slip) Dynamic Phase Aligner (DPA) 9-10 Synchronizer 9-11 Differential Termination 9-11 Left/Right PLLs (PLL_Lx/ PLL_Rx) 9-12 Clocking 9-13 Source Synchronous Timing Budget 9-14 Differential Data Orientation 9-15 Differential Position 9-15 Receiver Skew Margin Non-DPA 9-17 Differential Placement Guidelines 9-19 Guidelines DPA-Enabled Differential Channels 9-19 Guidelines DPA-Disabled Differential Channels 9-26 Document Revision History 9-32
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Stratix Device Handbook, Volume
Section III. Socketing, Configuration, Remote Upgrades, Testing
Chapter Socketing Power-On Reset Stratix Devices
Introduction Stratix Hot-Socketing Specifications Devices Driven Before Power-Up Pins Remain Tri-Stated During Power-Up Insertion Removal Stratix Device from Powered-Up System Socketing Feature Implementation Stratix Devices Power-On Reset Circuitry Power-On Reset Specifications Conclusion Document Revision History 10-1 10-1 10-2 10-2 10-2 10-3 10-4 10-6 10-7 10-7
Chapter Configuring Stratix Devices
Introduction 11-1 Configuration Devices 11-1 Configuration Schemes 11-2 Configuration Features 11-4 Configuration Data Decompression 11-5 Design Security Using Configuration Bitstream Encryption 11-9 Remote System Upgrade 11-9 Power-On Reset Circuit 11-9 VCCPGM Pins 11-10 VCCPD Pins 11-10 Fast Passive Parallel Configuration 11-11 Configuration Using Device External Host 11-11 Configuration Using Microprocessor 11-22 Configuration Using Enhanced Configuration Device 11-22 Fast Active Serial Configuration (Serial Configuration Devices) 11-30 Estimating Active Serial Configuration Time 11-37 Programming Serial Configuration Devices 11-38 Passive Serial Configuration 11-41 Configuration Using Device External Host 11-42 Configuration Using Microprocessor 11-49 Configuration Using Configuration Device 11-50 Configuration Using Download Cable 11-61 JTAG Configuration 11-66 STAPL 11-73 Device Configuration Pins 11-73 Conclusion 11-84 Document Revision History 11-84
viii
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Chapter Remote System Upgrades With Stratix Devices
Introduction 12-1 Enabling Remote Update 12-4 Configuration Image Types 12-5 Remote System Upgrade Mode 12-6 Overview 12-6 Remote Update Mode 12-6 Dedicated Remote System Upgrade Circuitry 12-8 Remote System Upgrade Registers 12-10 Remote System Upgrade State Machine 12-13 User Watchdog Timer 12-14 Quartus Software Support 12-15 altremote_update Megafunction 12-15 Conclusion 12-16 Document Revision History 12-16
Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Stratix Devices
Introduction 13-1 IEEE Std. 1149.1 Architecture 13-2 IEEE Std. 1149.1 Boundary-Scan Register 13-4 Boundary-Scan Cells Stratix Device 13-6 IEEE Std. 1149.1 Operation Control 13-9 SAMPLE/PRELOAD Instruction Mode 13-12 EXTEST Instruction Mode 13-14 BYPASS Instruction Mode 13-16 IDCODE Instruction Mode 13-17 USERCODE Instruction Mode 13-18 CLAMP Instruction Mode 13-18 HIGHZ Instruction Mode 13-18 Voltage Support JTAG Chain 13-18 IEEE Std. 1149.1 Circuitry 13-20 IEEE Std. 1149.1 Configured Devices 13-21 IEEE Std. 1149.1 Circuitry (Disabling) 13-21 IEEE Std. 1149.1 Guidelines 13-22 Boundary-Scan Description Language (BSDL) Support 13-23 Conclusion 13-23 References 13-23 Document Revision History 13-24
Section Design Security Single Event Upset (SEU) Mitigation
Chapter Design Security Stratix Devices
Introduction 14-1 Stratix Security Protection 14-2 Security Against Copying 14-2
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Security Against Reverse Engineering Security Against Tampering Decryption Block Flexible Security Storage Stratix Design Security Solution Security Modes Available Supported Configuration Schemes Conclusion Document Revision History
14-2 14-2 14-3 14-3 14-4 14-5 14-6 14-9 14-9
Chapter Mitigation Stratix Devices
Introduction 15-1 Configuration Error Detection 15-2 User Mode Error Detection 15-2 Automated Single Event Upset Detection 15-6 Critical Error Detection 15-7 Error Detection Description 15-8 CRC_ERROR 15-8 CRITICAL ERROR 15-8 Error Detection Block 15-9 Error Detection Registers 15-10 Error Detection Timing 15-12 Software Support 15-13 Recovering From Errors 15-15 Conclusion 15-15 Document Revision History 15-15
Section Power Thermal Management
Chapter Programmable Power Temperature Sensing Diode Stratix Devices
Introduction 16-1 Stratix Power Technology 16-2 Selectable Core Voltage 16-2 Programmable Power Technology 16-3 Relationship Between Selectable Core Voltage Programmable Power Technology 16-4 Stratix External Power Supply Requirements 16-5 Temperature Sensing Diode 16-6 External Connections 16-7 Architecture Description 16-8 Conclusion 16-9 Document Revision History 16-10
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Section Packaging Information
Chapter Stratix Device Packaging Information
Introduction Thermal Resistance Package Outlines Document Revision History 17-1 17-2 17-2 17-2
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Stratix Device Handbook, Volume
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Chapter Revision Dates
chapters this book, Stratix Device Handbook, Volume were revised following dates. Where chapters groups chapters available separately, part numbers listed.
Chapter Stratix Device Family Overview Revised: 2007 Part number: SIII51001-1.1 Chapter Logic Array Blocks Adaptive Logic Modules Stratix Devices Revised: 2007 Part number: SIII51002-1.1 Chapter MultiTrack Interconnect Stratix Devices Revised: November 2006 Part number: SIII51003-1.0 Chapter TriMatrix Embedded Memory Blocks Stratix Devices Revised: 2007 Part number: SIII51004-1.1 Chapter Blocks Stratix Devices Revised: 2007 Part number: SIII51005-1.1 Chapter Clock Networks PLLs Stratix Devices Revised: 2007 Part number: SIII51006-1.1 Stratix Device Features Revised: 2007 Part number: SIII51007-1.1
Chapter
Chapter External Memory Interfaces Stratix Devices Revised: 2007 Part number: SIII51008-1.1 Chapter High-Speed Differential Interfaces Stratix Devices Revised: 2007 Part number: SIII51009-1.1
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Chapter Revision Dates
Stratix Device Handbook, Volume
Chapter Socketing Power-On Reset Stratix Devices Revised: 2007 Part number: SIII51010-1.1 Chapter Configuring Stratix Devices Revised: 2007 Part number: SIII51011-1.1 Chapter Remote System Upgrades With Stratix Devices Revised: 2007 Part number: SIII51012-1.1 Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Stratix Devices Revised: 2007 Part number: SIII51013-1.1 Chapter Design Security Stratix Devices Revised: November 2006 Part number: SIII51014-1.0 Chapter Mitigation Stratix Devices Revised: 2007 Part number: SIII51015-1.1 Chapter Programmable Power Temperature Sensing Diode Stratix Devices Revised: 2007 Part number: SIII51016-1.1 Chapter Stratix Device Packaging Information Revised: 2007 Part number: SIII51017-1.1
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About this Handbook
This handbook provides comprehensive information about Altera® Stratix® family devices.
Contact Altera
most up-to-date information about Altera products, refer following table. Contact Method
Website Website Email Product literature Altera literature services Non-technical support (General) Website Email Email
Contact
Technical support Technical training
Address
www.altera.com/support www.altera.com/training custrain@altera.com www.altera.com/literature literature@altera.com nacomp@altera.com authorization@altera.com
(Software Licensing) Email Note table:
also contact your local Altera sales office sales representative.
Typographic Conventions
Visual
Bold Type with Initial Capital Letters bold type
This document uses typographic conventions shown below.
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \qdesigns directory, drive, chiptrip.gdf file. Document titles shown italic type with initial capital letters. Example: High-Speed Board Design.
Italic Type with Initial Capital Letters
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Preliminary
Typographic Conventions
Stratix Device Handbook, Volume
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Italic type
Meaning
Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file.
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Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles on-line help topics shown quotation marks. Example: "Typographic Conventions." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., resetn. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
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Numbered steps used list items when sequence items important, such steps listed procedure. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. caution indicates required information that needs special consideration understanding should read prior starting continuing with procedure process. warning indicates information that should read prior starting continuing procedure processes. angled arrow indicates should press Enter key. feet direct more information particular topic.
Preliminary
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Section Device Core
This section provides complete overview features relating Stratix® device family, which most architecturally advanced, high performance, power FPGA market place. This section includes following chapters:
Chapter Stratix Device Family Overview Chapter Logic Array Blocks Adaptive Logic Modules Stratix Devices Chapter MultiTrack Interconnect Stratix Devices Chapter TriMatrix Embedded Memory Blocks Stratix Devices Chapter Blocks Stratix Devices Chapter Clock Networks PLLs Stratix Devices
Revision History
Refer each chapter specific revision history. information when each chapter updated, refer Chapter Revision Dates section, which appears full handbook.
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Section
Device Core
Stratix Device Handbook, Volume
Section
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Stratix Device Family Overview
SIII51001-1.1
Introduction
Stratix® family provides most architecturally advanced, high performance, power FPGAs market place. Stratix FPGAs lower power consumption through Altera's innovative Programmable Power Technology, which provides ability turn performance where needed turn down power consumption everywhere else. Selectable Core Voltage latest silicon process optimizations also employed deliver industry's lowest power, high performance FPGAs. Specifically designed ease rapid system integration, Stratix FPGA family offers three family variants optimized meet different application needs:
Stratix family provides balanced logic, memory, multiplier ratios mainstream applications. Stratix family memory multiplier rich data-centric applications. Stratix family contains embedded high-speed serial transceivers extensive internal memory high bandwidth applications.
Modular banks with common bank structure vertical migration lend efficiency flexibility high speed I/O. Package enhancements with dynamic on-chip termination, output delay current strength control provide best-in-class signal integrity. Based 1.1-V, 65-nm all-layer copper SRAM process, Stratix family programmable alternative custom ASICs programmable processors high performance logic, digital signal processing (DSP), embedded designs architects. Stratix devices include optional configuration stream security through volatile non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability required, Stratix devices include automatic error detection circuitry detect data corruption soft errors configuration random-access memory (CRAM) user memory cells.
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Introduction
Features
Stratix devices offer following features:
48,000 338,000 equivalent logic elements (LEs), Table 2,430 20,497 Kbits enhanced TriMatrix memory consisting three block sizes implement true dual-port memory first-in first-out (FIFO) buffers High-speed blocks provide dedicated implementation multipliers MHz), multiplyaccumulate functions, finite impulse response (FIR) filters I/O:GND:PWR ratio 8:1:1 along with on-die on-package decoupling robust signal integrity Programmable Power Technology, which minimizes power while maximizing device performance Selectable Core Voltage, available low-voltage devices ordering code suffix), enables selection lowest power highest performance operation global clocks, regional clocks peripheral clocks device phase-locked loops (PLLs) device that support reconfiguration, clock switchover, programmable bandwidth, clock synthesis dynamic phase shifting Memory interface support with dedicated logic banks Support high-speed external memory interfaces including DDR,DDR2,DDR3 SDRAM, RLDRAM SRAM modular banks 1,104 user pins arranged modular banks that support wide range industry standards Dynamic On-Chip Termination (OCT) with auto calibration support banks High-speed differential support with serializer/deserializer (SERDES) dynamic phase alignment (DPA) circuitry 1.25 Gbps performance Support high-speed networking communications standards including SPI-4.2, SFI-4, SGMII, Utopia Gigabit Ethernet XSLI, Rapid NPSI only high-density, high-performance FPGA with support 256-bit (AES) volatile non-volatile security protect designs Robust on-chip socketing power sequencing support Integrated cyclical redundancy check (CRC) configuration memory error detection with critical error determination high availability systems support Built-in error correction coding (ECC) circuitry detect correct configuration user memory error events
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Stratix Device Family Overview
Nios embedded processor support Support multiple intellectual property megafunctions from Altera® MegaCore® functions Altera Megafunction Partners Program (AMPP)
Table lists Stratix FPGA family features.
Table 1-1. Stratix FPGA Family Features
Device/ Feature Stratix Logic Family
EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SE260 EP3SL340
ALMs
102K 135K 102K
47.5K 67.5K 107.5K 142.5K 200K 255K 337.5K 47.5K 107.5K 255K
blocks
1,040
M144K blocks
MLAB Blocks
1,350 2,150 2,850 4,000 5,100 6,750 1,600 2,150 5,100
Total Total MLAB Memory multipliers PLLs Embedded Kbits (FIR Mode) Kbits Kbits
1,836 2,214 4,203 5,499 7,668 14,688 16,272 5,328 6,183 8,055 14,688 1,344 1,781 2,500 3,188 4,219 1,000 1,344 3,188 2,430 3,058 5,547 7,280 10,168 17,876 20,491 5,922 7,183 9,399 17,876
Stratix Enhanced Family
EP3SE50 EP3SE80 EP3SE110 EP3SE260
Note Table 1-1:
EP3SE260 device rich memory, multiplier resources. Hence, aligns with both logic enhanced variants.
Stratix logic family offers balanced logic, memory, multipliers address wide range applications, while enhanced family offers more memory multipliers logic ideal wireless, medical imaging, military applications. Stratix devices available space-saving FineLine packages (see Table Table 1-3).
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Stratix Device Handbook, Volume
Introduction
Table lists Stratix FPGA package options counts.
Table 1-2. Package Options Counts Note Device
EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SL340 EP3SE50 EP3SE80 EP3SE110 EP3SE260 Note Table 1-2:
arrows indicate vertical migration. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p CLK10n) that used data inputs. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, CLK10n) eight dedicated corner clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, PLL_R1_CLKn) that used data inputs. Bank available EP3SL200 F1517 FPGA.
484-Pin FineLine
780-Pin FineLine
1152-Pin FineLine
1,517-Pin FineLine
1,760-Pin FineLine
1,120
Stratix devices support vertical migration within same package (for example, migrate between EP3SL50 EP3SL70 devices 780-pin FineLine package). Vertical migration allows migrate devices whose dedicated pins, configuration pins, power pins same given package across device densities. ensure that board layout supports migratable densities within package offering, enable applicable vertical migration path within Quartus® software (Assignments menu Device Migration Devices). migrate from family family without increasing number available. This minimizes cost vertical migration.
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Stratix Device Family Overview
Table lists Stratix FBGA package sizes.
Table 1-3. FineLine Package Sizes Dimension
Pitch (mm) Area (mm2) Length/Width (mm/
1.00 23/23
1.00 29/29
1152
1.00 1,225 35/35
1,517
1.00 1,600 40/40
1760
1.00 1,849 43/43
Stratix devices available three speed grades, with being fastest. Stratix devices offered both commercial industrial temperature range ratings with leaded lead-free packages. Selectable Core Voltage available specially marked lowvoltage devices ordering code suffix).
Architecture Features
following section briefly describes various features Stratix family FPGAs.
Logic Array Blocks Adaptive Logic Modules
Logic Array Block (LAB) composed basic building blocks known Adaptive Logic Modules (ALMs) that configured implement logic, arithmetic, register functions. Each consists ALMs, carry chains, shared arithmetic chains, control signals, local interconnect, register chain connection lines. ALMs part unique, innovative logic structure that delivers faster performance, minimizes area, reduces power consumption. ALMs expand traditional 4-input look-up table architecture inputs, increasing performance reducing LEs, logic levels, associated routing. addition, ALMs maximize performance with dedicated functionality efficiently implement adder trees other complex arithmetic functions. Quartus Compiler places associated logic adjacent LABs, allowing local, shared arithmetic chain, register chain connections performance area efficiency. Logic Array Block (LAB) Stratix-III derivative called Memory MLAB), which adds SRAM memory capability LAB. MLAB superset includes features. MLABs support maximum 640-bits simple dual-port Static Random Access Memory (SRAM). Each MLAB configured either block, resulting configuration simple dual port SRAM block. MLAB blocks always co-exist pairs Stratix-III families allowing logic (LABs) traded memory (MLABs).
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Stratix Device Handbook, Volume
Architecture Features
more information LABs ALMs, refer Logic Array Blocks Adaptive Logic Modules Stratix Devices chapter volume Stratix Device Handbook. more information MLAB modes, features design considerations, refer TriMatrix Embedded Memory Blocks Stratix Devices chapter volume Stratix Device Handbook.
MultiTrack Interconnect
Stratix architecture, connections between ALMs, TriMatrix memory, blocks, device pins provided MultiTrack interconnect structure with DirectDrive technology. MultiTrack interconnect consists continuous, performance-optimized column interconnects that span fixed distances. routing structure with fixed length resources devices allows predictable repeatable performance when migrating through different device densities. MultiTrack interconnect provides 1-hop connection adjacent LABs, 2-hop connections adjacent LABs connections adjacent LABs. DirectDrive technology deterministic routing technology that ensures identical routing resource usage function regardless placement device. MultiTrack interconnect DirectDrive technology simplify integration stage block-based designing eliminating reoptimization cycles that typically follow design changes additions. Quartus Compiler also automatically places critical design paths faster interconnects improve design performance.
more information, refer MultiTrack Interconnect Stratix Devices chapter Stratix Device Handbook, Volume
TriMatrix Embedded Memory Blocks
TriMatrix embedded memory blocks provide three different sizes embedded SRAM efficiently address needs Stratix FPGA designs. TriMatrix memory includes following blocks:
640-bit MLAB blocks optimized implement filter delay lines, small FIFO buffers shift registers 9-Kbit blocks that used general purpose memory applications 144-Kbit M144K blocks that ideal processor code storage, packet video frame buffering
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Stratix Device Family Overview
Each embedded memory block independently configured single- dual-port RAM, ROM, shift register Quartus MegaWizard. Multiple blocks same type also stitched together produce larger memories with minimal timing penalty. TriMatrix memory provides 16,272 Kbits embedded SRAM operation.
more information TriMatrix memory blocks, modes, features, design considerations, refer TriMatrix Embedded Memory Blocks Stratix Devices chapter volume Stratix Device Handbook.
Blocks
Stratix devices have dedicated high-performance digital signal processing (DSP) blocks optimized applications requiring high data throughput. Stratix devices provide with ability implement various high performance functions easily. Complex systems such WiMAX, 3GPP WCDMA, CDMA2000, voice over Internet protocol (VoIP), H.264 video compression high-definition television (HDTV) require high performance blocks process data. These system designs typically blocks implement finite impulse response (FIR) filters, complex filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, discrete cosine transform (DCT) functions. Stratix devices have blocks. architectural highlights Stratix block following:
High performance, power optimized, fully pipelined multiplication operations Native support 9-bit, 12-bit, 18-bit, 36-bit word lengths Native support 18-bit complex multiplications Efficient support floating point arithmetic formats (24-bit Single Precision 53-bit Double Precision) Signed unsigned input support Built-in addition, subtraction, accumulation units efficiently combine multiplication results Cascading 18-bit input form tap-delay lines Cascading 44-bit output propagate output results from block next block Rich flexible arithmetic rounding saturation units Efficient barrel shifter support Loopback capability support adaptive filtering
block multipliers optionally feed adder/subtractor accumulator block depending user configuration. This option saves routing resources increases performance, because
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Stratix Device Handbook, Volume
Architecture Features
connections blocks inside block. Additionally, Block input registers efficiently implement shift registers filter applications, Stratix blocks support rounding saturation. Quartus software includes megafunctions that control mode operation blocks based user parameter settings.
more information, refer Blocks Stratix Devices chapter volume Stratix Device Handbook.
Clock Networks PLLs
Stratix devices provide dedicated Global Clock Networks (GCLKs), Regional Clock Networks (RCLKs), Periphery Clock Networks (PCLKs). These clocks organized into hierarchical clock structure that provides unique clock domains GCLK RCLK) within Stratix device allows GCLK RCLK) unique GCLK/RCLK clock sources device quadrant. Stratix delivers abundant resources with PLLs device outputs PLL. Every output independently programmed creating unique, customizable clock frequency with fixed relation other input output clock. Inherent jitter filtration fine granularity control over multiply, divide ratios dynamic phase-shift reconfiguration provide high-performance precision required today's high-speed applications. Stratix device PLLs feature rich, supporting advanced capabilities such clock switchover, reconfigurable phase shift, reconfiguration, reconfigurable bandwidth. PLLs used general-purpose clock management supporting multiplication, phase shifting, programmable duty cycle. Stratix PLLs also support external feedback mode, spread-spectrum input clock tracking post-scale counter cascading.
more information, refer Clock Networks PLLs Stratix Devices chapter volume Stratix Device Handbook.
Banks Structure
Stratix devices contain modular banks, each which contains I/Os. This modular bank structure improves efficiency eases device migration. left right side banks contain circuitry support external memory interfaces speeds high-speed differential interfaces meeting 1.25 Gbps performance. bottom banks contain circuitry support external memory interfaces speeds MHz, high-speed differential inputs outputs running speeds respectively.
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Stratix Device Family Overview
Stratix devices support wide range industry standards, including single-ended, voltage referenced single-ended, differential standards. Stratix supports programmable hold, programmable pull-up resistor, programmable slew rate, programmable output delay control, open-drain output. Stratix devices also support on-chip series (RS) on-chip parallel (RT) termination with auto calibration single-ended standards on-chip differential termination (RD) LVDS standards Left/Right banks. Dynamic also supported bi-directional pins banks.
more information, refer Stratix Device Features chapter volume Stratix Device Handbook.
External Memory Interfaces
Stratix structure been completely redesigned from ground provide flexibility enable high-performance support existing emerging external memory standards such DDR, DDR2, DDR3, QDRII, QDRII+ RLDRAMII frequencies MHz. Packed with features such dynamic on-chip termination, trace mismatch compensation, read/write levelling, half-rate registers, 36-bit programmable group widths, Stratix I/O's supply built functionality required rapid robust implementation external memory interfaces. Double data-rate support found sides Stratix device. Stratix devices provide efficient architecture quickly easily wide external memory interfaces exactly where want them. self-calibrating soft core (ALTMEMPHY) optimized take advantage Stratix device along with Quartus timing analysis tool (TimeQuest) provide total solution highest reliable frequency operation across process voltage temperature.
more information external memory interfaces, refer External Memory Interfaces Stratix Devices chapter volume Stratix Device Handbook.
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Architecture Features
High Speed Differential Interfaces with
Stratix devices contain dedicated circuitry supporting differential standards speeds 1.25 Gbps. high-speed differential circuitry supports following high speed interconnect standards applications: Utopia SPI-4.2, SFI-4, Gigabit Ethernet XSLI, Rapid I/O, NPSI. Stratix devices support SERDES modes high speed differential interfaces SERDES modes when using dedicated circuitry. minimizes errors, simplifies layout timing management high-speed data transfer, eliminates channel-to-channel channelto-clock skew high-speed data transmission systems. Soft also implemented, enabling low-cost 1.25-Gbps clock embedded serial links. Stratix devices have following dedicated circuitry high-speed differential support:
Differential buffer Transmitter serializer Receiver deserializer Data realignment Dynamic phase aligner (DPA) Soft functionality Synchronizer (FIFO buffer) PLLs
more information, refer High Speed Differential Interfaces with Stratix Devices chapter volume Stratix Device Handbook.
Socketing Power-On Reset
Stratix devices hot-socketing compliant. socketing also known plug-in swap, power sequencing support without external devices. Robust on-chip hot-socketing power-sequencing support ensures proper device operation independent power-up sequence. insert remove Stratix board system during system operation without causing undesirable effects running system board that inserted into system. hot-socketing feature also makes easier Stratix devices printed circuit boards (PCBs) that also contain mixture 3.0-V, 2.5-V, 1.8-V, 1.5-V 1.2-V devices. With Stratix socketing feature, longer need ensure proper power-up sequence each device board.
1-10 Stratix Device Handbook, Volume
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Stratix Device Family Overview
more information, refer Socketing Power-On Reset Stratix Devices chapter volume Stratix Device Handbook.
Configuration
Stratix devices configured using following four configuration schemes:
Fast passive parallel (FPP) Fast active serial (AS) Passive serial (PS) Joint Test Action Group (JTAG)
configuration schemes either external controller (for example, MAX® device microprocessor), configuration device, download cable. Stratix devices support configuration data decompression, which saves configuration memory space time. This feature allows store compressed configuration data configuration devices other memory transmit this compressed bitstream Stratix devices. During configuration, Stratix device decompresses bitstream real time programs SRAM cells. Stratix devices support decompression when using device/microprocessor flash, fast configuration schemes. Stratix decompression feature available when using enhanced configuration device JTAG configuration schemes.
more information, refer Configuring Stratix Devices chapter volume Stratix Device Handbook.
Remote System Upgrades
Stratix devices feature remote system upgrade capability, allowing error-free deployment system upgrades from remote location securely reliably. Soft logic (either Nios embedded processor user logic) implemented Stratix device download configuration image from remote location, store configuration memory, direct dedicated remote system upgrade circuitry initiate reconfiguration cycle. dedicated circuitry performs error detection during after configuration process, recover from error condition reverting back safe configuration image, provides error status information. This dedicated remote system upgrade circuitry unique Stratix series FPGAs helps avoid system downtime.
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Architecture Features
more information refer Remote System Upgrades with Stratix Devices chapter volume Stratix Device Handbook.
IEEE 1149.1 (JTAG) Boundary Scan Testing
Stratix devices support JTAG IEEE Std. 1149.1 specification. Boundary-Scan Test (BST) architecture offers capability test connections without using physical test probes capture functional data while device operating normally. Boundary-scan cells Stratix device force signals onto pins capture data from logic array signals. Forced test data serially shifted into boundaryscan cells. Captured data serially shifted externally compared expected results. addition BST, IEEE Std. 1149.1 controller Stratix device in-circuit reconfiguration (ICR).
more information refer IEEE 1149.1 (JTAG) Boundary Scan Testing Stratix Devices chapter volume Stratix Device Handbook.
Design Security
Stratix devices only high-density, high-performance FPGAs with support 256-bit volatile non-volatile security keys protect designs against copying, reverse engineering, tampering. Stratix devices have ability decrypt configuration bitstream using Advanced Encryption Standard (AES) algorithm, industry standard encryption algorithm that FIPS-197 certified requires 256-bit security key. design security feature available when configuring Stratix FPGAs using fast passive parallel (FPP) configuration mode with external host (such device microprocessor), when using fast active serial (AS) passive serial (PS) configuration schemes.
more information design security feature, refer Design Security Stratix Devices chapter volume Stratix Device Handbook.
Mitigation
Stratix devices have built-in error detection circuitry detect data corruption soft errors configuration random-access memory (CRAM) cells. This feature allows CRAM contents read verified continuously during user mode operation match configuration-computed value. enhanced circuit frame-based configuration architecture allows detection location multiple, single, adjacent errors which, conjunction with soft
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Stratix Device Family Overview
circuit supplied reference design, allows don't-care soft errors CRAM ignored during device operation. This provides step decrease effective soft error rate, increasing system reliability. On-chip memory block mitigation also offered using configurable Megafunction Quartus MLAB blocks while M144K memory blocks have built-in error correction code (ECC) circuitry.
more information dedicated error detection circuitry, refer Mitigation Stratix Devices chapter volume Stratix Device Handbook.
Programmable Power
Stratix delivers Programmable Power, only FPGA with user programmable power options balancing today's power performance requirements. Stratix devices utilize most advanced power saving techniques including variety process, circuit, architecture optimizations innovations. addition, user controllable power reduction techniques provide optimal balance performance power reduction specific each design configured into Stratix FPGA. Quartus software (starting from Version 6.1) automatically optimizes designs meet performance goals while simultaneously leveraging programmable power saving options available Stratix FPGA without need changes design flow.
more information Programmable Power Stratix devices, refer following documents:
Programmable Power Temperature Sensing Diode Stratix Devices chapter Stratix Device Handbook, Volume Power Optimization Stratix Devices Application Note Stratix Power White Paper
Signal Integrity
Stratix devices simplify challenge signal integrity through number chip, package, board level enhancements enable efficient high speed data transfer into device. These enhancements include:
8:1:1 user I/O/Gnd/Vcc ratio reduce loop inductance package Dedicated power supply each bank, limit I/Os I/Os bank, help limit simultaneous switching noise
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Reference Ordering Information
Programmable slew-rate support with settings match desired standard, control noise, overshoot Programmable output-current drive strength support with settings match desired standard performance Programmable output-delay support control rise/fall times adjust duty cycle, compensate skew reduce simultaneous switching outputs (SSO) noise Dynamic with auto calibration support series parallel differential support LVDS standard left/right banks
more information support Quartus refer Quartus Handbook. following section describes Stratix device software support ordering information.
Reference Ordering Information
Software
Stratix devices supported Altera Quartus design software, version 6.1, which provides comprehensive environment system-on-a-programmable-chip (SOPC) design. Quartus software includes schematic design entry, compilation logic synthesis, full simulation advanced timing analysis, SignalTap® logic analyzer, device configuration. Quartus Handbook more information Quartus software features. Quartus software supports Windows XP/2000/NT/98, Solaris, Linux v7.1 HP-UX operating systems. also supports seamless integration with industry-leading tools through NativeLink® interface.
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Stratix Device Family Overview
Ordering Information
Figure describes ordering codes Stratix devices. more information specific package, refer Package Information Stratix Devices chapter Stratix Device Handbook. Figure 1-1. Stratix Device Packaging Ordering Information
EP3SL Family Signature EP3SL: Stratix Logic EP3SE: Stratix DSP/Memory EP3SGX: Stratix Transceiver Device Type Speed Grade Package Type FineLine (FBGA) Count Number pins particular package: 1152 1517 1760 with being fastest 1152 Optional Suffix Indicates specific device options Engineering sample Lead-free devices Low-voltage devices
Operating Temperature Commercial temperature Industrial temperature
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Document Revision History
Document Revision History
Table shows revision history this document.
Table 1-4. Document Revision History Date Document Version
2007
Changes Made
Minor formatting changes, fixed numbers ALM, MLAB counts Table 1-1.
Summary Changes
November 2006 Initial Release v1.0
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Logic Array Blocks Adaptive Logic Modules Stratix Devices
SIII51002-1.1
Introduction
This chapter describes features logic array block (LAB) Stratix® core fabric. logic array block composed basic building blocks known adaptive logic modules (ALMs) that configured implement logic functions, arithmetic functions, register functions. Each consists ALMs, carry chains, shared arithmetic chains, control signals, local interconnect, register chain connection lines. local interconnect transfers signals between ALMs same LAB. direct link interconnect allows drive into local interconnect left right neighbors. Register chain connections transfer output register adjacent register LAB. Quartus® Compiler places associated logic adjacent LABs, allowing local, shared arithmetic chain, register chain connections performance area efficiency. Figure shows Stratix structure interconnects.
Logic Array Blocks
Altera Corporation 2007
Logic Array Blocks
Figure 2-1. Stratix Structure
Interconnects Variable Speed Length
ALMs Direct link interconnect from adjacent block Direct link interconnect from adjacent block
Direct link interconnect adjacent block
Direct link interconnect adjacent block
Local Interconnect
MLAB Local Interconnect Driven from Either Side Columns LABs, from Above Rows
Column Interconnects Variable Speed Length
Stratix derivative called Memory (MLAB), which adds look-up table (LUT)-based SRAM capability shown Figure 2-2. MLAB supports maximum 640-bits simple dual-port static random access memory (SRAM). configure each MLAB either block, resulting configuration simple dual port SRAM block. MLAB blocks always co-exist pairs Stratix families. MLAB superset includes features. Figure shows overview MLAB topology.
MLAB described detail TriMatrix Embedded Memory Blocks Stratix Devices chapter volume Stratix Device Handbook.
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Figure 2-2. Stratix MLAB Structure
LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM
Control Block
LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM
Control Block
MLAB
Note Figure 2-2:
MLAB regular configure dual-port SRAM, shown.
Interconnects
local interconnect drive ALMs same LAB. driven column interconnects outputs same LAB. Neighboring LABs/MLABs, blocks, M144K blocks, blocks from left right also drive LAB's local interconnect through direct link connection. direct link connection feature minimizes column interconnects, providing higher performance flexibility. Each drive ALMs through fast local direct link interconnects.
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Figure shows direct link connection. Figure 2-3. Direct Link Connection
Direct link interconnect from left LAB, TriMatrix memory block, block, output Direct link interconnect from right LAB, TriMatrix memory block, block, output
ALMs
ALMs
Direct link interconnect left Local Interconnect
Direct link interconnect right
MLAB
Control Signals
Each contains dedicated logic driving control signals ALMs. control signals include three clocks, three clock enables, asynchronous clears, synchronous clear, synchronous load control signals. This gives maximum control signals time. Although generally synchronous load clear signals when implementing counters, also them with other functions. Each unique clock sources three clock enable signals, shown Figure 2-4. control block generate three clocks using clock sources three clock enable signals. Each LAB's clock clock enable signals linked. example, particular using labclk1 signal also uses labclkena1 signal. uses both rising falling edges clock, also uses LAB-wide clock signals. De-asserting clock enable signal turns corresponding LAB-wide clock.
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clocks [5.0] local interconnect generate LAB-wide control signals. MultiTrackinterconnect's inherent skew allows clock control signal distribution addition data. Figure shows control signal generation circuit. Figure 2-4. LAB-Wide Control Signals
There unique clock signals LAB. Dedicated Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0 labclkena0 asyncload labpreset
labclk1 labclkena1
labclk2 labclkena2
syncload labclr0
labclr1 synclr
Adaptive Logic Modules
basic building block logic Stratix architecture, adaptive logic module (ALM), provides advanced features with efficient logic utilization. Each contains variety look-up table (LUT)-based resources that divided between combinational adaptive LUTs (ALUTs) registers. With eight inputs combinational ALUTs, implement various combinations functions. This adaptability allows completely backward-compatible with four-input architectures. also implement function inputs certain seven-input functions.
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Stratix Device Handbook, Volume
Adaptive Logic Modules
addition adaptive LUT-based resources, each contains programmable registers, dedicated full adders, carry chain, shared arithmetic chain, register chain. Through these dedicated resources, efficiently implement various arithmetic functions shift registers. Each drives types interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, direct link interconnects. Figure shows high-level block diagram Stratix while Figure shows detailed view connections ALM. Figure 2-5. High-Level Block Diagram Stratix
shared_arith_in carry_in reg_chain_in labclk general local routing
6-Input
Combinational/Memory ALUT0 dataf0 datae0 dataa datab adder0
general local routing
reg0
datac datad datae1 dataf1
6-Input
adder1
general local routing
reg1 general local routing Combinational/Memory ALUT1 reg_chain_out shared_arith_out carry_out
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syncload aclr[1:0] shared_arith_in clk[2:0] sclr reg_chain_in shared_arith_out
dataf0 datae0
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dataa datab 4-INPUT datac
Figure 2-6. Stratix Details
3-INPUT
local interconnect row, column direct link routing row, column direct link routing
3-INPUT
datad
4-INPUT
3-INPUT
local interconnect row, column direct link routing row, column direct link routing
3-INPUT
datae1 dataf1
Logic Array Blocks Adaptive Logic Modules Stratix Devices
Stratix Device Handbook, Volume
shared_arith_out carry_out
Adaptive Logic Modules
contains programmable registers. Each register data, clock, clock enable, synchronous asynchronous clear, synchronous load/clear inputs. Global signals, general-purpose pins, internal logic drive register's clock clear control signals. Either general-purpose pins internal logic drive clock enable. combinational functions, register bypassed output drives directly outputs ALM. Each sets outputs that drive local, row, column routing resources. LUT, adder, register output drive these output drivers (refer Figure 2-6). each output drivers, outputs drive column, row, direct link routing connections, these outputs also drive local interconnect resources. This allows adder drive output while register drives another output. This feature, called register packing, improves device utilization because device register combinational logic unrelated functions. Another special packing mode allows register output feed back into same that register packed with fan-out LUT. This provides another mechanism improved fitting. also drive registered unregistered versions adder output.
Operating Modes
Stratix operate following modes:
Normal Extended Mode Arithmetic Shared Arithmetic LUT-Register
Each mode uses resources differently. each mode, eleven available inputs ALM-the eight data inputs from local interconnect, carry-in from previous LAB, shared arithmetic chain connection from previous LAB, register chain connection-are directed different destinations implement desired logic function. LAB-wide signals provide clock, asynchronous clear, synchronous clear, synchronous load, clock enable control register. These LAB-wide signals available modes. Refer "LAB Control Signals" page more information LAB-wide control signals.
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Quartus software supported third-party synthesis tools, conjunction with parameterized functions such library parameterized modules (LPM) functions, automatically choose appropriate mode common functions such counters, adders, subtractors, arithmetic functions.
Normal Mode
normal mode suitable general logic applications combinational functions. this mode, eight data inputs from local interconnect inputs combinational logic. normal mode allows functions implemented Stratix ALM, implement single function inputs. support certain combinations completely independent functions various combinations functions that have common inputs. Figure shows supported combinations normal mode.
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Stratix Device Handbook, Volume
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Figure 2-7. Normal Mode Note
dataf0 datae0 datac dataa datab datad datae1 dataf1
4-Input
combout0
dataf0 datae0 datac dataa datab
5-Input
combout0
4-Input
combout1 datad datae1 dataf1
5-Input
combout1
dataf0 datae0 datac dataa datab
5-Input
combout0
datad datae1 dataf1
dataf0 datae0 dataa datab datac datad
6-Input
combout0
3-Input
combout1
dataf0 datae0 datac dataa datab
5-Input
combout0
dataf0 datae0 dataa datab datac datad
6-Input
combout0
datad datae1 dataf1
4-Input
combout1
datae1 dataf1
6-Input
combout1
Note Figure 2-7:
Combinations functions with fewer inputs than those shown also supported. example, combinations functions with following number inputs supported:
normal mode provides complete backward compatibility with four-input architectures. packing five-input functions into ALM, functions must have least common inputs. common inputs dataa datab. combination four-input function with five-input function requires common input (either dataa datab).
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case implementing six-input functions ALM, four inputs must shared combinational function must same. example, crossbar switch (two 4-to-1 multiplexers with common inputs unique select lines) implemented ALM, shown Figure 2-8. shared inputs dataa, datab, datac, datad, while unique select lines datae0 dataf0 function0, datae1 dataf1 function1. This crossbar switch consumes four LUTs four-input LUT-based architecture. Figure 2-8. Crossbar Switch Example
Crossbar Switch sel0[1.0] inputa inputb inputc inputd out1 sel1[1.0] datae1 dataf1 Six-Input (Function1) out0 dataf0 datae0 dataa datab datac datad Implementation
Six-Input (Function0)
combout0
combout1
sparsely used device, functions that could placed into implemented separate ALMs Quartus software order achieve best possible performance. device begins fill Quartus software automatically utilizes full potential Stratix ALM. Quartus Compiler automatically searches functions common inputs completely independent functions placed into make efficient device resources. addition, manually control resource usage setting location assignments. six-input function implemented utilizing inputs dataa, datab, datac, datad, either datae0 dataf0 datae1 dataf1. datae0 dataf0 utilized, output driven register0, and/or register0 bypassed data drives interconnect using output drivers (refer Figure 2-9). datae1 dataf1 utilized, output drives register1 and/or bypasses register1 drives interconnect using bottom output drivers. Quartus Compiler automatically selects inputs LUT. ALMs normal mode support register packing.
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Adaptive Logic Modules
Figure 2-9. Input Function Normal Mode Note
dataf0 datae0 dataa datab datac datad datae1 dataf1 labclk These inputs available register packing. general local routing 6-Input
general local routing
reg0
general local routing
reg1
Notes Figure 2-9:
datae1 dataf1 used inputs six-input function, then datae0 dataf0 available register packing. dataf1 input available register packing only six-input function un-registered.
Extended Mode
extended mode implement specific seven-input functions. must 2-to-1 multiplexer arbitrary five-input functions sharing four inputs. Figure 2-10 shows template supported seven-input functions utilizing extended mode. this mode, seven-input function unregistered, unused eighth input available register packing. Functions that into template shown Figure 2-10 occur naturally designs. These functions often appear designs "if-else" statements Verilog VHDL code.
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Figure 2-10. Template Supported Seven-Input Functions Extended Mode
datae0 datac dataa datab datad dataf0 5-Input combout0
general local routing general local routing
5-Input datae1 dataf1 This input available register packing.
reg0
Note Figure 2-10:
seven-input function unregistered, unused eighth input available register packing. second register, reg1, available.
Arithmetic Mode
arithmetic mode ideal implementing adders, counters, accumulators, wide parity functions, comparators. arithmetic mode uses sets four-input LUTs along with dedicated full adders. dedicated adders allow LUTs available perform pre-adder logic; therefore, each adder output four-input functions. four LUTs share dataa datab inputs. shown Figure 2-11, carry-in signal feeds adder0, carry-out from adder0 feeds carry-in adder1. carry-out from adder1 drives adder0 next LAB. ALMs arithmetic mode drive registered and/or unregistered versions adder outputs.
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Figure 2-11. Arithmetic Mode
carry_in datae0 4-Input
adder0 general local routing general local routing
dataf0 datac datab dataa
4-Input
reg0
datad datae1
4-Input
adder1 general local routing
general local routing
4-Input dataf1
reg1
carry_out
While operating arithmetic mode, support simultaneous adder's carry output along with combinational logic outputs. this operation, adder output ignored. This usage adder with combinational logic output provides resource savings functions that this ability. example such functionality conditional operation, such shown Figure 2-12.
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Figure 2-12. Conditional Operation Example
Adder output used. X[0] Y[0] syncdata X[1] Y[1] Comb Adder Logic X[1]
Comb Adder Logic
X[0] R[0]
general local routing
reg0 syncload
R[1]
general local routing
reg1 Carry Chain X[2] Y[2] Comb Adder Logic syncload
X[2]
R[2]
general local routing
reg0 syncload Comb Adder Logic carry_out local routing then LAB-wide syncload
equation this example implement this function, adder used subtract from less than carry_out signal carry_out signal adder where drives local interconnect. then feeds LAB-wide syncload signal. When asserted, syncload selects syncdata input. this case, data drives syncdata inputs registers. greater than equal syncload signal de-asserted drives data port registers. arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, synchronous load. local interconnect data inputs generate clock enable, counter enable, synchronous up/down,
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Adaptive Logic Modules
add/subtract control signals. These control signals good candidates inputs that shared between four LUTs ALM. synchronous clear synchronous load options LAB-wide signals that affect registers LAB. These signals also individually disabled enabled register. Quartus software automatically places registers that used counter into other LABs. Carry Chain carry chain provides fast carry function between dedicated adders arithmetic shared arithmetic mode. two-bit carry select feature Stratix devices halves propagation delay carry chains within ALM. Carry chains begin either first fifth LAB. final carry-out signal routed ALM, where local, row, column interconnects. Quartus Compiler automatically creates carry chain logic during design processing, create manually during design entry. Parameterized functions such functions automatically take advantage carry chains appropriate functions. Quartus Compiler creates carry chains longer than ALMs arithmetic shared arithmetic mode) linking LABs together automatically. enhanced fitting, long carry chain runs vertically allowing fast horizontal connections TriMatrixmemory blocks. carry chain continue full column. avoid routing congestion small area device when high fan-in arithmetic function implemented, support carry chains that only utilize either half bottom half before connecting next LAB. This leaves other half ALMs available implementing narrower fan-in functions normal mode. Carry chains that five ALMs first carry into half ALMs next within column. Carry chains that bottom five ALMs first carry into bottom half ALMs next within column. every alternate column, half bypassed; other MLAB columns, bottom half bypassed. Refer "ALM Interconnects" page 2-22 more information carry chain interconnect.
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Shared Arithmetic Mode
shared arithmetic mode, implement three-input within ALM. this mode, configured with four-input LUTs. Each either computes three inputs carry three inputs. output carry computation next adder (either adder1 same adder0 next LAB) dedicated connection called shared arithmetic chain. This shared arithmetic chain significantly improve performance adder tree reducing number summation stages required implement adder tree. Figure 2-13 shows using this feature. Figure 2-13. Shared Arithmetic Mode
shared_arith_in carry_in labclk 4-Input
general local routing general local routing
datae0 datac datab dataa
4-Input
reg0
datad datae1
4-Input
general local routing general local routing
4-Input
reg1
carry_out shared_arith_out
find adder trees many different applications. example, summation partial products logic-based multiplier implemented tree structure. Another example correlator function that large adder tree filtered data samples given time frame recover de-spread data that transmitted utilizing spread spectrum technology.
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Adaptive Logic Modules
example three-bit operation utilizing shared arithmetic mode shown Figure 2-14. partial (S[3.0]) partial carry (C[3.0]) obtained using LUTs, while result (R[3.0]) computed using dedicated adders. Figure 2-14. Example 3-Bit Utilizing Shared Arithmetic Mode
shared_arith_in carry_in Implementation
3-Bit Example
stage implemented LUTs.
3-Input
3-Input
stage implemented
3-Input
3-Input 3-Input 3-Input
Binary
Decimal Equivalents
1110 0100 +1101 0111 +1100 11111
3-Input
3-Input
Shared Arithmetic Chain shared arithmetic chain available enhanced arithmetic mode allows implement three-input add. This significantly reduces resources necessary implement large adder trees correlator functions. shared arithmetic chains begin either first sixth LAB. Quartus Compiler creates shared arithmetic chains longer than ALMs arithmetic shared arithmetic mode) linking
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LABs together automatically. enhanced fitting, long shared arithmetic chain runs vertically allowing fast horizontal connections TriMatrix memory blocks. shared arithmetic chain continue full column. Similar carry chains, bottom half shared arithmetic chains alternate columns bypassed. This capability allows shared arithmetic chain cascade through half ALMs while leaving other half available narrower fan-in functionality. Every other column top-half bypassable, while other columns bottom-half bypassable. Refer "ALM Interconnects" page 2-22 more information shared arithmetic chain interconnect.
LUT-Register Mode
LUT-Register mode allows third register capability within ALM. internal feedback loops allow combinational ALUT1 implement master latch combinational ALUT0 implement slave latch needed third register. register shares clock, clock enable, asynchronous clear sources with dedicated register. Figure 2-15 shows register constructed using combinational blocks within ALM. Figure 2-16 shows LUT-Register mode. Figure 2-15. Register from Combinational Blocks
aclr 4-input sumout regout combout
sumout datain(datac) sclr 5-input combout
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Adaptive Logic Modules
Figure 2-16. LUT-Register Mode with 3-Register Capability
[2:0] aclr [1:0] reg_chain_in
datain lelocal aclr aclr sclr regout latchout sdata leout regout datain
leout
lelocal aclr datain leout regout
sdata
leout
reg_chain_out
Register Chain
addition general routing outputs, ALMs have register chain outputs. register chain routing allows registers same cascaded together. register chain interconnect allows LUTs single combinational function registers used unrelated shift register implementation. These resources speed connections between ALMs while saving local interconnect resources (refer Figure 2-17). Quartus Compiler automatically takes advantage these resources improve utilization performance.
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Figure 2-17. Register Chain within Note
From previous within reg_chain_in labclk general local routing adder0
general local routing
reg0 Combinational Logic adder1
general local routing
reg1 general local routing
general local routing adder0
general local routing
reg0 Combinational Logic adder1
general local routing
reg1 general local routing
reg_chain_out next within
Note Figure 2-17:
combinational adder logic implement unrelated, un-registered function.
Refer "ALM Interconnects" page 2-22 more information register chain interconnect.
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Adaptive Logic Modules
Interconnects
There three dedicated paths between ALMs: Register Cascade, Carry-chain, Shared Arithmetic chain. Stratix devices include enhanced interconnect structure LABs routing shared arithmetic chains carry chains efficient arithmetic functions. register chain connection allows register output connect directly register input next fast shift registers. These ALM-to-ALM connections bypass local interconnect. Quartus Compiler automatically takes advantage these resources improve utilization performance. Figure 2-18 shows shared arithmetic chain, carry chain, register chain interconnects. Figure 2-18. Shared Arithmetic Chain, Carry Chain, Register Chain Interconnects
Local interconnect routing among ALMs Carry chain shared arithmetic chain routing adjacent
Register chain routing adjacent ALM's register input
Local interconnect
Refer MultiTrack Interconnect Stratix Devices chapter volume Stratix Device Handbook information routing between LABs.
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Clear Preset Logic Control
LAB-wide signals control logic register's clear signal. directly supports asynchronous clear function. achieve register preset through Quartus software's NOT-gate push-back logic option. Each supports clears. Stratix devices provide device-wide reset (DEV_CLRn) that resets registers device. option before compilation Quartus software controls this pin. This device-wide reset overrides other control signals.
Power Management Techniques
following techniques used manage static dynamic power consumption within LAB:
Stratix low-voltage devices ordering code suffix) offer selectable core voltage reduce both power. save power, Quartus forces adder inputs when adders use. Stratix LABs operate high-performance mode low-power mode. Quartus software automatically chooses appropriate mode based design optimize speed leakage trade-offs. Clocks represent significant portion dynamic power consumption their high switching activity long paths. clock that distributes clock signal registers within significant contributor overall clock power consumption. Each LAB's clock clock enable signal linked. example, combinational ALUT register particular using labclk1 signal also uses labclkena1 signal. disable LAB-wide clock power consumption without disabling entire clock tree, LAB-wide clock enable gate LAB-wide clock. Quartus software automatically promotes register-level clock enable signals LAB-level. registers within that share common clock clock enable controlled shared gated clock. take advantage these clock enables, clock enable construct your code registered logic.
Refer Power Optimization section Quartus Handbook details implementation. Refer Programmable Power Temperature Sensing Diode Stratix Devices chapter volume Stratix Device Handbook detailed information Stratix programmable power capabilities.
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Conclusion
Conclusion
Logic array block adaptive logic modules basic building blocks Stratix device. these configure logic functions, arithmetic functions, register functions. provides advanced features with efficient logic utilization completely backward-compatible.
Document Revision History
Table shows revision history this document.
Table 2-1. Document Revision History Date Document Version
2007 v1.1
Changes Made
Minor formatting changes, updated Figure include missing connection.
Summary Changes
November 2006 Initial Release v1.0
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Introduction
Stratix® devices contain two-dimensional row- column-based architecture implement custom logic. series column interconnects varying length speed provides signal interconnects between logic array blocks (LABs), memory block structures, digital signal processing (DSP) blocks, input/output elements (IOE). These blocks communicate with themselves another through fabric routing wires. This chapter provides details Stratix core routing structure. also describes Stratix block types interface this fabric. Stratix architecture, connections between adaptive logic modules (ALMs), TriMatrix memory, blocks, device pins provided MultiTrack interconnect structure with DirectDrive technology. MultiTrack interconnect consists continuous, performance-optimized routing lines different lengths speeds used inter- intra-design block connectivity. Quartus® Compiler automatically routes critical design paths faster interconnects improve design performance. DirectDrive technology deterministic routing technology that ensures identical routing resource usage function regardless placement device. MultiTrack interconnect DirectDrive technology simplify integration stage block-based designing eliminating re-optimization cycles that typically follow design changes additions. MultiTrack interconnect consists column interconnects that span fixed distances. routing structure with fixed length resources devices allows predictable repeatable performance when migrating through different device densities.
Interconnects
Dedicated interconnects route signals from LABs, blocks, TriMatrix memory blocks same row. These interconnect resources include:
Direct link interconnects between LABs adjacent blocks interconnects traversing four blocks right left interconnects high-speed access across length device
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Interconnects
direct link interconnect allows LAB, block, TriMatrix memory block drive into local interconnect left right neighbors. This capability provides fast communication between adjacent LABs blocks without using interconnect resources. direct link interconnect fastest communicate between adjacent blocks. interconnects span combination four LABs, memory logic array blocks (MLAB), blocks, blocks, M144K blocks. these resources fast connections four-LAB region. Figure shows interconnect connections from LAB. interconnects drive driven blocks blocks IOEs. interfacing, primary neighbor drive given interconnect. interconnects that drive right, primary right neighbor drive interconnect. interconnects that drive left, primary left neighbor drive interconnect. interconnects drive other interconnects extend range LABs they drive. interconnects also drive (column interconnects) connections from another. Additionally, interconnects drive interconnects. Figure 3-1. Interconnect Connections Notes (1),
Adjacent Drive onto Another LAB's Interconnect Interconnect Driving Left Column Interconnects Interconnect Driving Right
Neighbor
MLAB
Neighbor
Notes Figure
interconnects drive interconnects. This pattern repeated every row.
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interconnects span LABs provide fastest resource connections between distant LABs, TriMatrix memory, blocks, IOEs. interconnects drive local interconnects interconnects. interconnects drive R20, C12, interconnects.
Column Interconnects
column interconnect operates similarly interconnect. vertically routes signals from LABs, TriMatrix memory, blocks, IOEs. Each column LABs served dedicated column interconnect. These column interconnect resources include:
Shared arithmetic chain interconnects from Carry chain interconnects from Register chain interconnects interconnects traversing distance four blocks same device column column interconnects high-speed vertical routing through device
Stratix devices include enhanced interconnect structure LABs routing-shared arithmetic chains carry chains efficient arithmetic functions. register chain connection allows register output connect directly register input next fast shift registers. These ALM-to-ALM connections bypass local interconnect. Quartus Compiler automatically takes advantage these resources improve utilization performance. Figure shows shared arithmetic chain, carry chain, register chain interconnects.
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Figure 3-2. Shared Arithmetic Chain, Carry Chain, Register Chain Interconnects
Local Interconnect Routing Among ALMs Carry Chain Shared Arithmetic Chain Routing Adjacent
Register Chain Routing Adjacent ALM's Register Input
Local Interconnect
ALM10
interconnects span four adjacent interfaces same device column. interconnects also pass M144K blocks. single M144K block utilizes eight adjacent interfaces same column. block utilizes four adjacent interfaces same column. Figure shows interconnect connections from column. interconnects drive driven types architecture blocks, including blocks, TriMatrix memory blocks, column IOEs. interconnection, primary neighbor drive given interconnect. interconnects drive each other extend their range well drive interconnects column-to-column connections.
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Figure 3-3. Interconnect Connections Note
Interconnects Drives Local Interconnects Four Rows
Interconnects Driving
Interconnects
Adjacent drive onto neighboring LAB's interconnect
Local Interconnect
Interconnects Driving Down
Note Figure 3-3:
Each interconnect drive either down four rows.
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Column Interconnects
column interconnects span length LABs provide fastest resource column connections between distant LABs, TriMatrix memory blocks, blocks, IOEs. interconnects drive local interconnects interconnects drive local interconnects directly. embedded blocks communicate with logic array through interconnects similar LAB-to-LAB interfaces. Each block (for example, TriMatrix memory blocks blocks) connects column interconnects local interconnect regions driven column interconnects. These blocks also have direct link interconnects fast connections from neighboring LAB. Table shows Stratix device's routing scheme.
Table 3-1. Stratix Device Routing Scheme (Part Destination Source
Shared Arithmetic Chain Carry Chain Register Chain Local Interconnect Direct Link Interconnect Interconnect Interconnect Interconnect Interconnect MLAB Block Block M144K Block Blocks Column
Shared arithmetic chain Carry chain Register chain Local interconnect Direct link interconnect interconnect interconnect interconnect interconnect MLAB block block M144K block
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Table 3-1. Stratix Device Routing Scheme (Part Destination Source
Shared Arithmetic Chain Carry Chain Register Chain Local Interconnect Direct Link Interconnect Interconnect Interconnect Interconnect Interconnect MLAB Block Block M144K Block Blocks Column
blocks Column Notes Table 3-1:
Except column local interconnects. local interconnects. Column local interconnects.
interconnects provide superior flexible routing capabilities. Stratix three-sided routing architecture which allows interconnect wires from each reach adjacent LABs right left. given drive other LABs using interconnect, hop. This routing scheme improves efficiency flexibility placing critical LABs within routing interconnects. Table shows many LABs reachable within one, two, three hops using interconnects.
Table 3-2. Number LABs reachable using interconnects Hops
Number LABs
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Memory Block Interface
Memory Block Interface
TriMatrix memory consists three types blocks: MLAB, M9K, M144K. This section provides brief overview different memory blocks interface routing structure. blocks Stratix devices have local interconnects allow ALMs interconnects drive into blocks. MLAB block local interconnect driven direct link interconnects from adjacent LABs. MLAB blocks communicate with LABs either left right side through these interconnects with columns left right side with column interconnects. Each MLAB block direct link input connections from left adjacent another from right adjacent LAB. MLAB outputs also connect left right LABs through direct link interconnect. MLAB block equal opportunity access performance from LABs either left right side. Figure shows MLAB block interface.
Figure 3-4. MLAB Block Interface
Interconnects Interconnects
Direct link interconnect adjacent
Direct link interconnect adjacent dataout
Direct link interconnect from adjacent
MLAB
Direct link interconnect from adjacent
clocks control signals
datain
address
MLAB Local Interconnect Region
Clocks
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block local interconnect driven direct link interconnects from adjacent LABs. blocks communicate with LABs either left right side through these resources with columns either right left with column resources. direct link input connections Block possible from left adjacent LABs another possible from right adjacent LAB. block outputs also connect left right LABs through direct link interconnect. Figure shows block logic array interface. Figure 3-5. Block Interface
Interconnects Interconnects
Direct link interconnect adjacent
dataout
Direct link interconnect adjacent
Direct link interconnect from adjacent datain control signals clocks byte enable Direct link interconnect from adjacent
address
Local Interconnect
Clocks
M144K blocks eight interfaces same device column. M144K block local interconnects driven direct link interconnects from adjacent LABs either right left side MRAM block. direct link input connections M144K block possible from left adjacent LABs another possible from right adjacent LAB. M144K block outputs also connect LABs block's left right sides through direct link interconnect. Figure shows interface between M144K block logic array.
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Block Interface
Figure 3-6. M144K Unit Interface Interconnect
Interconnects Interconnects Interconnects
M144K Block
dataout_a[
Direct Link Interconnects
datain_a[ addressa[ addressstall rden/wren byteena[ clocken_a clock_a aclr
Direct Link Interconnects
Interface Block M144K Block Interface Block Interconnect Region
Interface Block M144K Block Interface Block Interconnect Region
Block Interface
Stratix device block input registers generate shift register that cascades down same block column. Dedicated connections between blocks provide fast connections between shift register inputs cascade shift register chains. cascade registers within multiple blocks 9-bit 18-bit finite impulse response (FIR) filters larger than four taps, with additional adder stages implemented ALMs. block configured 36-bit blocks, adder, subtractor, accumulator stages implemented ALMs. Each block route shift register chain block cascade multiple columns blocks. block divided into four block units that interface with four rows left right. consider each block unit 18-bit multipliers followed adder with inputs outputs. local interconnect region associated with each block. Like LAB, this interconnect region with direct link interconnects from left right block same row. routing resources access block's local interconnect region.
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These outputs work similarly outputs. Eighteen outputs from block drive left through direct link interconnects eighteen drive right though direct link interconnects. outputs drive routing interconnects. Outputs drive right- left-column routing. Figures show block interfaces rows. Figure 3-7. High-Level View, Block Interface Interconnect
Block
Direct Link Interconnects
OA[17.0] OB[17.0] A1[35.0] B1[35.0]
Direct Link Interconnects
OC[17.0] OD[17.0] A2[35.0] B2[35.0]
OE[17.0] OF[17.0]
A3[35.0] B3[35.0]
OG[17.0] OH[17.0]
A4[35.0] B4[35.0]
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Block Interface
Figure 3-8. Detailed View, Block Interface Interconnect
Interconnects Direct Link Interconnect from Adjacent Interconnects Direct Link Outputs Adjacent LABs Direct Link Interconnect from Adjacent
Block Structure
Control A[35.0] B[35.0] OA[17.0] OB[17.0]
Interface Block Block Interface Block Interconnect Region Inputs Outputs
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Block Connections Interconnect
IOEs located blocks around periphery Stratix device. There four IOEs block four IOEs column block. blocks drive row, column, direct link interconnects. column blocks drive column interconnects. Figure shows block connects logic array. Figure 3-10 shows column block connects logic array.
Figure 3-9. Block Connection Interconnect
Interconnects
Interconnects
Interconnects Block Local Interconnect
Data Control Signals from Logic Array Horizontal Block
io_dataina[3.0] io_datainb[3.0]
Direct Link Interconnect Adjacent Local Interconnect
Direct Link Interconnect from Adjacent
Horizontal Block Contains Four IOEs
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Conclusion
Figure 3-10. Column Block Connection Interconnect
Data Control Signals from Logic Array
Vertical Block
Vertical Block Contains Four IOEs
IO_dataina[3:0] IO_datainb[3:0]
io_clk[7.0]
Block Local Interconnect
Interconnects
MLAB
Local Interconnects
Interconnects Interconnects
Conclusion
Stratix devices consist array logic blocks such LABs, TriMatrix memory, blocks, IOEs. These blocks communicate with themselves another through MultiTrack interconnect structures. Quartus compiler automatically routes critical design paths faster interconnects improve design performance optimize device resources.
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Document Revision History
Table shows revision history this document.
Table 3-3. Document Revision History Date Document Version
November 2006 Initial Release v1.0
Changes Made
Summary Changes
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Document Revision History
3-16 Stratix Device Handbook, Volume
Altera Corporation November 2006
TriMatrix Embedded Memory Blocks Stratix Devices
SIII51004-1.1
Introduction
TriMatrix embedded memory blocks provide three different sizes embedded SRAM efficiently address needs Stratix® FPGA designs. TriMatrix memory includes 640-bit memory logic array blocks (MLABs), 9-Kbit blocks, 144-Kbit M144K blocks. MLABs have been optimized implement filter delay lines, small first-in first-out (FIFO) buffers, shift registers. blocks general purpose memory applications, M144K blocks ideal processor code storage, packet buffering, video frame buffering. independently configure each embedded memory block single- dual-port RAM, FIFO, ROM, shift register Quartus® MegaWizard. stitch together multiple blocks same type produce larger memories with minimal timing penalty. TriMatrix memory provides 20,491 Kbits embedded SRAM operation. This chapter describes TriMatrix memory blocks, modes, features, design considerations.
Overview
Table summarizes features supported three sizes TriMatrix memory.
Table 4-1. Summary TriMatrix Memory Features (Part Feature
Maximum performance Total bits (including parity bits) Configurations (depth width)
MLABs
Blocks
9,216
M144K Blocks
147,456
Parity bits Byte enable
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Overview
Table 4-1. Summary TriMatrix Memory Features (Part Feature
Packed mode Address clock enable Single-port memory Simple dual-port memory True dual-port memory Embedded shift register FIFO buffer Simple dual-port mixed width support True dual-port mixed width support Memory initialization file (.mif) Mixed-clock mode Power-up condition Outputs cleared registered, otherwise reads memory contents. Output registers Write: Falling clock edges Read: Rising clock edges Outputs data Outputs data Soft support Quartus
MLABs
Blocks
Outputs cleared
M144K Blocks
Outputs cleared
Register clears Write/Read operation triggering
Output registers Write Read: Rising clock edges
Output registers Write Read: Rising clock edges
Same-port read-during-write Mixed-port read-during-write Support
Outputs Outputs data data Outputs Outputs data data Soft support Quartus Built-in support wide mode soft support Quartus
Note Table 4-1:
These features natively supported architecture, achieved through emulation Quartus software.
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Table shows capacity distribution TriMatrix memory blocks each Stratix family member
Table 4-2. TriMatrix Memory Capacity Distribution Stratix Devices Device
EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SL340 EP3SE50 EP3SE80 EP3SE110 EP3SE260
MLABs
1,350 2,150 2,850 4,000 6,750 1,600 2,150 5,100
Blocks
1,040
M144K Blocks
Total Dedicated Bits (dedicated memory blocks only)
1,836 2,214 4,203 5,499 7,668 16,272 5,328 6,183 8,055 14,688
Total Bits (including MLABs)
2,430 3,058 5,547 7,280 10,168 20,491 5,922 7,183 9,399 17,876
TriMatrix Memory Block Types
While M144K memory blocks dedicated resources, MLABs dual-purpose blocks. They configured regular logic array blocks (LABs) memory logic array blocks (MLABs). ALMs make MLAB. Each MLAB configured either block, resulting simple dual-port SRAM block single MLAB.
Parity Support
TriMatrix memory blocks have built-in parity-bit support. ninth associated with each byte store parity serve additional data bit. parity function actually performed ninth bit.
Byte Enable Support
TriMatrix memory blocks support byte enables that mask input data that only specific bytes data written. unwritten bytes retain previous written value. write enable (wren) signals, along with byte enable (byteena) signals, control blocks' write operations.
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Overview
default value byte enable signals high (enabled), which case writing controlled only write enable signals. byte enable registers have clear port. When using parity bits M144K blocks, byte enable controls nine bits (eight bits data plus parity bit). When using parity bits MLAB, byte-enable controls bits widest mode. Byte enables operate one-hot fashion, with least significant (LSB) byteena signal corresponding least significant byte data bus. example, using block mode, with byteena data[8.0] enabled data[17.9] disabled. Similarly, byteena both data[8.0] data[17.9] enabled. Byte enables active high. cannot byte enable feature when using error correction coding (ECC) feature M144K blocks.
Figure shows write enable (wren) byte enable (byteena) signals control operations RAM. When byte-enable de-asserted during write cycle, corresponding data byte output appear either "don't care" value current data that location. output value masked byte controllable Quartus software. When byte-enable asserted during write cycle, corresponding data byte output also depends setting chosen Quartus software.
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Figure 4-1. Stratix Byte Enable Functional Waveform
inclock wren address
data
XXXX
ABCD
XXXX
byteena
contents
FFFF
ABFF
contents
FFFF
FFCD
contents
FFFF
ABCD
don't care: (asynch)
doutn doutn
ABXX ABFF
XXCD FFCD
ABCD ABCD
ABFF ABFF
FFCD FFCD
ABCD ABCD
current data: (asynch)
Packed Mode Support
Stratix M144K blocks support packed mode. packed mode feature packs independent single-port RAMs into memory block. Quartus software automatically implements packed mode where appropriate placing physical block into true dual-port mode using most significant (MSB) address distinguish between logical RAMs. size each independent single-port must exceed half target block size.
Address Clock Enable Support
Stratix memory blocks support address clock enable, which holds previous address value long signal enabled (addressstall When memory blocks configured dual-port mode, each port independent address clock enable. default value address clock enable signals (disabled). Figure shows address clock enable block diagram. address clock enable referred port name addressstall.
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Overview
Figure 4-2. Stratix Address Clock Enable Block Diagram
address[0]
address[0] register
address[0]
address[N] addressstall clock
address[N] register
address[N]
Figure shows address clock enable waveform during read cycle. Figure 4-3. Stratix Address Clock Enable during Read Cycle Waveform
inclock rdaddress rden addressstall latched address (inside memory) doutn dout0 dout0 dout1 dout1 dout4 dout4 dout5
(synch) doutn-1 (asynch) doutn
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Figure shows address clock enable waveform during write cycle. Figure 4-4. Stratix Address Clock Enable during Write Cycle Waveform
inclock wraddress data wren addressstall latched address (inside memory) contents contents contents contents contents contents
Mixed Width Support
M144K memory blocks support mixed data widths inherently. MLABs support mixed data widths through emulation Quartus software. When using simple dual-port, true dual-port, FIFO modes, mixed width support allows read write different data widths memory block. "Memory Modes" page details different widths supported memory mode.
Asynchronous Clear
Stratix TriMatrix memory blocks support asynchronous clears output latches output registers. Therefore, your using output registers, still clear outputs output latch asynchronous clear. functional waveform showing this functionality shown Figure 4-5.
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Figure 4-5. Output Latch Asynchronous Clear Waveform
outclk aclr aclr latch
selectively enable asynchronous clears logical memory Quartus MegaWizard.
more information, refer Megafunction User Guide.
Error Correction Code (ECC) Support
Stratix M144K blocks have built-in support error correction code (ECC) when simple dual-port mode. allows detect correct data errors memory array. M144K blocks have single-error-correction double-error-detection (SECDED) implementation. SECDED detect single error 64-bit word detect errors 64-bit word. cannot detect three more errors. M144K status communicated three-bit status flag eccstatus[2.0]. status flag either registered unregistered. When registered, uses same clock asynchronous clear signals output registers. When registered, cannot asynchronously cleared. Table shows truth table status flags.
Table 4-3. Truth Table Status Flags Status
error Single error fixed Double error Illegal Illegal Illegal Illegal
eccstatus[2]
eccstatus[1]
eccstatus[0]
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cannot byte enable feature when engaged. Read during write "old data" mode supported when engaged.
Figure shows block diagram block M144K. Figure 4-6. Block Diagram M144K
Data Input
SECDED Encoder
Array
SECDED Encoder
Comparator
Error Locator
Flag Generator Status Flags
Error Correction Block Data Output
Memory Modes
Stratix TriMatrix memory blocks allow implement fully synchronous SRAM memory multiple modes operation. M144K blocks support asynchronous memory (unregistered inputs). MLABs support asynchronous (flow-through) read operations. Depending which TriMatrix memory block target, following modes used:
Single-port Simple dual-port True dual-port Shift-register FIFO
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Memory Modes
When using memory blocks ROM, single-port, simple dual-port, true dual-port mode, corrupt memory contents violate setup hold-time memory block input registers. This applies both read write operations.
Single Port
TriMatrix memory blocks support single-port mode. Single-port mode allows either one-read one-write operation time. Simultaneous reads writes supported single-port mode. Figure shows single-port configuration. Figure 4-7. Single-Port Memory Note
data[ address[ wren byteena[] addressstall inclock clockena rden aclr
outclock
Note Figure 4-7:
implement single-port memory blocks single M144K block. "Packed Mode Support" page more details.
During write operation, behavior outputs configurable. read-enable signal perform write operation with read enable deactivated, outputs retain values they held during most recent active read enable. activate read enable during write operation, using read-enable signal all, outputs either show data being written, data that address, don't care value. choose desired behavior, read-during-write behavior either data, data, don't care MegaWizard® Quartus software. "Read During Write" page 4-21 more details this behavior.
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Table shows possible port width configurations TriMatrix memory blocks single-port mode.
Table 4-4. Stratix Port Width Configurations MLABs, Blocks, M144K Blocks (Single-Port Mode) MLABs
Port Width Configurations
Blocks
M144K Blocks
Figure shows timing waveforms read write operations single-port mode with unregistered outputs. Registering RAM's outputs would simply delay output clock cycle. Figure 4-8. Timing Waveform Read-Write Operations (Single-Port Mode)
clk_a
wrena rdena address_a
data_a
(asynch)
a0(old data)
a1(old data)
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Memory Modes
Simple Dual-Port Mode
TriMatrix memory blocks support simple dual-port mode. Simple dual-port mode allows perform one-read one-write operation different locations same time. Figure shows simple dual-port configuration. Figure 4-9. Stratix Simple Dual-Port Memory Note
data[ wraddress[ wren byteena[] wr_addressstall wrclock wrclocken aclr rdaddress[ rden rd_addressstall rdclock rdclocken ecc_status
Note Figure 4-9:
Simple dual-port supports input/output clock mode addition read/write clock mode shown.
Simple dual-port mode supports different read write data widths (mixed width support). Table shows mixed width configurations blocks simple dual-port mode. MLABs have native support mixed width operation. Quartus software implement mixed width memories MLABs using more than MLAB.
Table 4-5. Stratix Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port Read Port
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Table shows mixed width configurations M144K blocks simple dual-port mode.
Table 4-6. Stratix M144K Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port Read Port
simple dual-port mode, M144K blocks support separate write-enable read-enable signals. save power keeping read-enable signal (inactive) when reading. Read-during-write operations same address either output don't care value data. choose desired behavior, read-during-write behavior either don't care data MegaWizard Quartus software. "Read During Write" page 4-21 more details this behavior. MLABs only support write-enable signal. Read-during-write behavior MLABs either don't care, data, data. available choices depend configuration MLAB. Figure 4-10 shows timing waveforms read write operations simple dual-port mode with unregistered outputs. Registering RAM's outputs would simply delay output clock cycle.
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Memory Modes
Figure 4-10. Stratix Simple Dual-Port Timing Waveforms
wrclock wren wraddress data rdclock rden rdaddress (asynch) doutn-1 doutn dout0 an-1 din-1 din4 din5 din6
Figure 4-11 shows timing waveforms read write operations mixed-port mode with unregistered outputs. Figure 4-11. Stratix Mixed-Port Read-During-Write Timing Waveforms
wrclock wren wraddress data rdclock rden rdaddress (asynch) doutn-1 doutn dout0 an-1 din-1 din4 din5 din6
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True Dual-Port Mode
Stratix M144K blocks support true dual-port mode. Sometimes called bi-directional dual-port, this mode allows perform combination port operations: reads, writes, read write different clock frequencies. Figure 4-12 shows true dual-port configuration. Figure 4-12. Stratix True Dual-Port Memory Note
data_a[ address_a[ wren_a byteena_a[] addressstall_a clock_a rden_a aclr_a q_a[]
data_b[ address_b[] wren_b byteena_b[] addressstall_b clock_b rden_b aclr_b q_b[]
Note Figure 4-12:
True dual-port memory supports input/output clock mode addition independent clock mode shown.
widest configuration M144K blocks true dual-port mode follows:
16-bit with parity) (M9K) 32-bit with parity) (M144K)
Wider configurations unavailable because number output drivers equivalent maximum width respective memory block. Because true dual-port outputs ports, maximum width equals half total number output drivers. Table lists possible block mixed-port width configurations true dual-port mode.
Table 4-7. Stratix Block Mixed-Width Configuration (True Dual-Port Mode) (Part Write Port Read Port
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Memory Modes
Table 4-7. Stratix Block Mixed-Width Configuration (True Dual-Port Mode) (Part Write Port Read Port
Table lists possible M144K block mixed-port width configurations true dual-port mode.
Table 4-8. Stratix M144K Block Mixed-Width Configurations (True Dual-Port Mode) Write Port Read Port
true dual-port mode, M144K blocks support separate write-enable read-enable signals. save power keeping read-enable signal (inactive) when reading. Read-during-write operations same address either output data that location data. choose desired behavior, read-during-write behavior either data data MegaWizard Quartus software. "Read During Write" page 4-21 more details this behavior. true dual-port mode access memory location time from either port. When accessing same memory location from both ports, must avoid possible write conflicts. write conflict happens when attempt write same address location from both ports same time. This results unknown data being stored that address location. conflict resolution circuitry built into Stratix TriMatrix memory blocks. must handle address conflicts external block.
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Figure 4-13 shows true dual-port timing waveforms write operation port read operation port with Read-DuringWrite behavior data. Registering RAM's outputs would simply delay outputs clock cycle. Figure 4-13. Stratix True Dual-Port Timing Waveform
clk_a wren_a address_a data_a (asynch) clk_b wren_b address_b (asynch) doutn-1 doutn dout0 dout1 dout2 an-1 din-1 din-1 dout0 dout1 dout2 din4 dout3 din5 din4 din6 din5
Shift-Register Mode
Stratix memory blocks support shift register mode. Embedded memory block configurations implement shift registers digital signal processing (DSP) applications, such finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, auto- cross-correlation functions. These other applications require local data storage, traditionally implemented with standard flip-flops that quickly exhaust many logic cells large shift registers. more efficient alternative embedded memory shift-register block, which saves logic cell routing resources. size shift register determined input data width (w), length taps (m), number taps (n). cascade memory blocks implement larger shift registers.
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Memory Modes
Figure 4-14 shows TriMatrix memory block shift-register mode. Figure 4-14. Stratix Shift-Register Memory Configuration
Shift Register m-Bit Shift Register
m-Bit Shift Register
Number Taps
m-Bit Shift Register
m-Bit Shift Register
Mode
Stratix TriMatrix memory blocks support mode. memory initialization file (.mif) initializes contents these blocks. address lines registered M144K blocks, unregistered MLABs. outputs registered unregistered. Output registers asynchronously cleared. read operation identical read operation single-port configuration.
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FIFO Mode
TriMatrix memory blocks support FIFO mode. MLABs ideal designs with many small, shallow FIFO buffers. implement FIFO buffers your design, Quartus software FIFO MegaWizard. Both single dual-clock (asynchronous) FIFOs supported.
Refer Single- Dual-Clock FIFO Megafunctions User Guide more information implementing FIFO buffers. Stratix TriMatrix memory blocks support following clocking modes:
Clocking Modes
Independent Input/output Read/write Single clock Violating setup hold time memory block address registers could corrupt memory contents. This applies both read write operations.
Table shows clocking mode versus memory mode support matrix.
Table 4-9. Stratix TriMatrix Memory Clock Modes Clocking Mode
Independent Input/output Read/write Single clock
True Dual-Port Mode
Simple Dual-Port Mode
Single-Port Mode
Mode
FIFO Mode
Independent Clock Mode
Stratix TriMatrix memory blocks implement independent clock mode true dual-port memories. this mode, separate clock available each port Clock controls registers port side, while clock controls registers port side. Each port also supports independent clock enables port port registers. Asynchronous clears supported only output latches output registers both ports.
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Design Considerations
Input/Output Clock Mode
Stratix TriMatrix memory blocks implement input/output clock mode true simple dual-port memories. this mode, input clock controls registers related data input memory block including data, address, byte enables, read enables, write enables. output clock controls data output registers. Asynchronous clears available output latches output registers only.
Read/Write Clock Mode
Stratix TriMatrix memory blocks implement read/write clock mode simple dual-port memories. this mode, write clock controls data-input, write-address, write-enable registers. Similarly, read clock controls data-output, read-address, read-enable registers. memory blocks support independent clock enables both read write clocks. Asynchronous clears available data output latches registers only.
Single Clock Mode
Stratix TriMatrix memory blocks implement single-clock mode true dual-port, simple dual-port, single-port memories. this mode, single clock, together with clock enable, used control registers memory block. Asynchronous clears available output latches output registers only.
Design Considerations
This section describes guidelines designing with TriMatrix memory blocks.
Selecting TriMatrix Memory Blocks
Quartus software automatically partitions user-defined memory into embedded memory blocks taking into account both speed size constraints placed your design. example, Quartus software spread memory across multiple memory blocks when resources available order increase performance design. manually assign memory specific block size MegaWizard. MLABs implement single-port SRAM through emulation Quartus software. Emulation results minimal additional logic resources being used. Because dual-purpose architecture MLAB, only data input registers output registers block. MLABs gain input address registers additional optional data output registers from adjacent ALMs using register packing.
4-20 Stratix Device Handbook, Volume<b
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