SIII51016-1.1 total power FPGA includes static power dynamic powe

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

SIII51016-1.1 total power FPGA includes static power dynamic powe

Datasheet Thumbnail

Top Searches for this datasheet

Programmable Power Temperature Sensing Diode Stratix Devices
SIII51016-1.1
total power FPGA includes static power dynamic power. Static power power consumed FPGA when programmed clocks operating, while dynamic power comprised switching power when device configured running. dynamic power calculated with following equation: Equation 16-1. Dynamic Power Equation frequency toggle rate
From equation, frequency toggle rate design-dependent. However, voltage varied lower dynamic power consumption square value voltage difference. Stratix® devices minimize static dynamic power with advanced process optimizations, selectable core voltage, revolutionary programmable power technology. These technologies enable Stratix designs optimally meet design-specific performance requirements with lowest possible power. Quartus® software optimizes designs with Stratix power technology ensure performance lowest power consumption. This automatic process allows designers concentrate functionality their design, instead power consumption design. Power consumption also affects thermal management. Stratix offers temperature sensing diode (TSD) with embedded analog-to-digital converter (ADC) circuitry which eliminates need external temperature sensing chip board. Stratix self-monitor device junction temperature used with external circuitry activities such controlling flow FPGA.
Altera Corporation 2007
16-1
Stratix Power Technology
Stratix Power Technology
following section provides details about Stratix selectable core voltage programmable power technology.
Selectable Core Voltage
Altera offers series low-voltage Stratix products that have ability power core logic device with either 0.9-V 1.1-V power supply. This power supply, called VCCL, powers LAB, MLAB, blocks, TriMatrix memory blocks, clock networks, routing lines. periphery, consisting registers their routing connections powered with 1.1-V power supply. same 1.1-V power supply want both VCCL Lowering core voltage reduces both static dynamic power, causes reduction performance. need correct core supply voltage Quartus settings under Operating Conditions, since Quartus analyzes core power consumption timing delays based this selection. When compile design, select either 0.9-V 1.1-V core voltage. compare power performance trade-offs 0.9-V core voltage compilation result 1.1-V core voltage compilation result then choose desirable core voltage your design. Quartus defaults core voltage Ensure that board separate 0.9-V power supply utilize lower voltage option, ensure that connect VCCL voltage level that Quartus Stratix device cannot distinguish which core voltage level used board. Connecting wrong voltage level will give different timing delays power consumption than what reported Quartus software.
Refer 437: Power Optimization Techniques information about selectable core voltage performance power effects sample designs.
16-2 Stratix Device Handbook, Volume
Altera Corporation 2007
Programmable Power Temperature Sensing Diode Stratix Devices
Programmable Power Technology
addition ability change core voltage, Stratix also offers ability configure portions core, called tiles, high-speed low-power mode operation performed Quartus without user intervention. This programmable power technology, used reduce static power, utilizes on-chip voltage regulator, powered VCCPT. design compilation, Quartus determines whether tile needs high-speed low-power mode based timing constraints design.
Refer 437: Power Optimization Techniques more information about Quartus uses programmable power technology when compiling design. Stratix tile consist following:
MLAB/LAB pairs with routing pair MLAB/LAB pairs with routing pair adjacent DSP/memory block routing TriMatrix memory blocks blocks interfaces
blocks routing associated with tile share same setting either high speed power. Tiles that include blocks, memory blocks, interfaces high-speed mode default optimum performance when used design. Unused blocks, memory blocks, elements low-power mode minimize static power. Clock networks support programmable power technology. With programmable power technology, faster speed grade FPGAs require less power, there will fewer high-speed MLAB pairs, compared slower speed grade FPGAs. slower speed grade device need more high-speed MLAB pairs meet performance requirements, while faster speed grade device meet performance requirements with MLAB pairs low-power mode.
Altera Corporation 2007
16-3 Stratix Device Handbook, Volume
Stratix Power Technology
Quartus unused, unshared inputs unused device resources design low-power mode reduce static dynamic power. Quartus following resources power when they used design:
LABs MLABs TriMatrix memory blocks External memory interface circuitry blocks SERDES blocks
instantiated design, asserting reset high keeps power.
Relationship Between Selectable Core Voltage Programmable Power Technology
Table 16-1 shows Stratix programmable power capabilities. Speed grade considerations permutations give flexibility designing your system.
Table 16-1. Stratix Programmable Power Capabilities Selectable Core Voltage
Routing Memory Blocks Blocks Global Clock Networks Elements Note Table 16-1:
Tiles with blocks, memory blocks, elements that used design always high-speed mode. Unused blocks, memory blocks, interfaces low-power mode default.
Programmable Power Technology
Fixed setting Fixed setting Fixed setting
16-4 Stratix Device Handbook, Volume
Altera Corporation 2007
Programmable Power Temperature Sensing Diode Stratix Devices
Stratix External Power Supply Requirements
This section describes different external power supplies needed power Stratix devices. Table 16-2 lists external power supply pins Stratix devices. Some power supply pins supplied with same external power supply, provided they need same voltage level, noted recommended board connection column. possible values each power supply, refer Switching Characteristics Stratix Devices chapter Stratix Device Handbook.
Table 16-2. Stratix Power Supply Requirements Power Supply
VCCL VCCD_PLL VCCA_PLL VCCPT VCCPGM VCCPD VCCIO VCC_CLKIN VCCBAT VREF
Recommended Board Connection
VCCL VCCD_PLL VCCA_PLL VCCPGM VCCPD VCCIO VCCBAT VREF
registers power supply digital power supply analog power supply
Description
Selectable core voltage power supply
Power supply programmable power technology Configuration pins power supply pre-driver power supply power supply Differential clock input pins power supply (top bottom banks only) Battery back-up power supply design security volatile register Power supply voltage-referenced standards Ground
Notes Table 16-2:
Designers minimize number external power supplies shorting pins left column supplying both pins with power supply voltage levels needed same). VCCPD voltage must equal greater than VCCIO. There VREF bank. external power supply resistor divider network supply this voltage.
Altera Corporation 2007
16-5 Stratix Device Handbook, Volume
Temperature Sensing Diode
Figure 16-1 shows example power management Stratix devices. Figure 16-1. Stratix Power Management Example
Voltage Regulator (Termination)
Voltage Regulator (Core) Variable (0.9
VCCL Termination Resistor
Voltage Regulator (VCC) Elements Fixed (1.1
Stratix
User
Voltage Regulator (VCCIO) (1.2 V/1.8 V/3.0
VCCIO VCCPD VCCPT VCCPGM VREF
Voltage Regulator (VCCPD) VCCIO) Voltage Reference Voltage Regulator (VCCPT) Fixed (2.5
Voltage Regulator (VCCPGM) Fixed (1.8 V/2.5 V/3.0
Temperature Sensing Diode
Knowing junction temperature crucial thermal management. Historically, junction temperature calculated using ambient case temperature, junction-to-ambient junction-to-case (jc) thermal resistance, device power consumption. Stratix device monitor temperature with embedded temperature sensing diode (TSD) with accuracy, control flow device. Stratix uses characteristics junction diode determine temperature. Stratix also built-in circuitry, without external temperature sensor. bypassed designers want external temperature sensor, similar Stratix solution.
16-6 Stratix Device Handbook, Volume
Altera Corporation 2007
Programmable Power Temperature Sensing Diode Stratix Devices
following section describes Stratix detail.
External Connections
Stratix TSD, located right corner die, requires pins voltage reference. When both used, connect TEMPDIODEP external resistor connect TEMPDIODEN ground, shown Figure 16-2. Figure 16-2. Connections When Both Used
TEMPDIODEP TEMPDIODEN Stratix
circuit bypassed when sensing diode connected external temperature sensor. This scheme, shown Figure 16-3, very similar Stratix connection. Figure 16-3. Connections When Bypassed
Temperature-Sensing Device
TEMPDIODEP Disabled TEMPDIODEN
Stratix
Altera Corporation 2007
16-7 Stratix Device Handbook, Volume
Temperature Sensing Diode
Architecture Description
Figure 16-4 shows block diagram Stratix circuitry, including block, accessible WYSIWYG Quartus software. ports shown Table 16-3. When used, Stratix different modes operations: power-up mode user mode. When include your design, circuit automatically calibrates itself upon powerup reads initial temperature die. user mode, request convert temperature sensed diode asserting clken signal. When used, circuitry disabled reduce static power. Figure 16-4. Stratix Temperature Sensing Diode Block Diagram
External Resistor
User Clock Internal Oscillator Clock
Clock Divider
1-MHz Clock CLKEN
TSDCALDONE TSDCAL0[7.0]
Notes Figure 16-4:
user clock must provided user mode. This signal only accepts either 1-MHz 40-MHz input clock. internal oscillator clock only available power-up mode calibrate circuitry. clock divider block bypassed when input (set user).
Table 16-3. Temperature Sensing Diode Ports Port Name
CLKEN TSDCALDONE TSDCALO Input Input Input Output Output
Input/Output
Description
Clock Clock enable request signal Reset Done signal temperature reading Eight-bit digital output showing temperature read
16-8 Stratix Device Handbook, Volume
Altera Corporation 2007
Programmable Power Temperature Sensing Diode Stratix Devices
circuit consists sensing diode block. block accept either 1-MHz 40-MHz clock that will divided down create 1-MHz clock. power-up mode, clock comes from internal oscillator. user mode, need provide user clock. clken signal must asserted request temperature sensing operation. circuit then outputs 8-bit digital reading (TSDCALO[7.0]) that maps specific temperature. TSDCALDONE signal asserted indicate that TSDCALO outputs ready read. Signals TSDCALO[7.0] shows temperature read complement. Table 16-4 lists examples conversion from complement actual temperatures.
Table 16-4. Temperature Output Mapping Examples Complement 8-bit TSDCALO [7:0]
00000000 00011001 01010101 01111101
Temperature
25°C 85°C 125°C
Conclusion
process geometries smaller, power thermal management becoming more crucial FPGA designs. Stratix offers programmable power technology selectable core voltage options power operation. These features, along with speed grade choices, used different permutations give best power performance combination. Taking advantage silicon, Quartus software able manipulate designs best combination achieve lowest power required performance. thermal management, Stratix temperature sensing diode uses embedded analog-to-digital converter, enabling designers easily incorporate this feature their designs. Being able monitor junction temperature device time also allows designers control flow device save power whole system.
Altera Corporation 2007
16-9 Stratix Device Handbook, Volume
Document Revision History
Document Revision History
Table 16-5 shows revision history this document.
Table 16-5. Document Revision History Date Document Version
2007 v1.1 November 2006 Initial Release v1.0
Changes Made
Replaced instances VCCR with VCCPT
Summary Changes
Minor update.
16-10 Stratix Device Handbook, Volume
Altera Corporation 2007

SIII51016-1.1 total power FPGA includes static power dynamic powe

Top Searches for this datasheet

Other recent searches