SIII51008-1.1 Stratix® structure been completely redesigned from

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External Memory Interfaces Stratix Devices
SIII51008-1.1
Stratix® structure been completely redesigned from ground provide flexible high-performance support existing emerging external memory standards. These include high-performance double data rate (DDR) memory standards such DDR3, DDR2, SDRAM; QDRII+, QDRII SRAM; RLDRAM frequencies MHz. Packed with features such dynamic on-chip termination (OCT), trace mismatch compensation, read/write leveling, half data rate (HDR) blocks, 36-bit programmable group widths, Stratix elements provide easy-to-use built-in functionality required rapid robust implementation. Double data rate external memory support found sides Stratix FPGA. Stratix devices provide efficient architecture quickly easily wide external memory interfaces with small modular bank structure. self-calibrating megafunction (ALTMEMPHY) optimized take advantage Stratix structure, along with Quartus® timing analysis tool, TimeQuest, completes picture provide total solution highest reliable frequency operation across process, voltage, temperature (PVT) variations.
Altera Corporation 2007
Table summarizes maximum clock rate Stratix devices support with external memory devices.
Table 8-1. Stratix Maximum Clock Rate Support External Memory Interfaces Note Speed Grade (MHz) Memory Standards Top/ Bottom Banks
Speed Grade (MHz) Top/ Bottom Banks
Speed Grade (MHz) Top/ Bottom Banks
Speed Grade (MHz) Top/ Bottom Banks
Left/ Right Banks
Left/ Right Banks
Left/ Right Banks
Left/ Right Banks
DDR3 SDRAM DDR2 SDRAM SDRAM QDRII+ SRAM QDRII SRAM RLDRAM Notes Table 8-1:
Numbers based half-rate controller preliminary until characterization final. Performance based 0.9-V core voltage. 1.1-V core voltage, speed grade devices have same performance speed grade devices. Left/right banks have lower maximum performance than top/bottom banks left/right I/Os having higher capacitance support LVDS standard. This applies interfaces with both modules components. Memory interfaces above require deskew circuitry pending characterization. Support will evaluated after characterization. This applies QDRII SRAM RLDRAM devices running 1.5-V 1.8-V voltages.
Figure shows general block diagram Stratix external memory support, showing phase-locked loop (PLL), delay-locked loop (DLL), banks. number available banks depend device density.
Stratix Device Handbook, Volume
Altera Corporation 2007
External Memory Interfaces Stratix Devices
Figure 8-1. Stratix External Memory Support
DLL1 PLL_L1 PLL_T1 PLL_T2 PLL_R1 DLL4
PLL_L2 Stratix Device PLL_L3
PLL_R2
PLL_R3
PLL_L4 DLL2 PLL_B1 PLL_B2
PLL_R4 DLL3
Altera Corporation 2007
Stratix Device Handbook, Volume
Figure shows overview memory interface data path. Figure 8-2. External Memory Interface Data Path Overview Note (1),
Stratix FPGA Memory
Logic Block
(Read)
FIFO Half Data Rate Input Registers
Alignment Synchronization Registers
Input Registers
(Read)
Resynchronization Clock
Half-Rate Resynchronization Clock
Half Data Rate Output Registers Alignment Registers
Output Registers
(Write)
Write Clock
Half Data Rate Output Registers Alignment Registers
Output Registers
(Write)
Clock Management Reset
Half-Rate Clock Alignment Clock Write Clock
Note Figure 8-2:
Each register block bypassed. blocks each memory interface differ slightly.
This chapter describes hardware features Stratix devices that facilitate high-speed memory interfacing each memory standard. Stratix devices feature DLLs, PLLs, dynamic OCT, read/write leveling, deskew ciruitry.
Stratix Device Handbook, Volume
Altera Corporation 2007
External Memory Interfaces Stratix Devices
Memory Interfaces Support
typical memory interface requires data DQ), data strobe (DQS DQSn/CQn), address, command, clock pins. Some memory interfaces data mask (DM) pins enable write masking QVLD pins indicate that read data ready captured. This section describes Stratix devices support these different pins.
Data Data Clock/Strobe Pins
Stratix memory interface data pins called pins. read data-strobes clocks called pins. Depending memory specifications, pins bidirectional single-ended signals DDR2 SDRAM), unidirectional differential signals RLDRAM II), bidirectional differential signals (DDR3 DDR2 SDRAM), unidirectional complementary signals (QDRII+ QDRII SRAM). Connect unidirectional read data-strobes clocks Stratix pins available pins same bank device side read data pins) unidirectional write data-strobes clocks since trace lengths from pins registers optimized these pins. Stratix devices offer differential input buffers differential read data-strobe/clock operations provide independent logic block each complementary read data-strobe/clock operations. Stratix tables, differential pin-pairs denoted DQSn pins, while complementary signals denoted pins. DQSn pins marked separately table. Each connects logic block shifted signals active-low input registers registers. DDR2 SDRAM, optional differential DQS/DQSn feature Stratix devices better signal integrity. also single-ended option reduce utilization.
pins bidirectional signals, DDR3, DDR2, SDRAM, RLDRAM common (CIO) interfaces, unidirectional signals, QDRII+, QDRII SRAM, RLDRAM separate (SIO) devices. Connect unidirectional read data signals Stratix pins unidirectional write data signals different group pins. Using DQS/DQ group write data signals minimizes output skew, allows access write leveling circuitry, allows vertical migration. These pins also have access deskewing circuitry that compensate delay mismatch between signals bus.
Altera Corporation 2007
Stratix Device Handbook, Volume
Memory Interfaces Support
Table summarizes connections between Stratix device external memory device.
Table 8-2. Stratix Memory Interfaces Utilization Description
Read Data Write Data Parity, BWSn, ECC, QVLD Read Clocks/Strobes Differential DQS/DQSn DDR3/DDR2 SDRAM RLDRAM Single-ended DDR2/DDR SDRAM Complementary DQS/CQn QDRII+/QDRII SRAM Write Clocks/Strobes Memory Clocks unused pins QDRII+/QDRII SRAM RLDRAM unused pins DDR3 SDRAM (for write leveling access) Adjacent user I/Os other memory interfaces Notes Table 8-2:
write data unidirectional, connect write data separate group other than read group. DDR2 SDRAM support either single-ended differential signaling.
Stratix Utilization
pins phase-shift circuitry (described "Stratix External Memory Interface Features" page 8-22) compensate variations. locations fixed table. memory interface circuitry available every Stratix bank. memory interface pins support standards required support DDR3, DDR2, SDRAM; QDRII+ QDRII SRAM; RLDRAM devices. output signals generated using DDIO registers. clock generating signals phase offset compared clock generating signals. Every bank Stratix device support signals with modes although devices support (see Table 8-4). mode, each DQSn pin-pair drives four pins within that group. There support this mode. mode, each DQSn/CQn pin-pair drives pins, support parity eight data bits, optional QVLD pin. parity bit, bit, QVLD pin, data used, these pins used regular user pins.
Stratix Device Handbook, Volume
Altera Corporation 2007
External Memory Interfaces Stratix Devices
Similarly, with modes, each DQSn/CQn pin-pair drives pins, respectively, with optional QVLD each group. There parity bits (counted number pins) mode four parity bits mode. Table lists maximum number pins DQS/DQ mode, including DQSn/CQn pin-pair.
Table 8-3. Stratix DQS/DQ Mode Pins Mode
Notes Table 8-3:
groups stitched make group. from original group becomes user pin. Four groups stitched make group. Three pins from original group become user pins. Eight groups stitched make group. Nine pins from original group become user pins.
DQSn Support
Support
Maximum Number Pins Group
Data
Parity (Optional)
QVLD (Optional)
Table shows maximum number DQS/DQ groups side Stratix device. more detailed listing number DQS/DQ groups available bank each Stratix device, Figures through Figure 8-8.
Table 8-4. Number DQS/DQ Groups Stratix Devices Side (Part Note (1), Device
EP3SE50/ EP3SL50/ EP3SL70
Package
Side
484-pin FineLine Left BGA® Bottom Right 780-pin FineLine Left Bottom Right
Altera Corporation 2007
Stratix Device Handbook, Volume
Memory Interfaces Support
Table 8-4. Number DQS/DQ Groups Stratix Devices Side (Part Note (1), Device Package Side
780-pin FineLine Left EP3SE80/ EP3SE110/ Bottom EP3SL110/ Right EP3SL150 1152-pin FineLine Left Bottom Right EP3SL200 780-pin FineLine Left Bottom Right 1152-pin FineLine Left Bottom Right 1517-pin FineLine Left Bottom Right EP3SE260 780-pin FineLine Left Bottom Right 1152-pin FineLine Left Bottom Right 1517-pin FineLine Left Bottom Right
Stratix Device Handbook, Volume
Altera Corporation 2007
External Memory Interfaces Stratix Devices
Table 8-4. Number DQS/DQ Groups Stratix Devices Side (Part Note (1), Device
EP3SL340
Package
1152-pin FineLine Left
Side
Bottom Right
1517-pin FineLine
Left Bottom Right
1760-pin FineLine
Left Bottom Right
Note Table 8-4:
Numbers preliminary. Some DQS/DQ pins also used RUP/RDN configuration pins. Make sure that DQS/DQ groups that have chosen also used configuration calibration.
Altera Corporation 2007
Stratix Device Handbook, Volume
Memory Interfaces Support
Figure 8-3. Number DQS/DQ Groups Bank EP3SE50, EP3SL50, EP3SL70 Devices 484-pin FineLine Package Notes (1),
Bank User I/Os x4=2 x8/x9=1 x16/x18=0 Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1x16/x18=0 EP3SE50, EP3SL50, EP3SL70 Devices 484-pin FineLine Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=2 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Notes Figure 8-3:
Numbers preliminary. This device does support mode. Some groups RUP/RDN pins pins. cannot these groups using these pins calibration. Some DQS/DQ pins this bank also used configuration pins. Choose DQS/DQ pins that going used your configuration scheme. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, CLK10n)
8-10 Stratix Device Handbook, Volume
Altera Corporation 2007
External Memory Interfaces Stratix Devices
Figure 8-4. Number DQS/DQ Groups Bank EP3SE50, EP3SL50, EP3SL70, EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200, EP3SE260 Devices 780-pin FineLine Package Notes (1),
Bank User I/Os x4=6 x8/x9=3 x16/x18=1 Bank User I/Os x4=2 x8/x9=1 x16/x18=0 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1
Bank User I/Os x4=4 x8/x9=2 x16/x18=1
Bank User I/Os x4=4 x8/x9=2 x16/x18=1
Bank User I/Os x4=3 x8/x9=1 x16/x18=0 EP3SE50, EP3SL50, EP3SL70, EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200, EP3SE260 Devices 780-pin FineLine
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=4 x8/x9=2 x16/x18=1
Bank User I/Os x4=4 x8/x9=2 x16/x18=1
Bank User I/Os x4=6 x8/x9=3 x16/x18=1
Bank User I/Os x4=2 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=6 x8/x9=3 x16/x18=1
Notes Figure 8-4:
Numbers preliminary until devices available. This device does support mode. Some groups RUP/RDN pins pins. cannot these groups using these pins calibration. Only EP3SE260 calibration blocks banks Some DQS/DQ pins this bank also used configuration pins. Choose DQS/DQ pins that going used your configuration scheme. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, CLK10n)
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8-11 Stratix Device Handbook, Volume
Memory Interfaces Support
Figure 8-5. Number DQS/DQ Groups EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200, EP3SE260, EP3SL340 Devices 1152-pin FineLine Package Notes (1),
Bank DLL1 User I/Os x4=6 x8/x9=3 x16/x18=1 Bank User I/Os x4=4 x8/x9=2 x16/x18=1 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 Bank User I/Os x4=4 x8/x9=2 x16/x18=1 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 DLL4
Bank User I/Os x4=7 x8/x9=3 x16/x18=1
Bank User I/Os x4=7 x8/x9=3 x16/x18=1
Bank User I/Os x4=6 x8/x9=3 x16/x18=1 EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200, EP3SE260, EP3SL340 Devices 1152-pin FineLine
Bank User I/Os x4=6 x8/x9=3 x16/x18=1
Bank User I/Os x4=6 x8/x9=3 x16/x18=1
Bank User I/Os x4=6 x8/x9=3 x16/x18=1
Bank User I/Os x4=7 x8/x9=3 x16/x18=1
Bank User I/Os x4=7 x8/x9=3 x16/x18=1
Bank DLL2 User I/Os x4=6 x8/x9=3 x16/x18=1
Bank User I/Os x4=4 x8/x9=2 x16/x18=1
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=3 x8/x9=1 x16/x18=0
Bank User I/Os x4=4 x8/x9=2 x16/x18=1
Bank User I/Os x4=6 x8/x9=3 x16/x18=1 DLL3
Notes Figure 8-5:
Numbers preliminary until devices available. This device does support mode. Some groups RUP/RDN pins pins. cannot these groups using these pins calibration. Only EP3SE260 EP3SL340 calibration blocks banks Some DQS/DQ pins this bank also used configuration pins. Choose DQS/DQ pins that going used your configuration scheme. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, CLK10n)
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External Memory Interfaces Stratix Devices
Figure 8-6. Number DQS/DQ Groups Bank EP3SL200 Devices 1517-pin FineLine Package Note
Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 Bank User I/Os x4=3 x8/x9=1 x16//x18=0 x32/x36=0 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1
DLL1
DLL4
Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1
Bank User I/Os x4=7 x8/x9=3 x6/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0
EP3SL200 Devices 1517-pin FineLine
DLL2
DLL3
Notes Figure 8-6:
Numbers preliminary. Some groups RUP/RDN pins pins. cannot these groups using these pins calibration. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, CLK10n) eight dedicated corner clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, PLL_R1_CLKn) that used data inputs. Some DQS/DQ pins this bank also used configuration pins. Choose DQS/DQ pins that going used your configuration scheme.
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8-13 Stratix Device Handbook, Volume
Memory Interfaces Support
Figure 8-7. Number DQS/DQ Groups Bank EP3SE260 EP3SL340 Devices 1517-pin FineLine Package Note
Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1
DLL1
DLL4
Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank DLL2 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 Bank User I/Os x4=3 x8/x9=1 x16/x18=0 x32/x36=0 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1
Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0
EP3SE260 EP3SL340 Devices 1517-Pin FineLine
DLL3
Notes Figure 8-7:
Numbers preliminary. Some groups RUP/RDN pins pins. cannot these groups using these pins calibration. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, CLK10n) eight dedicated corner clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, PLL_R1_CLKn) that used data inputs. Some DQS/DQ pins this bank also used configuration pins. Choose DQS/DQ pins that going used your configuration scheme.
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External Memory Interfaces Stratix Devices
Figure 8-8. DQS/DQ Mode Support Bank EP3SL340 Devices 1760-pin FineLine Package Note
Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 DLL4
DLL1
Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank DLL2 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x81x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Bank User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1
Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 Bank User I/Os x4=7 x8/x9=3 x16/x18=1 x32/x36=0
EP3SL340 Devices 1760-pin FineLine
DLL3
Notes Figure 8-8:
Numbers preliminary. Some groups RUP/RDN pins pins. cannot these groups using these pins calibration. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, CLK10n) eight dedicated corner clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, PLL_R1_CLKn) that used data inputs. Some DQS/DQ pins this bank also used configuration pins. Choose DQS/DQ pins that going used your configuration scheme.
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Memory Interfaces Support
DQSn pins listed Stratix tables DQSXY DQSnXY, respectively, where denotes DQS/DQ grouping number, denotes whether group located (T), bottom (B), left (L), right side device. corresponding pins marked DQXY, where indicates which group pins belong indicates whether group located (T), bottom (B), left (L), right side device. example, DQS1L indicates pin, located left side device. Figure illustrations. pins belonging that group will shown DQ1L table. numbering scheme starts from left side device going counter-clockwise. Figure shows DQS/DQ groups numbered device. bottom sides device contain DQS/DQ groups, left right sides device contain DQS/DQ groups. parity, BWSn, ECC, QVLD pins shown pins table. When used memory interface pins, these pins available regular pins.
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External Memory Interfaces Stratix Devices
Figure 8-9. Pins Stratix Banks
DQS44T DQS23T DQS22T DQS1T
DLL1 PLL_T1 PLL_L1 DQS1L PLL_T2
DLL4 PLL_R1
DQS40R
DQS20L
DQS21R
PLL_L2 Stratix Device PLL_L3
PLL_R2
PLL_R3
DQS21L
DQS20R
DQS40L PLL_L4 PLL_B1 DLL2 DQS1B DQS22B DQS23B PLL_B2
DQS1R
PLL_R4 DLL3 DQS44B
numbering based mode. mode, there eight DQS/DQ groups bank. Each mode DQS/DQ group consists pin, DQSn pin, four pins. mode, bank combines adjacent DQS/DQ groups; pair DQSn/CQn pins drive parity pins combined group that consists pins (including parity
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8-17 Stratix Device Handbook, Volume
Memory Interfaces Support
QVLD pins) pair DQSn/CQn pins. Similarly, mode, bank combines four adjacent DQS/DQ groups create group with maximum pins (including parity QVLD pins) pair DQSn/CQn pins. mode, bank combines eight adjacent groups together create group with maximum pins (including parity QVLD pins) pair DQSn/CQn pins. Stratix modular banks allow easy formation DQS/DQ groups. pins banks user pins used programming, RUP/RDN used calibration, clock output pins, divide number pins bank maximum possible number groups. then divide that number maximum possible number respectively (see Table 8-5). However, some pins bank used other functions.
Table 8-5. DQ/QS Group Stratix Modular Banks Maximum Maximum Possible Possible Number Number Groups Groups
Modular Bank Size
Maximum Possible Number Groups
Maximum Possible Number Groups
pins pins pins pins Note Table 8-5:
Some groups RUP/RDN pins. cannot these groups Stratix calibrated feature.
Optional Parity, BWSn, QVLD Pins
pins from same DQS/DQ group data parity pins Stratix devices. Stratix device family supports parity modes. There parity available eight bits data pins. pins same DQS/DQ group data parity they treated, configured, generated like pin. data mask (DM) pins only required when writing DDR3, DDR2, SDRAM, RLDRAM devices. QDRII+ QDRII SRAM devices BWSn signal select which byte write into memory. signal BWSn signals indicates that write
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External Memory Interfaces Stratix Devices
valid. DM/BWSn signal high, memory will mask signals. system does require write data masking, connect memory pins indicate every write data valid. pins same DQS/DQ group write data DM/BWSn signals. Each group signals DDR3, DDR2, SDRAM devices requires pin. There RLDRAM device BWSn byte (eight bits) QDRII+/QDRII SRAM data. Generate BWSn signals using pins configure signals similarly output signals. Stratix devices support signal DDR3 SDRAM DDR2 SDRAM interfaces with differential signaling. Some DDR3, DDR2, SDRAM devices modules support error correction coding (ECC), which method detecting automatically correcting errors data transmission. 72-bit DDR3, DDR2, SDRAM interface, typically eight pins used addition data pins. Connect DDR3, DDR2, SDRAM pins Stratix device DQS/DQ group. These signals also generated like pins. memory controller needs encoding decoding logic data. Designers also extra byte data other error checking methods. QVLD pins used RLDRAM QDRII+ SRAM interfaces indicate read data availability. There QVLD memory device. high QVLD indicates that memory outputting data requested. Similar inputs, this signal edge-aligned with read clock signals (CQ/CQn QDRII+/QDRII SRAM QK/QK# RLDRAM sent half clock cycle before data starts coming memory. QVLD treated supported like pin, connect QVLD available pins read data group. Refer "Data Data Clock/Strobe Pins" page section more information parity, ECC, QVLD pins these pins treated pins.
Address Control/Command Pins
Address control/command signals typically sent single data rate. only exception QDRII SRAM burst-of-two devices, where read address needs captured rising edge clock while write address needs captured falling edge clock memory. There special circuitry required address control/command pins. user pins same bank data pins.
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Memory Interfaces Support
Memory Clock Pins
addition (and CQn) signals capture data, DDR3, DDR2, SDRAM, RLDRAM extra pair clocks, called signals, capture address control/command signals. CK/CK# signals should generated mimic write data-strobe using Stratix registers (DDIOs) ensure that timing relationships between CK/CK# signals (tDQSS DDR3, DDR2, SDRAM tCKDK RLDRAM met. device pins generate CK/CK# signals DDR2 SDRAM. However, Stratix devices require available pins separate group CK/CK# signals DDR3 interfaces access write leveling circuitry. also generate RLDRAM DK/DK# signals using Stratix DDIOs available pins. QDRII+ QDRII SRAM devices same clock (K/K#) capture data, address, control/command signals. Generate these signals using DDIOs same pins ensure both K/K# signals subjected same variations.
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Figure 8-10 shows memory clock generation block diagram Stratix devices. Figure 8-10. Memory Clock Generation Block Diagram
FPGA Elements
System Clock
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Stratix External Memory Interface Features
Stratix devices rich with features that allow robust high-performance external memory interfacing. ALTMEMPHY megafunction allows these external memory interface features helps physical interface (PHY) best suited your system. This section describes each Stratix device feature that used external memory interfaces from phase-shift circuitry, logic block, leveling multiplexers, dynamic control block, registers, features, PLL. When using Altera memory controller MegaCore® functions, instantiated you. ALTMEMPHY megafunction Altera memory controller MegaCore functions half frequency interface memory devices allow better timing management high-speed memory interfaces. Stratix devices have built-in registers convert data from full-rate (the frequency) half-rate (the controller frequency) vice versa. These registers bypassed your memory controller running half rate frequency.
Phase-Shift Circuitry
Stratix phase-shift circuitry provides phase shift pins read transactions, when pins acting input clocks strobes FPGA. phase-shift circuitry consists DLLs that shared between multiple pins phase-offset module further fine-tune phase shift different sides device. Figure 8-11 shows phase-shift circuitry connected pins device.
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Figure 8-11. Pins Phase-Shift Circuitry Note
Reference Clock Reference Clock
Logic Blocks
Phase-Shift Circuitry
Phase-Shift Circuitry
Logic Blocks
Phase-Shift Circuitry
Phase-Shift Circuitry
Reference Clock
Reference Clock
Notes Figure 8-11:
Refer "DLL" page 8-24 section possible reference input clock pins each DLL. Each DQS/CQn determines phase shift with possible output settings.
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phase-shift circuitry connected logic blocks that control each pin. logic blocks allow delay settings updated concurrently every pin.
phase-shift circuitry uses dynamically measure clock period needed DQS/CQn pin. DLL, turn, uses frequency reference dynamically generate control signals delay chains each pins, allowing compensate variations. delay settings Gray-coded reduce jitter when updates settings. phase-shift circuitry needs maximum 1280 clock cycles calculate correct input clock period. Data should sent during these clock cycles since there guarantee will properly captured. settings from stable until this lock period elapsed, should aware that anything using these settings (including leveling delay system) unstable during this period. still phase-shift circuitry memory interfaces that less than MHz. signal will shifted Even signal shifted exactly middle valid window, element should still able capture data frequency applications where large amount timing margin available.
There four DLLs Stratix device, located each corner device. These four DLLs support maximum four unique frequencies, with each running frequency. Each have outputs, which allow Stratix device have eight different phase shift settings. Figure 8-12 shows bank locations Stratix devices.
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Figure 8-12. Stratix Bank Locations
PLL_L1 PLL_R1 PLL_T2
DLL1
PLL_T1
DLL4
PLL_L2 Stratix FPGA PLL_L3
PLL_R2
PLL_R3
PLL_L4 DLL2 PLL_B1 PLL_B2 DLL3
PLL_R4
access adjacent sides from location within device. example, left device access side (I/O banks left side device (I/O banks 2C). This means that each bank accessible DLLs, giving more flexibility create multiple frequencies
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multiple-types interfaces. example, design interface spanning within side device within sides adjacent DLL. outputs same delay settings both sides device adjacent DLL. Interfaces that span across sides device recommended high-performance memory interface applications.
Each bank settings from either both DLLs bank adjacent example, DQS1L phase-shift settings from DLL1, while DQS2L gets phase-shift settings from DLL2. Table lists location supported banks Stratix devices.
Table 8-6. Location Supported Banks
DLL1 DLL2 DLL3 DLL4
Location
left corner Bottom left corner Bottom right corner right corner
Accessible Banks
reference clock each come from output clocks dedicated clock input pins located either side DLL. Tables through show available reference clock input resources Stratix device family.
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When have dedicated only generate input reference clock, mode Compensation, Quartus software will change automatically. Because does other outputs, does need compensate clock paths.
Table 8-7. Reference Clock Input EP3SE50, EP3SL50 EP3SL70 Devices
DLL1
CLKIN (Top/Bottom)
CLK15P, CLK15N, CLK14P, CLK14N CLK5P, CLK5N, CLK4P, CLK4N CLK5P, CLK5N, CLK4P, CLK4N
CLKIN (Left/Right)
CLK0P, CLK0N, CLK1P, CLK1N
(Top/Bottom)
PLL_T1
(Left/Right)
PLL_L2
DLL2 DLL3
CLK0P, CLK0N, CLK1P, CLK1N CLK10P, CLK10N, CLK11P, CLK11N CLK10P, CLK10N, CLK11P, CLK11N
PLL_B1 PLL_B1
PLL_L2 PLL_R2
DLL4
CLK15P, CLK15N, CLK14P, CLK14N
PLL_T1
PLL_R2
Table 8-8. Reference Clock Input EP3SE80, EP3SE110, EP3SL110 EP3SL150 Devices
DLL1
CLKIN (Top/Bottom)
CLK15P, CLK15N, CLK14P, CLK14N CLK5P, CLK5N, CLK4P, CLK4N CLK7P, CLK7N, CLK6P, CLK6N CLK13P, CLK13N, CLK12P, CLK12N
CLKIN (Left/Right)
CLK0P, CLK0N, CLK1P, CLK1N
(Top/Bottom)
PLL_T1
(Left/Right)
PLL_L2
DLL2 DLL3 DLL4
CLK2P, CLK2N, CLK3P, CLK3N CLK8P, CLK8N, CLK9P, CLK9N CLK10P, CLK10N, CLK11P, CLK11N
PLL_B1 PLL_B2 PLL_T2
PLL_L3 PLL_R3 PLL_R2
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Table 8-9. Reference Clock Input EP3SL200, EP3SE260 EP3SL340 Devices
DLL1
CLKIN (Top/Bottom)
CLK15P, CLK15N, CLK14P, CLK14N CLK5P, CLK5N, CLK4P, CLK4N CLK7P, CLK7N, CLK6P, CLK6N CLK13P, CLK13N, CLK12P, CLK12N
CLKIN (Left/Right)
CLK0P, CLK0N, CLK1P, CLK1N CLK2P, CLK2N, CLK3P, CLK3N CLK8P, CLK8N, CLK9P, CLK9N CLK10P, CLK10N, CLK11P, CLK11N
(Top/Bottom) (Left/Right) (Corner)
PLL_T1 PLL_L2 PLL_L1
DLL2
PLL_B1
PLL_L3
PLL_L4
DLL3
PLL_B2
PLL_R3
PLL_R4
DLL4
PLL_T2
PLL_R2
PLL_R1
Figure 8-13 shows simple block diagram DLL. input reference clock goes into chain delay elements. phase comparator compares signal coming delay chain block input reference clock. phase comparator then issues upndn signal Gray-code counter. This signal increments decrements six-bit delay setting (DQS delay settings) that will increase decrease delay through delay element chain bring input reference clock signals coming delay element chain phase.
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Figure 8-13. Simplified Diagram Phase Shift Circuitry Note
addnsub_a Phase offset settings from logic array Phase Offset Control Phase offset settings pins bottom edge
Input Reference Clock Phase Comparator
upndn Up/Down Counter
addnsub_b Phase offset settings from logic array Phase Offset Control Phase offset settings
clock enable
Delay Chains Delay Settings
Notes Figure 8-13:
features phase-shift circuitry accessible from ALTMEMPHY megafunction Quartus software. input reference clock phase-shift circuitry come from output clock input clock pin. Refer Tables through exact input clock pin. Phase offset settings only logic blocks. delay settings logic array, logic block, leveling circuitry.
reset from either logic array user pin. Each time reset, must wait 1280 clock cycles before capture data properly. shift incoming signals 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°, 120°, 135°, 144°, 180°, depending frequency mode. shifted signal then used clock input registers. pins, referenced same DLL, have their input signal phase shifted different degree amount must referenced particular frequency. example, have phase shift DQS1T phase shift DQS2T, referenced from 200-MHz clock. phase-shift combinations supported, however.
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Stratix External Memory Interface Features
phase shifts pins referenced same must multiple 22.5° 90°), multiple 120°), multiple 144°), multiple 180°). There different frequency modes Stratix DLL, shown Table 8-10. Each frequency mode provides different phase shift selections. frequency mode 6-bit delay settings vary with implement phase-shift delay. frequency modes only bits delay settings vary implement phase-shift delay; most significant delay setting Refer Switching Characteristics Stratix Devices chapter Stratix Device Handbook frequency range each mode.
Table 8-10. Stratix Frequency Modes Frequency Mode
Note Table 8-10:
frequency range each mode please refer Switching Characteristics chapter Stratix Handbook volume
Delay Setting Width
bits bits bits bits bits bits
Available Phase Shift
22.5°, 45°, 67.5°, 30°, 60°, 90°, 120° 36°, 72°, 108°, 144° 30°, 60°, 90°, 120° 36°, 72°, 108°, 144° 45°, 90°, 135°, 180°
Number Delay Chains
shift, signal bypasses both logic blocks. Since Stratix pins designed such that delays matched, skew between registers negligible when shift implemented. feed delay settings logic block logic array. shifted signal goes clock input registers pins. signal also into logic array resynchronization using resynchronization registers. shifted signal only active-low input register only used QDRII+ QDRII SRAM interfaces.
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Phase Offset Control
Each phase-offset modules provide separate delay settings with independent offset, top/bottom bank left/right bank, fine-tune phase shift settings between different sides device. Even though have independent phase offset control, frequency interface using same same. should phase offset control module making small shifts input signal phase-shift circuitry larger signal shifts. example, only offers multiple phase shift, your interface needs 67.5° phase shift signal, delay chains logic blocks give phase shift phase offset control feature implement extra 7.5° phase shift. either static phase offset dynamic phase offset implement additional phase shift. available additional phase shift implemented 2's-complement Gray code between settings frequency mode between settings frequency modes phase shift delay settings user selected phase offset settings which maxes setting mode frequency mode maxes setting frequency modes actual physical offset setting range will subtracted delay settings from DLL. When using this feature, need monitor delay settings know many offest subtract system.
example, determines that delay settings needed achieve phase shift frequency mode subtract phase offset settings phase offset settings achieve optimal delay that need. However, same delay settings needed achieve phase shift frequency mode still subtract phase offset settings, only phase offset settings before delay settings reach their maximum settings, because frequency mode only uses 5-bit delay settings. Each phase offset setting translates certain delay specified Switching Characteristics Stratix Devices chapter Stratix Device Handbook.
Refer Switching Characteristics Stratix Devices chapter volume Stratix Device Handbook information value each step.
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When using static phase offset, specify phase offset amount ALTMEMPHY megafunction positive number addition negative number subtraction. also have dynamic phase offset that always added subtracted from, both added subtracted from phase shift. When always subtract, dynamically input phase offset amount into dll_offset[5.0] port. When want both subtract dynamically, control addnsub signal addition dll_offset[5.0] signals.
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Logic Block
Each connected separate logic block, which consists delay chains, update enable circuitry, postamble circuitry (see Figure 8-14). Figure 8-14. Stratix Logic Block
reset Enable gated_dqs control Delay Chain EnableN
DQS' Bypass
dqsenable
Phase offset settings from phase shift circuitry
Update Enable Circuitry
Postamble Enable Resynchronization Clock Postamble Clock
delay settings from phaseshift circuitry
Input Reference Clock
Note Figure 8-14:
input reference clock phase-shift circuitry come from output clock input clock pin. Refer Tables through exact input clock pin.
Delay Chain
delay chains consist variable delay elements allow input signals shifted amount specified phase-shift circuitry logic array. There four delay elements delay chain; first delay chain closest either shifted delay settings delay setting phase-offset setting. number delay chains required transparent users because ALTMEMPHY megafunction automatically sets when choose operating frequency. delay settings come from phase-shift circuitry either banks from logic array.
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Stratix External Memory Interface Features
delay elements logic block have same characteristics delay elements DLL. When used control delay chains, input your 6-bit 5-bit settings using dqs_delayctrlin[5.0]signals available ALTMEMPHY megafunction. These settings control delay elements delay chains. ALTMEMPHY megafunction also dynamically choose number delay chains needed system. amount delay equal delay element's intrinsic delay product number delay steps value delay steps. also bypass delay chain achieve phase shift.
Update Enable Circuitry
Both delay settings phase-offset settings pass through register before going into delay chains. registers controlled update enable circuitry allow enough time changes delay setting bits arrive delay elements. This allows them adjusted same time. update enable circuitry enables registers allow enough time delay settings travel from phase-shift circuitry core logic logic blocks before next change. uses input reference clock user clock from core generate update enable output. ALTMEMPHY megafunction uses this circuit default. Figure 8-15 example waveform update enable circuitry output. Figure 8-15. Update Enable Waveform
Counter Update (Every cycles) Counter Update (Every cycles)
System Clock
Delay Settings (Updated every cycles) Update Enable Circuitry Output
Postamble Circuitry
external memory interfaces that bidirectional read strobe like DDR3, DDR2, SDRAM, signal before going coming from high-impedance state. state where low, just after high-impedance state, called preamble state where low, just before returns high-impedance state, called
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postamble. There preamble postamble specifications both read write operations DDR3, DDR2, SDRAM. postamble circuitry, featured Figure 8-16, ensures that data lost when there noise line read postamble time. Stratix devices have dedicated postamble register that controlled ground shifted signal used clock input registers read operation. This ensures that glitches input signals read postamble time affect registers. Figure 8-16. Stratix Postamble Circuitry Note
reset Enable gated_dqs control EnableN
DQS'
Postamble Enable Resynchronization Clock Postamble Clock
DQSenable
Note Figure 8-16:
postamble clock come from delayed resynchronization clock taps although necessarily same phase resynchronization clock.
addition dedicated postamble register, Stratix devices also have block inside postamble enable circuitry. These registers used controller running half frequency I/Os. block first stage capture register postamble enable circuitry block Figure 8-16 optional. block clocked half-rate resynchronization clock, which
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output DIV2 circuit. There gate after postamble register outputs that used avoid postamble glitches from previous read burst non-consecutive read burst. This scheme allows half-aclock cycle latency dqsenable assertion zero latency dqsenable deassertion shown Figure 8-17. Figure 8-17. Avoiding Glitch Non-Consecutive Read Burst Waveform
Postamble glitch Postamble
Preamble
Postamble Enable
dqsenable
Delayed 1/2T logic
Leveling Circuitry
DDR3 SDRAM unbuffered modules fly-by clock distribution topology better signal integrity. This means that CK/CK# signals arrive each DDR3 SDRAM device module different times. difference arrival time between first DDR3 SDRAM device last device module long Figure 8-18 shows clock topology DDR3 SDRAM unbuffered modules.
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Figure 8-18. DDR3 SDRAM Unbuffered Module Clock Topology
DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ
CK/CK# DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ
Stratix
Because data read strobe signals still point-to-point, special consideration needs taken ensure that timing relationship between CK/CK# signals (tDQSS) during write every device modules. Furthermore, read data coming back into FPGA from memory will also staggered similar way. Stratix FPGAs have leveling circuitry take care these needs. There group leveling circuitry bank, located middle bank. These delay chains PVT-compensated same delay settings delay chains. frequencies equal above MHz, uses eight delay chains such that each delay chain generates delay. generated clock phases distributed every logic block that available bank. delay chain taps, then feeds multiplexer controlled ALTMEMPHY megafunction select which clock phases used that group. Each group different output from readleveling/write-leveling delay chains compensate different CK/CK# delay going into each device module. Figure 8-19 illustrates Stratix read write leveling circuitry.
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Figure 8-19. Stratix Read Write Leveling Delay Chains Multiplexers
Write (-900)
Write-Leveled Clock
Write-Leveled Clock
Resynchronization clock
DIV2
Half-Rate Resynchronization Clock
Half-Rate Source Synchronous Clock Read-Leveled Resynchronization Clock
Leveling Circuitry Multiplexers
-90° write clock ALTMEMPHY megafunction feeds write-leveling circuitry produce clock generate signals. During initialization, ALTMEMPHY megafunction picks correct write-leveled clock clocks each DQS/DQ group after sweeping available clocks write calibration process. clock output -90° phase-shifted compared clock output. Similarly, resynchronization clock feeds read-leveling circuitry produce optimal resynchronization postamble clock each DQS/DQ group calibration process. resynchronization postamble clocks different clock outputs from leveling circuitry. output from read-leveling circuitry also generate half-rate resynchronization clock that goes FPGA fabric. ALTMEMPHY megafunction calibrates alignment read write leveling dynamically during initialization process.
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Dynamic On-Chip Termination Control
Figure 8-20 shows dynamic control block. block includes registers needed dynamically turn during read turn during write.
more information refer section "OCT" page 8-43, Stratix Device Features chapter volume Stratix Device Handbook.
Figure 8-20. Stratix Dynamic Control Block
Control HalfRate Clock Enable
Block
Resynchronization Registers Write Clock
Control Path
Note Figure 8-20:
Write clock comes from either write leveling delay chain.
Element (IOE) Registers
registers have been expanded allow source-synchronous systems have faster register-to-register transfers resynchronization. Both top/bottom left/right IOEs have same capability with left/right IOEs having extra features support LVDS data transfer. Figure 8-21 shows registers available Stratix input path. input path consists input registers, resynchronization registers, block. Each block input path bypassed.
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Figure 8-21. Stratix Input Path Registers Note
Half Data Rate Registers
core
Double Data Rate Input Registers core
Input
Alignment Synchronization Registers
neg_reg_out
core
Input
Input
Resynchronization Clock
core
core DIV2 Half-Rate Resynchronization Clock
Notes Figure 8-21:
Each register block this path bypassed. There three levels resynchronization registers. input clock from logic block (whether postamble circuitry bypassed not) from global clock line. This input clock comes from logic block. This resynchronization clock come either from from read-leveling delay chain. divide-by-2 (DIV2) circuitry resides adjacent logic block. half-rate data clock signals feed into FIFO FPGA core.
There three registers input registers block. registers capture data positive negative edges clock, while third register aligns captured data. choose have same clock positive edge negative edge registers, different clocks (DQS positive edge register, negative edge register). third register that aligns captured data uses same clock positive edge registers. resynchronization registers consist three levels registers resynchronize data system clock domain. These registers clocked resynchronization clock that either generated
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read-leveling delay chain. outputs resynchronization registers straight core blocks, which clocked divided-down resynchronization clock. more information about read-leveling delay chain, refer "Leveling Circuitry" page 8-36. Figure 8-22 shows registers available Stratix output output-enable paths. path divided into block, resynchronization registers, output/output-enable registers. device bypass each block output output-enable path.
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Figure 8-22. Stratix Output Output-Enable Path Registers Note
Half Data Rate Single Data Rate Output-Enable Registers From Core
Double Data Rate Output-Enable Registers
Alignment Registers
From Core
Half Data Rate Single Data Rate Output Registers From Core Double Data Rate Output Registers From Core Output Alignment Registers From Core
Output
From Core
Half-Rate Clock(3)
Alignment Clock
Write Clock
Notes Figure 8-22:
Each register block output output enable paths bypassed. Data coming from FPGA core half frequency memory interface. Half-rate alignment clocks come from PLL. There levels registers data alignment. These registers only used DDR3 SDRAM interfaces. write clock come from either from write leveling delay chain. write clock write clock have offset between them.
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output path designed route combinatorial registered outputs full-rate half-rate outputs from FPGA core. Half-rate data converted full-rate using block, clocked half-rate clock from PLL. resynchronization registers also clocked same system clock, except DDR3 SDRAM interface. DDR3 SDRAM interfaces, leveling registers clocked write-leveling clock. more information write leveling delay chain, refer "Leveling Circuitry" page 8-36. output-enable path structure similar output path. have combinatorial registered output applications half-rate full-rate operation applications. also have resynchronization registers like output path registers structure, ensuring that output enable path goes through same delay latency output path.
Features
This section briefly describes OCT, programmable delay chains, programmable output delay, slew rate adjustment, programmable drive strength useful memory interfaces.
more information about features listed below, refer Stratix Device Features chapter volume Stratix Device Handbook.
Stratix devices feature dynamic calibrated OCT, which series termination (OCT turned when driving signals turned when receiving signals, while parallel termination (OCT turned when driving signals turned when receiving signals. This feature complements DDR3/DDR2 SDRAM on-die termination (ODT), whereby memory termination turned when memory sending data turned when receiving data. other memory interfaces improve signal integrity. cannot programmable drive strength programmable slew rate features when using
dynamic calibrated OCT, must pins calibrate calibration block. calibration block used calibrate type termination with same VCCIO
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entire device. There calibration blocks allow different types terminations throughout device. more details, refer "Dynamic On-Chip Termination Control" page 8-39. have option feature with without calibration. However, feature only available with calibration.
pins also used pins, cannot DQS/DQ groups where pins located planning dynamic calibrated OCT. pins located first last DQS/DQ group each side device. should RT/RS setting uni-directional read/write data dynamic setting bi-directional data signals.
Programmable Delay Chains
programmable delay chains Stratix registers used deskewing circuitry. Each have different input delay from input register delay from output register output ensure that same delay going into FPGA. This feature helps read write time margins minimizes uncertainties between signals bus.
Programmable Output Buffer Delay
addition allowing output buffer duty cycle adjustment, programmable output buffer delay chain allows adjust delays between data bits your output introduce compensate channel-to-channel skew. Incorporating skew output help minimize simultaneous switching events enabling smaller parts switch simultaneously, instead whole bus. This feature also particularly useful DDR3 SDRAM interfaces where memory system clock delay much larger than data data clock/strobe delay. this delay chain delay data data clock/strobe better match memory system clock delay.
Programmable Slew Rate Control
Stratix devices provide four levels static output slew rate control: where slowest slew rate setting fastest slew rate setting. default setting HSTL SSTL standards fast slew rate setting allows achieve higher performance, while slow slew-rate setting reduces system noise signal overshoot. This feature disabled using features.
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Programmable Drive Strength
choose optimal drive strength needed your interface after performing board simulation. Higher drive strength helps provide larger voltage swing, which turn provides bigger diagrams with greater timing margin. However, higher drive strengths typically require more power, faster slew rates simultaneous switching noise. programmable slew rate control along with this feature minimize simultaneous switching noise with higher drive strengths. This feature also disabled using feature, which default drive strength Stratix devices. should RT/RS setting unidirectional read/write data dynamic setting bidirectional data signals. need simulate system determine drive strength needed command, address, clock signals.
PLLs used generate memory interface controller clocks, like system clock, -90° 270° phase-shifted write clock, half-rate clock, resynchronization clock. reconfiguration feature used calibrate resynchronization phase shift balance setup hold margin. counter setting combinations limited high performance memory interfaces. more information about Stratix PLL, refer Clock Networks PLLs Stratix Devices chapter volume Stratix Device Handbook.
Conclusion
Stratix devices have many features available support existing emerging external memory interfaces. ALTMEMPHY megafunction, built support Stratix memory interface features, allows customers easily implement their data path with either their controller Altera's controller. Stratix devices, most critical data transfers taken care IOE, alleviating burden having close timing FPGA fabric. Furthermore, since most registers IOE, data delays between registers short, allowing circuitry work higher frequency. Dynamically calibrated OCT, slew rate adjustment, programmable drive strength improve signal integrity, especially higher frequencies operation.
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Document Revision History
addition, programmable delay chain de-skew circuits allow Stratix devices achieve better margin high performance memory interfaces. Dynamic calibration resynchronization postamble clocks guarantee high performance over variations. Leveling circuitry enables Stratix support DDR3 modules, thus offering customers choice highest performance memory technologies. Stratix devices also offer memory interface support modular banks with four different frequencies operations.
Document Revision History
Table 8-11 shows revision history this document.
Table 8-11. Document Revision History Date Document Version
2007 v1.1
Changes Made
Updated Figure 8-5, Figure 8-8, Figure 8-14, Figure 8-18, Figure 8-19, Figure 8-20, Figure 8-21. Added figure, Figure 8-17. Added memory support information Table 8-1, Table 8-7, Table 8-8, Table 8-9. Added material "Phase Offset Control" page 8-31.
Summary Changes
Minor updates content.
November 2006 Initial Release v1.0
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SIII51008-1.1 Stratix® structure been completely redesigned from

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