SIII51005-1.1 Stratix® family devices have dedicated high-perform
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Blocks Stratix Devices
SIII51005-1.1
Stratix® family devices have dedicated high-performance digital signal processing (DSP) blocks optimized applications. These blocks Altera® Stratix device family third generation hardwired, fixed function silicon blocks dedicated maximizing signal processing capability, ease use, lowest silicon cost. Many complex systems such WiMAX, 3GPP WCDMA, high-performance computing (HPC), voice over Internet protocol (VoIP), H.264 video compression, medical imaging, HDTV sophisticated digital signal processing techniques, this typically requires large number mathematical computations. Stratix devices ideally suited blocks consist combination dedicated elements that perform multiplication, addition, subtraction, accumulation, summation, dynamic shift operations. Along with high-performance Stratix soft logic fabric TriMatrixmemory structures, configure these blocks build sophisticated fixed-point floating-point arithmetic functions. These manipulated easily implement common larger computationally intensive subsystems such finite impulse response (FIR) filters, complex filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, discrete cosine transform (DCT) functions.
Block Overview
Each Stratix device seven columns blocks that implement multiplication, multiply-add, multiply-accumulate (MAC), dynamic shift functions efficiently. logical functionality Stratix block superset previous generation block found Stratix Stratix devices. Architectural highlights Stratix block include:
High-performance, power-optimized, fully registered pipelined multiplication operations Natively supported 9-bit, 12-bit, 18-bit, 36-bit wordlengths Natively supported 18-bit complex multiplications Efficiently supported floating-point arithmetic formats (24-bit single precision 53-bit double precision) Signed unsigned input support
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Block Overview
Built-in addition, subtraction accumulation units combine multiplication results efficiently Cascading 18-bit input form tap-delay line filtering applications Cascading 44-bit output propagate output results from block next block without external logic support Rich flexible arithmetic rounding saturation units Efficient barrel shifter support Loopback capability support adaptive filtering
number blocks Stratix device family shown Table 5-1.
Table 5-1. Number Blocks Stratix Devices Four Multiplier Adder Mode
Independent Input Output Multiplication Operators
Device
EP3SL50 EP3SL70 EP3SL110 Stratix Logic EP3SL150 EP3SL200 EP3SE260 EP3SL340 EP3SE50 Stratix Enhanced EP3SE80 EP3SE110 EP3SE260 Note Table 5-1:
Blocks Multipliers Multipliers Multipliers Complex Multipliers
EP3SE260 device rich memory, multiplier resources. Hence, aligns with both logic enhanced variants.
Table shows that largest Stratix centric device (EP3SE110) provides multiplier functionality complex summation modes.
Stratix Device Handbook, Volume
Altera Corporation 2007
Blocks Stratix Devices
Each block occupies four blocks height divided further into half-blocks that share some common clock signals, common purposes identical functionality. layout each block shown Figure 5-1. Stratix block input data lines bits double that Stratix Stratix number output data lines remains bits.
Figure 5-1. Overview Block Signals
Control
Half-DSP Block
Output Data
Input Data
Half-DSP Block
Output Data
Full Block
Simplified Operation
Stratix Stratix devices, fundamental building block consists 18-bit 18-bit multiplier that also function 9-bit 9-bit multipliers. Stratix III, fundamental building block pair 18-bit 18-bit multipliers followed first-stage 37-bit addition/subtraction unit, shown Equation Figure 5-2. Note that signed numbers, input output data represented complement format only. Equation 5-1. Multiplier Equation P[36.0] A0[17.0] B0[17.0] A1[17.0] B1[17.0]
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Stratix Device Handbook, Volume
Simplified Operation
Figure 5-2. Basic Two-Multiplier Adder Building Block
A0[17.0]
B0[17.0]
A1[17.0]
P[36.0]
B1[17.0]
structure shown Figure very useful building more complex structures, such complex multipliers multipliers, described later sections. Each Stratix block contains four Two-Multiplier Adder units (two Two-Multiplier Adder units half-block). Therefore, there eight multiplier functionalities block.
Stratix Device Handbook, Volume
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Blocks Stratix Devices
Following Two-Multiplier Adder units pipeline registers, second-stage adders, output register stage. configure second-stage adders provide following alternative functions Half-Block: Equation 5-2. Four-Multiplier Adder Equation Z[37.0] P0[36.0] P1[36.0]
Equation 5-3. Four-Multiplier Adder Equation (44-Bit Accumulation) Wn[43.0] Wn-1[43.0] Zn[37.0]
these equations, denotes sample time, P[36.0] results from Two-Multiplier Adder units. Equation provides four 18-bit 18-bit multiplication operations (Four-Multiplier Adder), Equation provides four 18-bit 18-bit multiplication operation with maximum 44-bit accumulation capability feeding output unit back itself. This shown Figure 5-3. bypass register stages depending which mode select.
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Stratix Device Handbook, Volume
Simplified Operation
Figure 5-3. Four-Multiplier Adder Accumulation Capability
Pipeline Register Bank
Input Data
Adder/ Accumulator
Output Register Bank
Input Register Bank
Result
Half-DSP Block
support commonly found FIR-like structures efficiently, major addition block Stratix ability propagate result Half-Block next Half-Block completely within block without additional soft logic overhead. This achieved inclusion dedicated addition unit routing that adds 44-bit result previous Half-Block with 44-bit result current block. 44-bit result either next Half-Block block output register stage. This shown Figure 5-4. Detailed examples described later sections. combination fast, low-latency Four-Multiplier Adder unit "chained cascade" capability output chaining adder provides optimal vector multiplication capability.
Stratix Device Handbook, Volume
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Blocks Stratix Devices
support single-channel type filters efficiently, configure multiplier input's registers form delay line input, saving resources providing higher system performance. Figure 5-4. Output Cascading Feature Structures
From Previous Half-Block
Pipeline Register Bank
Input Data
Output Register Bank
Input Register Bank
Round/Saturate
Adder/ Accumulator
Result
Half Block
Next Half-Block
Also shown Figure optional Rounding Saturation Unit (RSU). This unit provides rich commonly found arithmetic round saturation functions used signal processing. addition independent multipliers modes, blocks perform shift operations. block dynamically switch between logical shift left/right, arithmetic shift left/right, rotation operation clock cycle. top-level view Stratix block shown Figure 5-5. more detailed diagram shown Figure 5-6.
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Stratix Device Handbook, Volume
Simplified Operation
Figure 5-5. Stratix Full Block Summary
From Previous Half-Block
Pipeline Register Bank Output Register Bank Input Register Bank Adder/Accumulator Round/Saturate Output
Input Data
Result
Half-DSP Block
Pipeline Register Bank Output Register Bank Input Register Bank Adder/Accumulator Round/Saturate Output
Input Data
Result
Bottom Half-DSP Block
Next Half-Block
Stratix Device Handbook, Volume
Altera Corporation 2007
Blocks Stratix Devices
Operational Modes Overview
Each Stratix block used five basic operational modes. Table shows five basic operational modes number multipliers that implemented within single block, depending mode.
Table 5-2. Stratix Block Operation Modes Mode Multiplier Width
9-bits 12-bits Independent Multiplier 18-bits 36-bits Double Two-Multiplier Adder(1) Four-Multiplier Adder Multiply Accumulate Shift
Mults
Block
Signed Unsigned
Both Both Both Both Both Signed Both Both Both
RND,
Shift Chainout Register Adder
Stage Stage Add/Sub Add/Acc
Both Both Both Only Both
18-bits 18-bits 18-bits 36-bits
Notes Table 5-2:
This mode also supports loopback mode. loopback mode, number loopback multipliers block remaining multipliers used regular Two-Multiplier Adder mode. dynamic shift mode supports arithmetic shift left, arithmetic shift right, logical shift left, logical shift right, rotation operation. dynamic shift mode operates 32-bit input vector multiplier width configured 36-bits. Unsigned value also supported must make sure that result contained within 36-bits.
block consists identical halves (top-half bottom-half). Each half four multipliers. Quartus® software includes megafunctions used control mode operation multipliers. After making appropriate parameter settings using megafunction's MegaWizard® Plug-In Manager, Quartus software automatically configures block. Stratix blocks operate different modes simultaneously. Each Half-block fully independent except sharing four clock, ena, aclr signals. example, break down single block operate multiplier Half-Block two-multiplier adder other Half-Block. This increases block
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Stratix Device Handbook, Volume
Block Resource Descriptions
resource efficiency allows implement more multipliers within Stratix device. Quartus software automatically places multipliers that share same block resources within same block.
Block Resource Descriptions
block consists following elements:
Input register bank Four Two-Multiplier Adders Pipeline register bank second-stage adders Four round saturation logic units Second adder register output register bank
detailed overall architecture half block shown Figure 5-6.
5-10 Stratix Device Handbook, Volume
Altera Corporation 2007
Blocks Stratix Devices
Figure 5-6. Half-DSP Block Architecture
zero_loopback accum_sload zero_chainout chainout_round chainout_saturate signa signb output_round output_saturate rotate shift_right
chainin[ scanina[
clock[3.0] ena[3.0] alcr[3.0]
overflow chainout_sat_overflow
dataa_0[ First Stage Adder
loopback
datab_0[ dataa_1[ Input Register Bank
Second Stage Adder/Accumulator
Pipeline Register Bank
First Round/Saturate
Output Register Bank
datab_1[ dataa_2[
Shift/Rotate
Second Adder Register Bank
datab_2[ dataa_3[
datab_3[
Half-DSP Block
Input Registers
block registers triggered positive edge clock signal cleared upon power Each multiplier operand feed input register directly multiplier, bypassing input registers. (This configured compile time.) following block signals control input registers within block:
clock[3.0] ena[3.0] aclr[3.0]
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5-11 Stratix Device Handbook, Volume
Second Round/Saturate
First Stage Adder
Chainout Adder
result[
Block Resource Descriptions
Every block nine 18-bit data input register banks half block. Every half block option eight data register banks inputs four multipliers. special ninth register bank delay register required modes that both cascade chainout features block balancing latency requirements when using chained cascade feature. feature input register bank support delay line. Therefore, multiplier input driven from general routing from cascade chain, shown Figure 5-7.
5-12 Stratix Device Handbook, Volume
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Blocks Stratix Devices
Figure 5-7. Input Register Half-DSP Block
clock[3.0] ena[3.0] aclr[3.0] scanina[17.0] signa signb
dataa_0[17.0]
loopback datab_0[17.0]
dataa_1[17.0]
datab_1[17.0]
dataa_2[17.0]
datab_2[17.0]
dataa_3[17.0]
datab_3[17.0]
Delay Register
Altera Corporation 2007
5-13 Stratix Device Handbook, Volume
Block Resource Descriptions
must select whether A-input comes from general routing from cascade chain compile time. cascade mode, dedicated shift outputs from multiplier block directly feeds input registers adjacent multiplier below (within same half block) first multiplier next half block, form 8-tap shift register chain Block. block increase length shift register chain cascading lower blocks. dedicated shift register chain spans single column, implement longer shift register chains requiring multiple columns using regular FPGA routing resources. Shift registers useful functions such filters. When implementing smaller width multipliers, need external logic create shift register chain because input shift registers internal block. This implementation significantly reduces logical element (LE) resources required, avoids routing congestion, results predictable timing. first multiplier every half block (top- bottom-half) Stratix devices first multiplier B-input (lower-leg input) register select between general routing loopback, shown Figure 5-6. loopback mode, most significant 18-bit registered outputs connected feedback multiplier input first multiplier each half block. Loopback modes used recursive filters where previous output needed compute current output. loopback mode described detail "Two-Multiplier Adder Mode" page 5-25. Table shows summary input register modes block.
Table 5-3. Input Register Modes Register Input Mode
Parallel input Shift register input Loopback input Notes Table 5-3:
multiplier operand input wordlengths statically configured compile time. Available only A-operand. Only loopback input allowed Half-Block. Figure 5-15 details.
Double
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Blocks Stratix Devices
Multiplier First-Stage Adder
multiplier stage natively supports multipliers. Other wordlengths padded nearest appropriate native wordlength; example, would padded Refer "Independent Multiplier Modes" page 5-18 more details. Depending data width multiplier, single block perform many multiplications parallel. Each multiplier operand unique signed unsigned number. dynamic signals, signa signb, control representation each operand, respectively. logic value signa/signb signal indicates that data A/data signed number; logic value indicates unsigned number. Table shows sign multiplication result various operand sign representations. result multiplication signed operands signed value.
Table 5-4. Multiplier Sign Representation Data (signa Value)
Unsigned (logic Unsigned (logic Signed (logic Signed (logic
Data (signb Value)
Unsigned (logic Signed (logic Unsigned (logic Signed (logic
Result
Unsigned Signed Signed Signed
Each Half Block signa signb signal. Therefore, data inputs feeding same Half Block must have same sign representation. Similarly, data inputs feeding same Half Block must have same sign representation. multiplier offers full precision regardless sign representation operational modes except full precision loopback Two-Multiplier Adder modes. Refer "Two-Multiplier Adder Mode" page 5-25 details. When signa signb signals unused, Quartus software sets multiplier perform unsigned multiplication default.
outputs multipliers only outputs that feed into first-stage adder, shown Figure 5-6. There four first-stage adders block (two adders half block). first-stage adder block ability perform addition subtraction. control signal addition subtraction static configured upon
Altera Corporation 2007
5-15 Stratix Device Handbook, Volume
Block Resource Descriptions
compile time. first-stage adders used modes compute multipliers, 18-complex multipliers, perform first stage multiply shift operation. Depending your specifications, output first-stage adder option feed into pipeline registers, second-stage adder, round saturation unit, output registers.
Pipeline Register Stage
output from first-stage adder either feed bypass pipeline registers, shown Figure 5-6. Pipeline registers increase block's maximum performance expense extra cycles latency), especially when using subsequent block stages. Pipeline registers split long signal path between adder second-stage creating shorter paths.
Second-Stage Adder
There four individual 44-bit second-stage adders block adders half block). configure second-stage adders follows:
final stage 36-bit multiplier four accumulator (44-bits maximum) chained output summation (44-bits maximum) chained-output adder used same time second-level adder chained output summation mode.
output second-stage adder option into round saturation logic unit output register. cannot second-stage adder independently from multiplier first-stage adder.
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Blocks Stratix Devices
Round Saturation Stage
round saturation logic units located output 44-bit second-stage adder (round logic unit followed saturation logic unit). There round saturation logic units half block. input round saturation logic unit come from following stages:
Output multiplier (independent multiply mode Output first-stage adder (Two-Multiplier Adder) Output pipeline registers Output second-stage adder (Four-Multiplier Adder, Multiply-Accumulate Mode
These stages discussed detail "Operational Mode Descriptions" page 5-18. round saturation logic unit controlled dynamic round saturate signals, respectively. logic value round and/or saturate enables round and/or saturate logic unit, respectively. round saturation logic units together independently.
Second Adder Output Registers
second adder register output register banks banks 44-bit registers that also combined form larger 72-bit banks support output results. outputs different stages Stratix devices routed output registers through output selection unit. Depending operational mode block, output selection unit selects whether outputs blocks comes from outputs multiplier block, first-stage adder, pipeline registers, second-stage adder, round saturation logic unit. output selection unit automatically software, based block operational mode specified, option either drive bypass output registers. exception when block used shift mode, which case user dynamically controls output-select directly. When block configured "chained cascaded" output mode, both second-stage adders used. first used performing Four-Multiplier Adder second used chainout adder. outputs Four-Multiplier Adder routed second-stage adder registers before enters chainout adder. output chainout adder goes regular output register bank.
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5-17 Stratix Device Handbook, Volume
Operational Mode Descriptions
Depending configuration, chainout results routed input next half-block's chainout adder input general fabric (functioning regular output registers). Refer "Operational Mode Descriptions" page 5-18 details. second-stage output registers triggered positive edge clock signal cleared power following block signals control output registers within block:
clock[3.0] ena[3.0] aclr[3.0]
Operational Mode Descriptions
Independent Multiplier Modes
independent input output multiplier mode, block performs individual multiplication operations general-purpose multipliers.
18-Bit Multiplier
configure each block multiplier 12-, 18-bit multiplication. single block support eight individual multipliers, multipliers, four individual multipliers. operand widths bits, multiplier implemented. operand widths from bits, multiplier implemented, operand widths from bits, multiplier implemented. This done Quartus software zero-padding LSBs. Figures 5-8, 5-9, 5-10 show block independent multiplier operation mode.
5-18 Stratix Device Handbook, Volume
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Blocks Stratix Devices
Figure 5-8. 18-Bit Independent Multiplier Mode Shown Half-DSP Block
signa clock[3.0] ena[3.0] aclr[3.0] signb output_round output_saturate
overflow
dataa_0[17.0]
Round/Saturate
result_0[
Pipeline Register Bank
datab_0[17.0] dataa_1[17.0]
Round/Saturate
Output Register Bank
Input Register Bank
result_1[
datab_1[17.0]
Half-DSP Block
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5-19 Stratix Device Handbook, Volume
Operational Mode Descriptions
Figure 5-9. 12-Bit Independent Multiplier Mode Shown Half-DSP Block
clock[3.0] ena[3.0] aclr[3.0] signa signb
dataa_0[11.0]
result_0[
datab_0[11.0] dataa_1[11.0] Output Register Bank Input Register Bank
Pipeline Register Bank
result_1[
datab_1[11.0]
dataa_2[11.0]
result_2[
datab_2[11.0]
Half-DSP Block
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Blocks Stratix Devices
Figure 5-10. 9-Bit Independent Multiplier Mode Shown Half-Block
clock[3.0] ena[3.0] aclr[3.0] signa signb
dataa_0[8.0]
result_0[
datab_0[8.0]
dataa_1[8.0]
Pipeline Register Bank
datab_1[8.0]
dataa_2[8.0]
Output Register Bank
result_1[
Input Register Bank
result_2[
datab_2[8.0]
dataa_3[8.0]
result_3[
datab_3[8.0]
Half-DSP Block
multiplier operands accept signed integers, unsigned integers, combination both. change signa signb signals dynamically registered block. Additionally,
Altera Corporation 2007
5-21 Stratix Device Handbook, Volume
Operational Mode Descriptions
multiplier inputs result registered independently. pipeline registers within block pipeline multiplier result, increasing performance block. round saturation logic unit supported 18-bit independent multiplier mode only.
36-Bit Multiplier
efficiently construct multiplier using four multipliers. This simplification fits conveniently into half-DSP block, implemented block automatically selecting mode. Stratix devices have 36-bit multipliers block (one 36-bit multiplier half block). 36-bit multiplier also under independent multiplier mode uses entire half block, including dedicated hardware logic after pipeline registers implement multiplication operation. This shown Figure 5-11. 36-bit multiplier useful applications requiring more than 18-bit precision; example, mantissa multiplication portion single precision extended single precision floating-point arithmetic applications.
5-22 Stratix Device Handbook, Volume
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Blocks Stratix Devices
Figure 5-11. 36-Bit Independent Multiplier Mode Shown Half-DSP Block
clock[3.0] ena[3.0] aclr[3.0] signa signb
dataa_0[35.18]
datab_0[35.18] dataa_0[17.0] Input Register Bank
Pipeline Register Bank Output Register Bank
datab_0[35.18] dataa_0[35.18]
result[
datab_0[17.0] dataa_0[17.0]
datab_0[17.0]
Half-DSP Block
Double Multiplier
Stratix block configured efficiently support unsigned multiplier that required compute mantissa portion IEEE double precision floating point multiplication. multiplier built using basic multipliers, shifters adders. order efficiently utilize Stratix block's built
Altera Corporation 2007
5-23 Stratix Device Handbook, Volume
Operational Mode Descriptions
shifters adders, special Double mode (partial multiplier) available that slight modification basic Multiplier mode. This shown Figure 5-12 Figure 5-13. Figure 5-12. Double Mode Shown Half-DSP Block
clock[3.0] ena[3.0] aclr[3.0] signa signb
dataa_0[35.18]
datab_0[35.18] dataa_0[17.0]
Pipeline Register Bank Output Register Bank Input Register Bank
datab_0[35.18] dataa_0[35.18]
result[
datab_0[17.0] dataa_0[17.0]
datab_0[17.0]
Half-DSP Block
5-24 Stratix Device Handbook, Volume
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Blocks Stratix Devices
Figure 5-13. Unsigned Multiplier
clock[3.0] ena[3.0] aclr[3.0] signa signb
Multiplier Adder Mode
dataa[53.36]
datab[53.36]
dataa[35.18]
Double Mode
datab[53.36] dataa[17.0] Shifters Adders Final Adder (implemented with ALUT logic)
datab[53.36] dataa[53.36]
result[
datab[35.18] dataa[53.36]
datab[17.0]
dataa[35.18]
Mode
datab[35.18] dataa[17.0] Shifters Adders
datab[35.18] dataa[35.18]
datab[17.0] dataa[17.0]
datab[17.0] Unsigned Multiplier
Two-Multiplier Adder Mode
two-multiplier adder configuration, block implement four 18-bit Two-Multiplier Adders Two-Multiplier Adders half block). configure adders take difference
Altera Corporation 2007
5-25 Stratix Device Handbook, Volume
Operational Mode Descriptions
multiplier outputs. Summation subtraction selected compile time. Two-Multiplier Adder function useful applications such FFTs, complex FIR, filters. Figure 5-14 shows block configured two-multiplier adder mode. loopback mode other sub-feature two-multiplier adder mode. Figure 5-15 shows block configured loopback mode. This mode takes 36-bit summation result multipliers feeds back most significant 18-bits input. lower 18-bits discarded. have option disable zero-out loopback data using dynamic zero_loopback signal. logic value zero_loopback signal selects zeroed data disables looped back data, while logic selects looped back data. option loopback mode general two-multiplier adder mode must selected compile time.
Two-Multiplier Adder mode, inputs full 18-bit unsigned, result will require bits. output data width Two-Multiplier Adder mode limited bits, this 37-bit output requirement allowed. other combination that does violate 36-bit maximum result permitted; example, signed Two-Multiplier Adders valid. two-multiplier adder mode supports round saturation logic unit. pipeline registers output registers within block pipeline multiplier-adder result, increasing performance block.
5-26 Stratix Device Handbook, Volume
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Blocks Stratix Devices
Figure 5-14. Two-Multiplier Adder Mode Shown Half-DSP Block
signa clock[3.0] ena[3.0] aclr[3.0] signb output_round output_saturate
overflow
dataa_0[17.0]
Pipeline Register Bank
datab_0[17.0] dataa_1[17.0]
Output Register Bank
Input Register Bank
Round/Saturate
result[
datab_1[17.0]
Half-DSP Block
Altera Corporation 2007
5-27 Stratix Device Handbook, Volume
Operational Mode Descriptions
Figure 5-15. Loopback Mode Half-DSP Block
clock[3.0] ena[3.0] aclr[3.0] signa signb output_round output_saturate
zero_loopback
overflow
dataa_0[17.0]
Pipeline Register Bank
datab_0[17.0] dataa_1[17.0]
Round/Saturate
loopback
Output Register Bank
Input Register Bank
result[
datab_1[17.0]
Half-DSP Block
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Blocks Stratix Devices
Complex Multiply
configure block when used Two-Multiplier Adder mode implement complex multipliers using two-multiplier adder mode. single half block implement 18-bit complex multiplier. complex multiplication written shown Equation 5-4. Equation 5-4. Complex Multiplication Equation j((a
implement this complex multiplication within block, real part implemented using multipliers feeding subtractor block while imaginary part implemented using another multipliers feeding adder block. Figure 5-16 shows 18-bit complex multiplication. This mode automatically assumes inputs using signed numbers.
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5-29 Stratix Device Handbook, Volume
Operational Mode Descriptions
Figure 5-16. Complex Multiplier Using Two-Multiplier Adder Mode
clock[3.0] ena[3.0] aclr[3.0] signa signb
(Real Part)
Pipeline Register Bank
Output Register Bank
Input Register Bank
(Imaginary Part)
Half-DSP Block
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Blocks Stratix Devices
Four-Multiplier Adder
four-multiplier adder configuration shown Figure 5-17, block implement four-multiplier adders (one four-multiplier adder half block). These modes useful implementing one-dimensional two-dimensional filtering applications. four-multiplier adder performed addition stages. outputs four multipliers initially summed first-stage adder blocks. results these adder blocks then summed second-stage adder block produce final four-multiplier adder result, shown Equation Equation 5-3.
Altera Corporation 2007
5-31 Stratix Device Handbook, Volume
Operational Mode Descriptions
Figure 5-17. Four-Multiplier Adder Mode Shown Half-DSP Block
clock[3.0] ena[3.0] aclr[3.0] signa signb output_round output_saturate
overflow
dataa_0[
datab_0[
dataa_1[
Pipeline Register Bank
datab_1[ dataa_2[
Output Register Bank
Input Register Bank
Round/Saturate
result[
datab_2[
dataa_3[
datab_3[
Half-DSP Block
four-multiplier adder mode supports round saturation logic unit. pipeline registers output registers within block pipeline multiplier-adder result, increasing performance block.
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Blocks Stratix Devices
Multiply Accumulate Mode
multiply accumulate mode, second-stage adder configured 44-bit accumulator subtractor. output block looped back second-stage adder added subtracted with outputs first-stage adder block according Equation 5-3. Figure 5-18 shows block configured operate multiply accumulate mode. Figure 5-18. Multiply Accumulate Mode Shown Half-DSP Block
clock[3.0] ena[3.0] aclr[3.0] accum_sload signa signb output_round output_saturate chainout_sat_overflow
dataa_0[
datab_0[
dataa_1[
Pipeline Register Bank
Second Register Bank
datab_1[
Output Register Bank
Input Register Bank
Round/Saturate
result[
dataa_2[
datab_2[
dataa_3[
datab_3[
Half-DSP Block
Altera Corporation 2007
5-33 Stratix Device Handbook, Volume
Operational Mode Descriptions
single block implement independent 44-bit accumulators. dynamic accum_sload control signal used clear accumulation. logic value accum_sload signal synchronously loads accumulator with multiplier result only, while logic enables accumulation adding subtracting output block (accumulator feedback) output multiplier first-stage adder. control signal accumulator subtractor static therefore configured compile time.
This mode supports round saturation logic unit configured 18-bit multiplier accumulator. pipeline registers output registers within block increase performance block.
Shift Modes
Stratix devices support following shift modes 32-bit input only:
Arithmetic shift left, ASL[N] Arithmetic shift right, ASR[32-N] Logical shift left, LSL[N] Logical shift right, LSR[32-N] 32-bit rotator Barrel shifter, ROT[N] switch shift mode between these modes using dynamic rotate shift control signals.
shift mode Stratix device easily used soft embedded processor such Nios® perform dynamic shift rotate operation. Figure 5-19 shows shift mode configuration. shift mode makes available multipliers logically arithmetically shift left, right, rotate desired 32-bit data. block configured like independent 36-bit multiplier mode perform shift mode operations. arithmetic shift right requires signed input vector. During arithmetic shift right, sign extended fill 32-bit vector. logical shift right uses unsigned input vector. During logical shift right, zeros padded most significant bits shifting 32-bit vector right. barrel shifter uses unsigned input vector implements rotation function 32-bit word length.
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Blocks Stratix Devices
control signals rotate shift_right together with signa signb signals, determining shifting operation. Examples shift operations shown Table 5-5. Figure 5-19. Shift Operation Mode Shown Half-DSP Block
clock[3.0] ena[3.0] aclr[3.0] signa signb rotate shift_right
dataa_0[35.18]
datab_0[35.18]
dataa_0[17.0]
Pipeline Register Bank
Shift/Rotate
datab_0[35.18]
Output Register Bank
Input Register Bank
dataa_0[35.18]
result[
datab_0[17.0]
dataa_0[17.0]
datab_0[17.0]
Half-DSP Block
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5-35 Stratix Device Handbook, Volume
Operational Mode Descriptions
Table 5-5. Examples Shift Operations Example
Logical Shift Left LSL[N] Logical Shift Right
Signa
Unsigned Unsigned
Signb
Unsigned Unsigned
Shift
Rotate
A-input
0xAABBCCDD 0xAABBCCDD
B-input
0x0000100 0x0000100
Result
0xBBCCDD00 0x000000AA
LSR[32-N]
Arithmetic Shift Left ASL[N] Arithmetic Shift Right Signed Signed Unsigned Unsigned 0xAABBCCDD 0xAABBCCDD 0x0000100 0x0000100 0xBBCCDD00 0xFFFFFFAA
ASR[32-N]
Rotation Unsigned Unsigned 0xAABBCCDD 0x0000100 0xBBCCDDAA
ROT[N]
Rounding Saturation Mode
Round saturation functions often required arithmetic. Rounding used limit growth side effects saturation used reduce overflow underflow side effects. rounding modes supported Stratix devices:
Round-to-nearest-integer mode Round-to-nearest-even mode
must select options compile time. Round-to-nearest-integer provides biased rounding support simplest form rounding commonly used arithmetic. round-to-nearest-even method provides unbiased rounding support used where offsets concern. Table shows round-to-nearest-even works. Examples difference between modes shown Table 5-7. this example, 6-bit input rounded bits. observe from Table that main difference between rounding options when residue bits exactly half between nearest integers zero (even).
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Blocks Stratix Devices
Table 5-6. Example Round-To-Nearest-Even Mode 4-bits Rounding
010111 001101 001010 001110 110111 101101 110110 110010
Odd/Even (Integer)
Even (0010) (0011) (1101) Even (1100)
Fractional
(11) (01) (10) (10) (11) (01) (10) (10)
Integer
Result
0110 0011 0010 0100 1110 1011 1110 1100
Table 5-7. Comparison Round-to-Nearest-Integer Round-to-Nearest-Even Round-To-Nearest-Integer 010111 0110 001101 0011 001010 0011 001110 0100 110111 1110 101101 1011 110110 1110 110010 1101 Round-To-Nearest-Even 010111 0110 001101 0011 001010 0010 001110 0100 110111 1110 101101 1011 110110 1110 110010 1100
saturation modes supported Stratix III:
Asymmetric saturation mode Symmetric saturation mode
must select options compile time.
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Operational Mode Descriptions
complement format, maximum negative number that represented -2(n-1) while maximum positive number 2(n-1)-1. Symmetrical saturation will limit maximum negative number -2(n-1) example, bits:
Asymmetric 32-bit saturation: 0x7FFFFFFF, 0x80000000 Symmetric 32-bit saturation: 0x7FFFFFFF, 0x80000001
Table shows saturation works. this example, 44-bit input saturated 36-bits.
Table 5-8. Examples Saturation Bits Saturation
5926AC01342h ADA38D2210h
Symmetric Result
7FFFFFFFFh 800000001h
Asymmetric Result
7FFFFFFFFh 800000000h
Stratix devices have configurable positions 44-bit ([43:0]) round saturate logic unit providing higher flexibility. must select configurable positions compile time. These 16-bit positions located bits [21:6] rounding [43:28] saturation, shown Figure 5-20. Figure 5-20. Round Saturation Locations
User defined Positions (bit 43-28)
User defined Positions (bit 21-6)
symmetric saturation, position also used determine where saturated data located.
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rounding saturation function described above regular supported multiplication operations specified Table 5-2. However, accumulation type operations, following convention used. functionality round logic unit format Result RND[ B)], when used accumulation type operation. Likewise, functionality saturation logic unit format Result SAT[(A B)], when used accumulation type operation. both round saturation logic units used accumulation type operation, format Result SAT[RND[(A B)]]
Block Control Signals
Stratix block configured using static dynamic signals. block dynamic signals user configurable toggled time. This list dynamic signals shown Table block.
Table 5-9. Block Dynamic Signals (Part Signal Name
Function
Signed/unsigned control multipliers adders. signa "multiplicand" input dataa[17:0] each multiplier. signb "multiplier" input datab[17:0] each multiplier. signa signb signed-signed multiplication signa signb signed-unsigned multiplication signa signb unsigned-signed multiplication signa signb unsigned-unsigned multiplication Round control first stage round/saturation block. output_round rounding multiply output output_round normal multiply output
Count
signa signb
output_round
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Operational Mode Descriptions
Table 5-9. Block Dynamic Signals (Part Signal Name
chainout_round
Function
Round control second stage round/saturation block. chainout_round rounding multiply output chainout_round normal multiply output Saturation control first stage round/saturation block Qformat multiply. both rounding saturation enabled, saturation done rounded result. output_saturate saturation support output_saturate saturation support Saturation control second stage round/saturation block Q-format multiply. both rounding saturation's enabled, saturation done rounded result. chainout_saturate saturation support chainout_saturate saturation support Dynamically specifies whether accumulator value zero. accum_sload accumulation input from output registers accum_sload accumulation input zero Dynamically specifies whether chainout value zero. Dynamically specifies whether loopback value zero.
Count
output_saturate
chainout_saturate
accum_sload
zero_chainout zero_loopback rotate shift_right clock0 clock1 clock2 clock3 ena0 ena1 ena2 ena3 aclr0 aclr1 aclr2 aclr3
rotation rotation feature enabled shift_right shift right feature enabled
Total Signals Half-block DSP-block-wide clock signals
Input Pipeline Register enable signals
block-wide asynchronous clear signals (active low).
Total Count Full Block
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Blocks Stratix Devices
Application Examples
Example
finite impulse response filter common function used many systems perform spectral manipulations. basic form shown Equation 5-5. Equation 5-5. Finite Impulse Response Flter Equation
y(n)
this equation, x(n) input samples filter, c(k) filter coefficients, y(n) filtered output samples. Typically, coefficients change time most applications such Digital Down Converters (DDC). filters implemented many forms, most simple being tap-delay line approach. Stratix block implement various types filters very efficiently. form tap-delay line, input register stage block ability cascade input chained fashion 18-bit wide format. Unlike Stratix block, which built-in parallel input register scan paths, Stratix supports only built-in 18-bit parallel input register scan path data input. pair 18-bit input buses, input first 18-bit back registered again input second (lower) pair inputs. Refer Figure 5-21 details. input multiplier feeds from general routing. scan data 18-bit parallel form multiply 18-bit input from general routing each cycle. Normally filter, fixed data input (from general routing from cascade) constant that needs multiplied cascaded input. 18-bit mode, block enough input registers register general routing signals cascaded signal buses before multiplying them. This makes having eight taps 18-bit cascade mode possible. Each considered single multiplier. eight multiplier inputs full block cascaded parallel scan chain, eight-tap filter created, shown Figure 5-21. block concatenated have more than eight taps enabling option output parallel scan chain next (lower) block. Likewise, output previous (above) cascade chain used input current block. first (top) multiplier each half
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Application Examples
block will have option select 18-bit cascade chain input from regular routing from previous (above) cascade chain. Also, last cascaded chain each half block exit block routing cascade chain after last (fourth from top) input register output routing channel, bypassing both pipeline output registers. This concatenation allows user easily construct their desired filter length. Four-Multiplier Adder mode with inputs each multiplier being form chained cascaded input from previous (above) register. This very similar regular Four-Multiplier Adder with difference being that inputs from general routing. complete FIR, results individual Four-Multiplier Adder combined either tree chained cascade manner. Using external logic adders, very easily implement tree summation, shown Figure 5-21.
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Blocks Stratix Devices
Figure 5-21. Filter Using Tap-Delay Line Input Tree Summation Final Result
clock[3.0] ena[3.0] aclr[3.0]
signa signb output_round output_saturate overflow
dataa_0[
datab_0[17.0]
Pipeline Register Bank Output Register Bank
datab_1[17.0]
Round/Saturate
Final Summation Adder Soft Logic
Final Result
datab_2[17.0]
datab_3[17.0]
datab_4[17.0]
Pipeline Register Bank Output Register Bank
datab_5[17.0]
datab_6[17.0]
datab_7[17.0]
Altera Corporation 2007
Round/Saturate
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Application Examples
faster more efficient chained cascade summation, block implement chainout function cascade mode. This mode uses second-stage 44-bit adder current Four-Multiplier Adder half block adjacent half block Four-Multiplier Adder shown Figure 5-22. This scheme possible because each half block second-stage adders. second-stage adders used current Four-Multiplier Adder. second second-stage adder takes output first second-stage adder adjacent half block Four-Multiplier Adder result. Figure 5-22, adder that adds adjacent half block current Four-Multiplier Adder shown chainout adder clarity. This scheme used chain multiple blocks together. output chainout adder registered. registered chainout output feed lower adjacent block chainout summation feed general FPGA routing. chainout result zeroed applying logic dynamic zerochainout signal. zerochainout signal also registered.
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Blocks Stratix Devices
Figure 5-22. Filter using Tap-Delay Line Input Chained Cascade Summation Final Result
clock[3.0] ena[3.0] aclr[3.0] signa signb chainout_round chainout_saturate zero_chainout
chainout_sat_overflow
dataa_0[
datab_0[17.0]
Pipeline Register Bank Second Adder Register Bank
Zero
Round/Saturate
datab_1[17.0]
datab_2[17.0]
datab_3[17.0] Half-DSP Block
Delay Register
datab_4[17.0]
Pipeline Register Bank Second Adder Register Bank Output Register Bank Round/Saturate
datab_5[17.0]
Output Register Bank
result[
datab_6[17.0]
datab_7[17.0] Half-DSP Block
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Application Examples
When both input cascade chainout features, block uses 18-bit delay register boundary each half-DSP block from block-to-block synchronize input scan chain data with chainout data. half computes product chains output next block after output register. output register uses delay register delay cascade input clock cycle compensate latency bottom half. applications which system clock slower than speed block, multipliers time-multiplexed improve efficiency. This makes multi-channel semi-parallel structures possible. structure achieve this similar Figures 5-21 5-22. main difference that input cascade chain longer used each half-DSP block used Four-Multiplier Mode with independent inputs. Figure 5-23 shows example chained cascaded summation. most cases, only final stage with rounding saturation unit deployed.
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Blocks Stratix Devices
Figure 5-23. Semi-Parallel Structure Using Chained Cascaded Summation
clock[3.0] ena[3.0] aclr[3.0] signa signb chainout_round chainout_saturate zero_chainout
chainout_sat_overflow
dataa_0[
datab_0[
Pipeline Register Bank Second Adder Register Bank
Zero
dataa_1[ datab_1[
Round/Saturate
dataa_2[
datab_2[
dataa_3[ datab_3[
Half-DSP Block dataa_4[
datab_4[
Pipeline Register Bank Second Adder Register Bank Output Register Bank Round/Saturate
dataa_5[ datab_5[
Output Register Bank
result[
dataa_6[ datab_6[
dataa_7[ datab_7[
Half-DSP Block
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5-47 Stratix Device Handbook, Volume
Application Examples
Example
Fast Fourier Transform (FFT) very common function used convert samples time domain from frequency domain. fundamental building block butterfly. FFTs most efficient when operating complex samples. Stratix block form core complex butterfly very efficiently. Figure 5-24, radix-4 butterfly shown. Each butterfly requires three complex multipliers. This implemented Stratix using three half-DSP blocks assuming that data twiddle wordlengths bits fewer. Figure 5-24. Radix-4 Butterfly
G[k,0] X[k,0] ENGINE H[k,0] BFPU
G[k,1] X[k,1]
H[k,1] BFPU
G[k,2] X[k,2]
H[k,2] BFPU
G[k,3] X[k,3]
H[k,3] BFPU
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Blocks Stratix Devices
Software Support
Altera provides distinct methods implementing various modes block design: instantiation inference. Both methods following Quartus megafunctions:
lpm_mult altmult_add altmult_accum altfp_mult
instantiate megafunctions Quartus software block. Alternatively, with inference, create design synthesize using third-party synthesis tool (such LeonardoSpectrum, Synplify, Quartus Native Synthesis) that infers appropriate megafunction recognizing multipliers, multiplier adders, multiplier accumulators, shift functions. Using either method, Quartus software maps functionality blocks during compilation.
Refer Quartus Software Help instructions about using megafunctions MegaWizard Plug-In Manager. more information, refer Synthesis section volume Quartus Development Software Handbook. Stratix device blocks optimized support applications requiring high data throughput, such filters, filters, functions, encoders. These blocks flexible configured implement several operational modes suit particular application. built-in shift register chain, multipliers, adders/subtractors minimize amount external logic required implement these functions, resulting efficient resource utilization improved performance data throughput applications. Quartus software, used with LeonardoSpectrum Synplify software, provide complete easy-to-use flow implementing these multiplier functions blocks.
Conclusion
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Document Revision History
Document Revision History
Table 5-10 shows revision history this document.
Table 5-10. Document Revision History Date Document Version
2007 v1.1
Changes Made
Updated signal names Figures Added figures, Figure 5-12 Figure 5-13. Updated Figure 5-18. Updated Table Table 5-9. Deleted Table 5-10. Added "Double Multiplier" page 5-23. Clarification added "Shift Modes" page 5-34. Initial Release
Summary Changes
November 2006 v1.0
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