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Logic Array Blocks Adaptive Logic Modules Stratix Devices
SIII51002-1.1
This chapter describes features logic array block (LAB) Stratix® core fabric. logic array block composed basic building blocks known adaptive logic modules (ALMs) that configured implement logic functions, arithmetic functions, register functions. Each consists ALMs, carry chains, shared arithmetic chains, control signals, local interconnect, register chain connection lines. local interconnect transfers signals between ALMs same LAB. direct link interconnect allows drive into local interconnect left right neighbors. Register chain connections transfer output register adjacent register LAB. Quartus® Compiler places associated logic adjacent LABs, allowing local, shared arithmetic chain, register chain connections performance area efficiency. Figure shows Stratix structure interconnects.
Logic Array Blocks
Altera Corporation 2007
Logic Array Blocks
Figure 2-1. Stratix Structure
Interconnects Variable Speed Length
ALMs Direct link interconnect from adjacent block Direct link interconnect from adjacent block
Direct link interconnect adjacent block
Direct link interconnect adjacent block
Local Interconnect
MLAB Local Interconnect Driven from Either Side Columns LABs, from Above Rows
Column Interconnects Variable Speed Length
Stratix derivative called Memory (MLAB), which adds look-up table (LUT)-based SRAM capability shown Figure 2-2. MLAB supports maximum 640-bits simple dual-port static random access memory (SRAM). configure each MLAB either block, resulting configuration simple dual port SRAM block. MLAB blocks always co-exist pairs Stratix families. MLAB superset includes features. Figure shows overview MLAB topology.
MLAB described detail TriMatrix Embedded Memory Blocks Stratix Devices chapter volume Stratix Device Handbook.
Stratix Device Handbook, Volume
Altera Corporation 2007
Logic Array Blocks Adaptive Logic Modules Stratix Devices
Figure 2-2. Stratix MLAB Structure
LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM
Control Block
LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM LUT-based-64 Simple dual port SRAM
Control Block
MLAB
Note Figure 2-2:
MLAB regular configure dual-port SRAM, shown.
Interconnects
local interconnect drive ALMs same LAB. driven column interconnects outputs same LAB. Neighboring LABs/MLABs, blocks, M144K blocks, blocks from left right also drive LAB's local interconnect through direct link connection. direct link connection feature minimizes column interconnects, providing higher performance flexibility. Each drive ALMs through fast local direct link interconnects.
Altera Corporation 2007
Stratix Device Handbook, Volume
Logic Array Blocks
Figure shows direct link connection. Figure 2-3. Direct Link Connection
Direct link interconnect from left LAB, TriMatrix memory block, block, output Direct link interconnect from right LAB, TriMatrix memory block, block, output
ALMs
ALMs
Direct link interconnect left Local Interconnect
Direct link interconnect right
MLAB
Control Signals
Each contains dedicated logic driving control signals ALMs. control signals include three clocks, three clock enables, asynchronous clears, synchronous clear, synchronous load control signals. This gives maximum control signals time. Although generally synchronous load clear signals when implementing counters, also them with other functions. Each unique clock sources three clock enable signals, shown Figure 2-4. control block generate three clocks using clock sources three clock enable signals. Each LAB's clock clock enable signals linked. example, particular using labclk1 signal also uses labclkena1 signal. uses both rising falling edges clock, also uses LAB-wide clock signals. De-asserting clock enable signal turns corresponding LAB-wide clock.
Stratix Device Handbook, Volume
Altera Corporation 2007
Logic Array Blocks Adaptive Logic Modules Stratix Devices
clocks [5.0] local interconnect generate LAB-wide control signals. MultiTrackinterconnect's inherent skew allows clock control signal distribution addition data. Figure shows control signal generation circuit. Figure 2-4. LAB-Wide Control Signals
There unique clock signals LAB. Dedicated Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0 labclkena0 asyncload labpreset
labclk1 labclkena1
labclk2 labclkena2
syncload labclr0
labclr1 synclr
Adaptive Logic Modules
basic building block logic Stratix architecture, adaptive logic module (ALM), provides advanced features with efficient logic utilization. Each contains variety look-up table (LUT)-based resources that divided between combinational adaptive LUTs (ALUTs) registers. With eight inputs combinational ALUTs, implement various combinations functions. This adaptability allows completely backward-compatible with four-input architectures. also implement function inputs certain seven-input functions.
Altera Corporation 2007
Stratix Device Handbook, Volume
Adaptive Logic Modules
addition adaptive LUT-based resources, each contains programmable registers, dedicated full adders, carry chain, shared arithmetic chain, register chain. Through these dedicated resources, efficiently implement various arithmetic functions shift registers. Each drives types interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, direct link interconnects. Figure shows high-level block diagram Stratix while Figure shows detailed view connections ALM. Figure 2-5. High-Level Block Diagram Stratix
shared_arith_in carry_in reg_chain_in labclk general local routing
6-Input
Combinational/Memory ALUT0 dataf0 datae0 dataa datab adder0
general local routing
reg0
datac datad datae1 dataf1
6-Input
adder1
general local routing
reg1 general local routing Combinational/Memory ALUT1 reg_chain_out shared_arith_out carry_out
Stratix Device Handbook, Volume
Altera Corporation 2007
syncload aclr[1:0] shared_arith_in clk[2:0] sclr reg_chain_in shared_arith_out
dataf0 datae0
Altera Corporation 2007
dataa datab 4-INPUT datac
Figure 2-6. Stratix Details
3-INPUT
local interconnect row, column direct link routing row, column direct link routing
3-INPUT
datad
4-INPUT
3-INPUT
local interconnect row, column direct link routing row, column direct link routing
3-INPUT
datae1 dataf1
Logic Array Blocks Adaptive Logic Modules Stratix Devices
Stratix Device Handbook, Volume
shared_arith_out carry_out
Adaptive Logic Modules
contains programmable registers. Each register data, clock, clock enable, synchronous asynchronous clear, synchronous load/clear inputs. Global signals, general-purpose pins, internal logic drive register's clock clear control signals. Either general-purpose pins internal logic drive clock enable. combinational functions, register bypassed output drives directly outputs ALM. Each sets outputs that drive local, row, column routing resources. LUT, adder, register output drive these output drivers (refer Figure 2-6). each output drivers, outputs drive column, row, direct link routing connections, these outputs also drive local interconnect resources. This allows adder drive output while register drives another output. This feature, called register packing, improves device utilization because device register combinational logic unrelated functions. Another special packing mode allows register output feed back into same that register packed with fan-out LUT. This provides another mechanism improved fitting. also drive registered unregistered versions adder output.
Operating Modes
Stratix operate following modes:
Normal Extended Mode Arithmetic Shared Arithmetic LUT-Register
Each mode uses resources differently. each mode, eleven available inputs ALM-the eight data inputs from local interconnect, carry-in from previous LAB, shared arithmetic chain connection from previous LAB, register chain connection-are directed different destinations implement desired logic function. LAB-wide signals provide clock, asynchronous clear, synchronous clear, synchronous load, clock enable control register. These LAB-wide signals available modes. Refer "LAB Control Signals" page more information LAB-wide control signals.
Stratix Device Handbook, Volume
Altera Corporation 2007
Logic Array Blocks Adaptive Logic Modules Stratix Devices
Quartus software supported third-party synthesis tools, conjunction with parameterized functions such library parameterized modules (LPM) functions, automatically choose appropriate mode common functions such counters, adders, subtractors, arithmetic functions.
Normal Mode
normal mode suitable general logic applications combinational functions. this mode, eight data inputs from local interconnect inputs combinational logic. normal mode allows functions implemented Stratix ALM, implement single function inputs. support certain combinations completely independent functions various combinations functions that have common inputs. Figure shows supported combinations normal mode.
Altera Corporation 2007
Stratix Device Handbook, Volume
Adaptive Logic Modules
Figure 2-7. Normal Mode Note
dataf0 datae0 datac dataa datab datad datae1 dataf1
4-Input
combout0
dataf0 datae0 datac dataa datab
5-Input
combout0
4-Input
combout1 datad datae1 dataf1
5-Input
combout1
dataf0 datae0 datac dataa datab
5-Input
combout0
datad datae1 dataf1
dataf0 datae0 dataa datab datac datad
6-Input
combout0
3-Input
combout1
dataf0 datae0 datac dataa datab
5-Input
combout0
dataf0 datae0 dataa datab datac datad
6-Input
combout0
datad datae1 dataf1
4-Input
combout1
datae1 dataf1
6-Input
combout1
Note Figure 2-7:
Combinations functions with fewer inputs than those shown also supported. example, combinations functions with following number inputs supported:
normal mode provides complete backward compatibility with four-input architectures. packing five-input functions into ALM, functions must have least common inputs. common inputs dataa datab. combination four-input function with five-input function requires common input (either dataa datab).
2-10 Stratix Device Handbook, Volume
Altera Corporation 2007
Logic Array Blocks Adaptive Logic Modules Stratix Devices
case implementing six-input functions ALM, four inputs must shared combinational function must same. example, crossbar switch (two 4-to-1 multiplexers with common inputs unique select lines) implemented ALM, shown Figure 2-8. shared inputs dataa, datab, datac, datad, while unique select lines datae0 dataf0 function0, datae1 dataf1 function1. This crossbar switch consumes four LUTs four-input LUT-based architecture. Figure 2-8. Crossbar Switch Example
Crossbar Switch sel0[1.0] inputa inputb inputc inputd out1 sel1[1.0] datae1 dataf1 Six-Input (Function1) out0 dataf0 datae0 dataa datab datac datad Implementation
Six-Input (Function0)
combout0
combout1
sparsely used device, functions that could placed into implemented separate ALMs Quartus software order achieve best possible performance. device begins fill Quartus software automatically utilizes full potential Stratix ALM. Quartus Compiler automatically searches functions common inputs completely independent functions placed into make efficient device resources. addition, manually control resource usage setting location assignments. six-input function implemented utilizing inputs dataa, datab, datac, datad, either datae0 dataf0 datae1 dataf1. datae0 dataf0 utilized, output driven register0, and/or register0 bypassed data drives interconnect using output drivers (refer Figure 2-9). datae1 dataf1 utilized, output drives register1 and/or bypasses register1 drives interconnect using bottom output drivers. Quartus Compiler automatically selects inputs LUT. ALMs normal mode support register packing.
Altera Corporation 2007
2-11 Stratix Device Handbook, Volume
Adaptive Logic Modules
Figure 2-9. Input Function Normal Mode Note
dataf0 datae0 dataa datab datac datad datae1 dataf1 labclk These inputs available register packing. general local routing 6-Input
general local routing
reg0
general local routing
reg1
Notes Figure 2-9:
datae1 dataf1 used inputs six-input function, then datae0 dataf0 available register packing. dataf1 input available register packing only six-input function un-registered.
Extended Mode
extended mode implement specific seven-input functions. must 2-to-1 multiplexer arbitrary five-input functions sharing four inputs. Figure 2-10 shows template supported seven-input functions utilizing extended mode. this mode, seven-input function unregistered, unused eighth input available register packing. Functions that into template shown Figure 2-10 occur naturally designs. These functions often appear designs "if-else" statements Verilog VHDL code.
2-12 Stratix Device Handbook, Volume
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Logic Array Blocks Adaptive Logic Modules Stratix Devices
Figure 2-10. Template Supported Seven-Input Functions Extended Mode
datae0 datac dataa datab datad dataf0 5-Input combout0
general local routing general local routing
5-Input datae1 dataf1 This input available register packing.
reg0
Note Figure 2-10:
seven-input function unregistered, unused eighth input available register packing. second register, reg1, available.
Arithmetic Mode
arithmetic mode ideal implementing adders, counters, accumulators, wide parity functions, comparators. arithmetic mode uses sets four-input LUTs along with dedicated full adders. dedicated adders allow LUTs available perform pre-adder logic; therefore, each adder output four-input functions. four LUTs share dataa datab inputs. shown Figure 2-11, carry-in signal feeds adder0, carry-out from adder0 feeds carry-in adder1. carry-out from adder1 drives adder0 next LAB. ALMs arithmetic mode drive registered and/or unregistered versions adder outputs.
Altera Corporation 2007
2-13 Stratix Device Handbook, Volume
Adaptive Logic Modules
Figure 2-11. Arithmetic Mode
carry_in datae0 4-Input
adder0 general local routing general local routing
dataf0 datac datab dataa
4-Input
reg0
datad datae1
4-Input
adder1 general local routing
general local routing
4-Input dataf1
reg1
carry_out
While operating arithmetic mode, support simultaneous adder's carry output along with combinational logic outputs. this operation, adder output ignored. This usage adder with combinational logic output provides resource savings functions that this ability. example such functionality conditional operation, such shown Figure 2-12.
2-14 Stratix Device Handbook, Volume
Altera Corporation 2007
Logic Array Blocks Adaptive Logic Modules Stratix Devices
Figure 2-12. Conditional Operation Example
Adder output used. X[0] Y[0] syncdata X[1] Y[1] Comb Adder Logic X[1]
Comb Adder Logic
X[0] R[0]
general local routing
reg0 syncload
R[1]
general local routing
reg1 Carry Chain X[2] Y[2] Comb Adder Logic syncload
X[2]
R[2]
general local routing
reg0 syncload Comb Adder Logic carry_out local routing then LAB-wide syncload
equation this example implement this function, adder used subtract from less than carry_out signal carry_out signal adder where drives local interconnect. then feeds LAB-wide syncload signal. When asserted, syncload selects syncdata input. this case, data drives syncdata inputs registers. greater than equal syncload signal de-asserted drives data port registers. arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, synchronous load. local interconnect data inputs generate clock enable, counter enable, synchronous up/down,
Altera Corporation 2007
2-15 Stratix Device Handbook, Volume
Adaptive Logic Modules
add/subtract control signals. These control signals good candidates inputs that shared between four LUTs ALM. synchronous clear synchronous load options LAB-wide signals that affect registers LAB. These signals also individually disabled enabled register. Quartus software automatically places registers that used counter into other LABs. Carry Chain carry chain provides fast carry function between dedicated adders arithmetic shared arithmetic mode. two-bit carry select feature Stratix devices halves propagation delay carry chains within ALM. Carry chains begin either first fifth LAB. final carry-out signal routed ALM, where local, row, column interconnects. Quartus Compiler automatically creates carry chain logic during design processing, create manually during design entry. Parameterized functions such functions automatically take advantage carry chains appropriate functions. Quartus Compiler creates carry chains longer than ALMs arithmetic shared arithmetic mode) linking LABs together automatically. enhanced fitting, long carry chain runs vertically allowing fast horizontal connections TriMatrixmemory blocks. carry chain continue full column. avoid routing congestion small area device when high fan-in arithmetic function implemented, support carry chains that only utilize either half bottom half before connecting next LAB. This leaves other half ALMs available implementing narrower fan-in functions normal mode. Carry chains that five ALMs first carry into half ALMs next within column. Carry chains that bottom five ALMs first carry into bottom half ALMs next within column. every alternate column, half bypassed; other MLAB columns, bottom half bypassed. Refer "ALM Interconnects" page 2-22 more information carry chain interconnect.
2-16 Stratix Device Handbook, Volume
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Logic Array Blocks Adaptive Logic Modules Stratix Devices
Shared Arithmetic Mode
shared arithmetic mode, implement three-input within ALM. this mode, configured with four-input LUTs. Each either computes three inputs carry three inputs. output carry computation next adder (either adder1 same adder0 next LAB) dedicated connection called shared arithmetic chain. This shared arithmetic chain significantly improve performance adder tree reducing number summation stages required implement adder tree. Figure 2-13 shows using this feature. Figure 2-13. Shared Arithmetic Mode
shared_arith_in carry_in labclk 4-Input
general local routing general local routing
datae0 datac datab dataa
4-Input
reg0
datad datae1
4-Input
general local routing general local routing
4-Input
reg1
carry_out shared_arith_out
find adder trees many different applications. example, summation partial products logic-based multiplier implemented tree structure. Another example correlator function that large adder tree filtered data samples given time frame recover de-spread data that transmitted utilizing spread spectrum technology.
Altera Corporation 2007
2-17 Stratix Device Handbook, Volume
Adaptive Logic Modules
example three-bit operation utilizing shared arithmetic mode shown Figure 2-14. partial (S[3.0]) partial carry (C[3.0]) obtained using LUTs, while result (R[3.0]) computed using dedicated adders. Figure 2-14. Example 3-Bit Utilizing Shared Arithmetic Mode
shared_arith_in carry_in Implementation
3-Bit Example
stage implemented LUTs.
3-Input
3-Input
stage implemented
3-Input
3-Input 3-Input 3-Input
Binary
Decimal Equivalents
1110 0100 +1101 0111 +1100 11111
3-Input
3-Input
Shared Arithmetic Chain shared arithmetic chain available enhanced arithmetic mode allows implement three-input add. This significantly reduces resources necessary implement large adder trees correlator functions. shared arithmetic chains begin either first sixth LAB. Quartus Compiler creates shared arithmetic chains longer than ALMs arithmetic shared arithmetic mode) linking
2-18 Stratix Device Handbook, Volume
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Logic Array Blocks Adaptive Logic Modules Stratix Devices
LABs together automatically. enhanced fitting, long shared arithmetic chain runs vertically allowing fast horizontal connections TriMatrix memory blocks. shared arithmetic chain continue full column. Similar carry chains, bottom half shared arithmetic chains alternate columns bypassed. This capability allows shared arithmetic chain cascade through half ALMs while leaving other half available narrower fan-in functionality. Every other column top-half bypassable, while other columns bottom-half bypassable. Refer "ALM Interconnects" page 2-22 more information shared arithmetic chain interconnect.
LUT-Register Mode
LUT-Register mode allows third register capability within ALM. internal feedback loops allow combinational ALUT1 implement master latch combinational ALUT0 implement slave latch needed third register. register shares clock, clock enable, asynchronous clear sources with dedicated register. Figure 2-15 shows register constructed using combinational blocks within ALM. Figure 2-16 shows LUT-Register mode. Figure 2-15. Register from Combinational Blocks
aclr 4-input sumout regout combout
sumout datain(datac) sclr 5-input combout
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2-19 Stratix Device Handbook, Volume
Adaptive Logic Modules
Figure 2-16. LUT-Register Mode with 3-Register Capability
[2:0] aclr [1:0] reg_chain_in
datain lelocal aclr aclr sclr regout latchout sdata leout regout datain
leout
lelocal aclr datain leout regout
sdata
leout
reg_chain_out
Register Chain
addition general routing outputs, ALMs have register chain outputs. register chain routing allows registers same cascaded together. register chain interconnect allows LUTs single combinational function registers used unrelated shift register implementation. These resources speed connections between ALMs while saving local interconnect resources (refer Figure 2-17). Quartus Compiler automatically takes advantage these resources improve utilization performance.
2-20 Stratix Device Handbook, Volume
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Logic Array Blocks Adaptive Logic Modules Stratix Devices
Figure 2-17. Register Chain within Note
From previous within reg_chain_in labclk general local routing adder0
general local routing
reg0 Combinational Logic adder1
general local routing
reg1 general local routing
general local routing adder0
general local routing
reg0 Combinational Logic adder1
general local routing
reg1 general local routing
reg_chain_out next within
Note Figure 2-17:
combinational adder logic implement unrelated, un-registered function.
Refer "ALM Interconnects" page 2-22 more information register chain interconnect.
Altera Corporation 2007
2-21 Stratix Device Handbook, Volume
Adaptive Logic Modules
Interconnects
There three dedicated paths between ALMs: Register Cascade, Carry-chain, Shared Arithmetic chain. Stratix devices include enhanced interconnect structure LABs routing shared arithmetic chains carry chains efficient arithmetic functions. register chain connection allows register output connect directly register input next fast shift registers. These ALM-to-ALM connections bypass local interconnect. Quartus Compiler automatically takes advantage these resources improve utilization performance. Figure 2-18 shows shared arithmetic chain, carry chain, register chain interconnects. Figure 2-18. Shared Arithmetic Chain, Carry Chain, Register Chain Interconnects
Local interconnect routing among ALMs Carry chain shared arithmetic chain routing adjacent
Register chain routing adjacent ALM's register input
Local interconnect
Refer MultiTrack Interconnect Stratix Devices chapter volume Stratix Device Handbook information routing between LABs.
2-22 Stratix Device Handbook, Volume
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Logic Array Blocks Adaptive Logic Modules Stratix Devices
Clear Preset Logic Control
LAB-wide signals control logic register's clear signal. directly supports asynchronous clear function. achieve register preset through Quartus software's NOT-gate push-back logic option. Each supports clears. Stratix devices provide device-wide reset (DEV_CLRn) that resets registers device. option before compilation Quartus software controls this pin. This device-wide reset overrides other control signals.
Power Management Techniques
following techniques used manage static dynamic power consumption within LAB:
Stratix low-voltage devices ordering code suffix) offer selectable core voltage reduce both power. save power, Quartus forces adder inputs when adders use. Stratix LABs operate high-performance mode low-power mode. Quartus software automatically chooses appropriate mode based design optimize speed leakage trade-offs. Clocks represent significant portion dynamic power consumption their high switching activity long paths. clock that distributes clock signal registers within significant contributor overall clock power consumption. Each LAB's clock clock enable signal linked. example, combinational ALUT register particular using labclk1 signal also uses labclkena1 signal. disable LAB-wide clock power consumption without disabling entire clock tree, LAB-wide clock enable gate LAB-wide clock. Quartus software automatically promotes register-level clock enable signals LAB-level. registers within that share common clock clock enable controlled shared gated clock. take advantage these clock enables, clock enable construct your code registered logic.
Refer Power Optimization section Quartus Handbook details implementation. Refer Programmable Power Temperature Sensing Diode Stratix Devices chapter volume Stratix Device Handbook detailed information Stratix programmable power capabilities.
Altera Corporation 2007
2-23 Stratix Device Handbook, Volume
Conclusion
Conclusion
Logic array block adaptive logic modules basic building blocks Stratix device. these configure logic functions, arithmetic functions, register functions. provides advanced features with efficient logic utilization completely backward-compatible.
Document Revision History
Table shows revision history this document.
Table 2-1. Document Revision History Date Document Version
2007 v1.1
Changes Made
Minor formatting changes, updated Figure include missing connection.
Summary Changes
November 2006 Initial Release v1.0
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SIII51002-1.1 This chapter describes features logic array block (

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