SST25VF512 SST25VF512512Kb Serial Peripheral Interface (SPI) flas
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Kbit Serial Flash
SST25VF512
SST25VF512512Kb Serial Peripheral Interface (SPI) flash memory
FEATURES:
Single 2.7-3.6V Read Write Operations Serial Interface Architecture Compatible: Mode Mode Clock Frequency Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Read Current: (typical) Standby Current: (typical) Flexible Erase Capability Uniform KByte sectors Uniform KByte overlay blocks Fast Erase Byte-Program: Chip-Erase Time: (typical) Sector- Block-Erase Time: (typical) Byte-Program Time: (typical) Auto Address Increment (AAI) Programming Decrease total chip programming time over Byte-Program operations End-of-Write Detection Software Status Hold (HOLD#) Suspends serial sequence memory without deselecting device Write Protection (WP#) Enables/Disables Lock-Down function status register Software Write Protection Write protection through Block-Protection bits status register Packages Available 8-lead SOIC (4.9mm 6mm) 8-contact WSON non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST's serial flash family features four-wire, SPI-compatible interface that allows pin-count package occupying less board space ultimately lowering total system costs. SST25VF512 serial flash memory manufactured with SST's proprietary, high-performance CMOS SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST25VF512 device significantly improves performance, while lowering power consumption. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash memory technologies. SST25VF512 device operates with single 2.7-3.6V power supply. SST25VF512 device offered both 8-lead SOIC 8-contact WSON packages. Figure assignments.
©2005 Silicon Storage Technology, Inc. S71192-08-000 11/05
logo SuperFlash registered Trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Serial Flash SST25VF512
FUNCTIONAL BLOCK DIAGRAM
Address Buffers Latches
Decoder
SuperFlash Memory
Decoder
Control Logic
Buffers Data Latches
Serial Interface
1192 B1.5
HOLD#
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
DESCRIPTION
HOLD#
HOLD#
View
1192 08-soic P1.4
View
1192 08-wson P1a.6
8-LEAD SOIC
8-CONTACT WSON
FIGURE ASSIGNMENTS TABLE DESCRIPTION
Symbol Name Serial Clock Functions provide timing serial interface. Commands, addresses, input data latched rising edge clock input, while output data shifted falling edge clock input. transfer commands, addresses, data serially into device. Inputs latched rising edge serial clock. transfer data serially device. Data shifted falling edge serial clock. device enabled high transition CE#. must remain duration command sequence. Write Protect (WP#) used enable/disable status register. temporarily stop serial communication with flash memory without resetting device. provide power supply (2.7-3.6V).
T1.7 1192
HOLD#
Serial Data Input Serial Data Output Chip Enable Write Protect Hold Power Supply Ground
MODE MODE MODE
MODE
DON'T CARE
1192 F34.6
HIGH IMPEDANCE
FIGURE PROTOCOL
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
PRODUCT IDENTIFICATION
TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST25VF512 00001H
T2.5 1192
DEVICE OPERATION
SST25VF512 accessed through (Serial Peripheral Interface) compatible protocol. consist four control lines; Chip Enable (CE#) used select device, data accessed through Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK). SST25VF512 supports both Mode (0,0) Mode (1,1) operations. difference between modes, shown Figure state signal when master Stand-by mode data being transferred. signal Mode signal high Mode both modes, Serial Data (SI) sampled rising edge clock signal Serial Data Output (SO) driven after falling edge clock signal.
Data
00000H
MEMORY ORGANIZATION
SST25VF512 SuperFlash memory array organized KByte sectors with KByte overlay blocks.
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Hold Operation
HOLD# used pause serial sequence underway with flash memory without resetting clocking sequence. activate HOLD# mode, must active state. HOLD# mode begins when active state coincides with falling edge HOLD# signal. HOLD mode ends when HOLD# signal's rising edge coincides with active state. falling edge HOLD# signal does coincide with active state, then device enters Hold mode when next reaches active state. Similarly, rising edge HOLD# signal does coincide with active state, then device exits Hold mode when next reaches active state. Figure Hold Condition waveform. Once device enters Hold mode, will highimpedance state while VIH. driven active high during Hold condition, resets internal logic device. long HOLD# signal low, memory remains Hold condition. resume communication with device, HOLD# must driven active high, must driven active low. Figure Hold timing.
HOLD# Active Hold Active Hold Active
1192 F44.0
FIGURE HOLD CONDITION WAVEFORM
Write Protection
SST25VF512 provides software Write protection. Write Protect (WP#) enables disables lock-down function status register. Block-Protection bits (BP1, BP0, BPL) status register provide Write protection memory array status register. Table Block-Protection description. Write Protect (WP#) Write Protect (WP#) enables lock-down function (bit status register. When driven low, execution Write-Status-Register (WRSR) instruction determined value (see Table When high, lock-down function disabled. TABLE CONDITIONS EXECUTE WRITE-STATUSREGISTER (WRSR) INSTRUCTION
Execute WRSR Instruction Allowed Allowed Allowed
T3.0 1192
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Status Register
software status register provides status whether flash memory array available Read Write operation, whether device Write enabled, state memory Write protection. During internal Erase Program operation, status register read only determine completion operation progress. Table describes function each software status register. Busy Busy determines whether there internal Erase Program operation progress. Busy indicates device busy with operation progress. indicates device ready next valid operation. Write Enable Latch (WEL) Write-Enable-Latch indicates status internal memory Write Enable Latch. Write-Enable-Latch "1", indicates device Write enabled. (reset), indicates device Write enabled does accept memory Write (Program/ Erase) commands. Write-Enable-Latch automatically reset under following conditions: Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming reached highest memory address Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion
Block Protection (BP1, BP0) Block-Protection (BP1, BP0) bits define size memory area, defined Table software protected against memory Write (Program Erase) operations. Write-Status-Register (WRSR) instruction used program bits long high Block-Protect-Lock (BPL) Chip-Erase only executed Block-Protection bits both After power-up, Block Protection Lock-Down (BPL) driven (VIL), enables Block-ProtectionLock-Down (BPL) bit. When prevents further alteration BPL, BP1, bits. When driven high (VIH), effect value "Don't Care". After power-up, reset TABLE SOFTWARE STATUS REGISTER BLOCK PROTECTION1
Status Register Protection Level (1/4 Memory Array)2 (1/2 Memory Array) (Full Memory Array) Protected Memory Area None 0C000H-0FFFFH 08000H-0FFFFH 00000H-0FFFFH
T4.5 1192
Default power-up `11'. Protection Level (1/4 Memory Array) applies ByteProgram, Sector-Erase, Chip-Erase operations. does apply Block-Erase operations.
TABLE SOFTWARE STATUS REGISTER
Name BUSY Function Internal Write operation progress internal Write operation progress Device memory Write enabled Device memory Write enabled Indicate current level block write protection (See Table Indicate current level block write protection (See Table Reserved future Auto Address Increment Programming status programming mode Byte-Program mode BP1, read-only bits BP1, read/writable Default Power-up Read/Write
T5.0 1192
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet Auto Address Increment (AAI) Auto Address Increment Programming-Status provides status whether device programming mode Byte-Program mode. default power Byte-Program mode. (WREN) instruction must executed first. complete list instructions provided Table instructions synchronized high transition CE#. Inputs will accepted rising edge starting with most significant bit. must driven before instruction entered must driven high after last instruction been shifted (except Read, Read-ID Read-Status-Register instructions). high transition CE#, before receiving last instruction cycle, will terminate instruction progress return device standby mode. Instruction commands Code), addresses, data input from most significant (MSB) first.
Instructions
Instructions used Read, Write (Erase Program), configure SST25VF512. instruction cycles bits each commands Code), data, addresses. Prior executing Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Chip-Erase instructions, Write-Enable TABLE DEVICE OPERATION INSTRUCTIONS1
Cycle2 Cycle Type/Operation3,4 Read Sector-Erase5,6 Block-Erase5,7 Chip-Erase6 Byte-Program6 Auto Address Increment (AAI) Program6,8 Read-Status-Register (RDSR) Enable-Write-Status-Register (EWSR)10 Write-Status-Register Write-Enable (WREN) Write-Disable (WRDI) Read-ID (WRSR)10 SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 Data
SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note9 Hi-Z A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8
SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note9 Hi-Z
SOUT DOUT Hi-Z Hi-Z Note9 DOUT12
T6.18 1192
Addr11
Most Significant Address SST25VF512 Address bits above most significant each density cycle eight clock periods. Operation: Serial SOUT Serial Dummy Input Cycles (VIL VIH); Non-Applicable Cycles (Cycles necessary) Sector addresses: AMS-A12, remaining addresses Prior Byte-Program, AAI-Program, Sector-Erase, Block-Erase, Chip-Erase operation, Write-Enable (WREN) instruction must executed. Block addresses for: AMS-A15, remaining addresses continue programming next sequential address location, enter 8-bit command, AFH, followed data programmed. Read-Status-Register continuous with ongoing clock cycles until terminated high transition CE#. Enable-Write-Status-Register (EWSR) instruction Write-Status-Register (WRSR) instruction must work conjunction each other. WRSR instruction must executed immediately (very next cycle) after EWSR instruction make both instructions effective. Manufacturer's read with A0=0, Device read with A0=1. other address bits 00H. Manufacturer's Device output stream continuous until terminated high transition Device SST25VF512
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet Read Read instruction outputs data starting from specified address location. data output stream continuous through addresses until terminated high transition CE#. internal address pointer will automatically increment until highest memory address reached. Once highest memory address reached, address pointer will automatically increment beginning (wrap-around) address space, i.e. Mbit density, once data from address location 7FFFFH been read, next output will from address location 00000H. Read instruction initiated executing 8-bit command, 03H, followed address bits [A23-A0]. must remain active duration Read cycle. Figure Read sequence.
MODE
MODE
ADD. HIGH IMPEDANCE
ADD.
ADD. DOUT
1192 F10.11
DOUT
DOUT
DOUT
DOUT
FIGURE READ SEQUENCE
Byte-Program Byte-Program instruction programs bits selected byte desired data. selected byte must erased state (FFH) when initiating Program operation. Byte-Program instruction applied protected memory area will ignored. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration Byte-Program instruction. ByteProgram instruction initiated executing 8-bit command, 02H, followed address bits [A23-A0]. Following address, data input order from (bit (bit must driven high before instruction executed. user poll Busy software status register wait completion internal self-timed Byte-Program operation. Figure Byte-Program sequence.
MODE
MODE
ADD.
ADD.
ADD.
HIGH IMPEDANCE
1192 F08.11
FIGURE BYTE-PROGRAM SEQUENCE
©2005 Silicon Storage Technology, Inc. S71192-08-000 11/05
Kbit Serial Flash SST25VF512
Data Sheet Auto Address Increment (AAI) Program program instruction allows multiple bytes data programmed without re-issuing next sequential address location. This feature decreases total programming time when entire memory array programmed. program instruction pointing protected memory area will ignored. selected address range must erased state (FFH) when initiating program instruction. Prior write operation, Write-Enable (WREN) instruction must executed. program instruction initiated executing 8-bit command, AFH, followed address bits [A23-A0]. Following addresses, data input sequentially from (bit (bit must driven high before program instruction executed. user must poll BUSY software status register wait completion each internal self-timed Byte-Program cycle. Once device completes programming byte, next sequential address program, enter 8-bit command, AFH, followed data programmed. When last desired byte been programmed, execute Write-Disable (WRDI) instruction, 04H, terminate AAI. After execution WRDI command, user must poll Status register ensure device completes programming. Figure programming sequence. There wrap mode during programming; once highest unprotected memory address reached, device will exit operation reset Write-EnableLatch (WEL
MODE
MODE
A[23:16] A[15:8]
A[7:0]
Data Byte
Data Byte
Last Data Byte Write Disable (WRDI) Instruction terminate Operation Read Status Register (RDSR) Instruction verify Operation DOUT
1192 F39.10
FIGURE AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet Sector-Erase Sector-Erase instruction clears bits selected KByte sector FFH. Sector-Erase instruction applied protected memory area will ignored. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration command sequence. Sector-Erase instruction initiated executing 8-bit command, 20H, followed address bits [A23-A0]. Address bits [AMS-A12] (AMS Most Significant address) used determine sector address (SAX), remaining address bits VIH. must driven high before instruction executed. user poll Busy software status register wait completion internal selftimed Sector-Erase cycle. Figure SectorErase sequence.
MODE
MODE
ADD.
ADD.
ADD.
HIGH IMPEDANCE
1192 F06.12
FIGURE SECTOR-ERASE SEQUENCE
Block-Erase Block-Erase instruction clears bits selected KByte block FFH. Block-Erase instruction applied protected memory area will ignored. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration command sequence. Block-Erase instruction initiated executing 8-bit command, 52H, followed address bits [A23-A0]. Address bits [AMS-A15] (AMS Most significant address) used determine block address (BAX), remaining address bits VIH. must driven high before instruction executed. user poll Busy software status register wait completion internal self-timed BlockErase cycle. Figure Block-Erase sequence.
MODE
MODE
ADD.
ADD.
ADD.
HIGH IMPEDANCE
1192 F28.11
FIGURE BLOCK-ERASE SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet Chip-Erase Chip-Erase instruction clears bits device FFH. Chip-Erase instruction will ignored memory area protected. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration Chip-Erase instruction sequence. Chip-Erase instruction initiated executing 8-bit command, 60H. must driven high before instruction executed. user poll Busy software status register wait completion internal self-timed Chip-Erase cycle. Figure Chip-Erase sequence.
MODE
MODE
HIGH IMPEDANCE
1192 F07.12
FIGURE CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR) Read-Status-Register (RDSR) instruction allows reading status register. status register read time even during Write (Program/Erase) operation. When Write operation progress, Busy checked before sending commands assure that commands properly received device. must driven before RDSR instruction entered remain until status data read. ReadStatus-Register continuous with ongoing clock cycles until terminated high transition CE#. Figure RDSR instruction sequence.
MODE
MODE
HIGH IMPEDANCE
Status Register
1192 F37.7
FIGURE READ-STATUS-REGISTER (RDSR) SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet Write-Enable (WREN) Write-Enable (WREN) instruction sets WriteEnable-Latch allowing Write operations occur. WREN instruction must executed prior Write (Program/Erase) operation. must driven high before WREN instruction executed.
MODE
MODE
HIGH IMPEDANCE
1192 F35.6
FIGURE WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI) Write-Disable (WRDI) instruction resets WriteEnable-Latch disabling Write operations from occurring. must driven high before WRDI instruction executed.
MODE
MODE
HIGH IMPEDANCE
1192 F36.6
FIGURE WRITE DISABLE (WRDI) SEQUENCE
Enable-Write-Status-Register (EWSR) Enable-Write-Status-Register (EWSR) instruction arms Write-Status-Register (WRSR) instruction opens status register alteration. Enable-WriteStatus-Register instruction does have effect will wasted, followed immediately Write©2005 Silicon Storage Technology, Inc.
Status-Register (WRSR) instruction. must driven before EWSR instruction entered must driven high before EWSR instruction executed.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet Write-Status-Register (WRSR) Write-Status-Register instruction works conjunction with Enable-Write-Status-Register (EWSR) instruction write values BP1, BP0, bits status register. Write-Status-Register instruction must executed immediately after execution EnableWrite-Status-Register instruction (very next instruction cycle). This two-step instruction sequence EWSR instruction followed WRSR instruction works like (software data protection) command structure which prevents accidental alteration status register values. Write-Status-Register instruction will ignored when "1". When low, only from lockdown status register, cannot reset from "0". When high, lock-down function disabled BPL, BP0, bits status register changed. long driven high (VIH) prior low-to-high transition WRSR instruction, BP0, BP1, status register altered WRSR instruction. this case, single WRSR instruction lock down status register well altering same time. Table summary description functions. must driven before command sequence WRSR instruction entered driven high before WRSR instruction executed. Figure EWSR WRSR instruction sequences.
MODE
MODE MODE
MODE
HIGH IMPEDANCE
STATUS REGISTER
1192 F38.9
FIGURE ENABLE-WRITE-STATUS-REGISTER (EWSR) WRITE-STATUS-REGISTER (WRSR) SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet Read-ID Read-ID instruction identifies device SST25VF512 manufacturer SST. device information read from executing 8-bit command, ABH, followed address bits [A23-A0]. Following Read-ID instruction, manufacturer's located address 00000H device located address 00001H. Once device Read-ID mode, manufacturer's device output data toggles between address 00000H 00001H until terminated high transition CE#.
MODE
MODE
ADD1
HIGH IMPEDANCE
Device
Device
HIGH IMPEDANCE
Note: manufacturer's device output stream continuous until terminated high transition CE#. will output manfacturer's first will output device first before toggling between two.
1192 F19.15
FIGURE READ-ID SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature 260°C seconds Output Short Circuit Current1
Output shorted more than second. more than output shorted time.
OPERATING RANGE:
Range Commercial Ambient Temp +70°C 2.7-3.6V
CONDITIONS TEST
Input Rise/Fall Time Output Load Figures
TABLE OPERATING CHARACTERISTICS 2.7-3.6V
Limits Symbol IDDR IDDW Parameter Read Current Program Erase Current Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage VDD-0.2 Units Test Conditions CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open CE#=VDD CE#=VDD, VIN=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T7.9 1192
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Read Operation Write Operation
Minimum
Units
T8.0 1192
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE 25°C, Mhz, other pins open)
Parameter COUT1
Description Output Capacitance Input Capacitance
Test Condition VOUT
Maximum
T9.0 1192
This parameter measured only initial qualification after design process change that could affect this parameter.
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet TABLE RELIABILITY CHARACTERISTICS
Symbol NEND1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T10.1 1192
ILTH1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE OPERATING CHARACTERISTICS 2.7-3.6V
Limits Symbol FCLK TSCKH TSCKL TSCKR TSCKF TCES1 TCEH1 TCHS1 TCHH TCPH TCHZ TCLZ THLS THHS THLH THHH TSCE
Relative SCK.
Parameter Serial Clock Frequency Serial Clock High Time Serial Clock Time Serial Clock Rise Time Serial Clock Fall Time Active Setup Time Active Hold Time Active Setup Time Active Hold Time High Time High High-Z Output Low-Z Output Data Setup Time Data Hold Time HOLD# Setup Time HOLD# High Setup Time HOLD# Hold Time HOLD# High Hold Time HOLD# High-Z Output HOLD# High Low-Z Output Output Hold from Change Output Valid from Sector-Erase Block-Erase Chip-Erase Byte-Program
Units
T11.15 1192
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
TCPH TCHH TCES TSCKR TSCKF TCEH TCHS
HIGH-Z
HIGH-Z
1192 F41.7
FIGURE SERIAL INPUT TIMING DIAGRAM
TSCKH TCLZ
1192 F42.6
TSCKL
TCHZ
FIGURE SERIAL OUTPUT TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
THHH THLH THLS THHS
HOLD#
1192 F43.1
FIGURE HOLD TIMING DIAGRAM
Chip selection allowed. commands rejected device.
TPU-READ TPU-WRITE Device fully accessible
Time
1192 F45.0
FIGURE POWER-UP TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
1192 F02.1
test inputs driven VIHT (0.9VDD) logic VILT (0.1VDD) logic "0". Measurement reference points inputs outputs (0.7VDD) (0.3VDD). Input rise fall times (10% 90%)
Note: VHIGH Test VLOW Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
1192 F03.0
FIGURE TEST LOAD EXAMPLE
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 Environmental Attribute non-Pb Package Modifier leads contacts Package Type SOIC WSON Temperature Range Commercial +70°C Minimum Endurance 10,000 cycles Operating Frequency Device Density Kbit Voltage 2.7-3.6V Product Series Serial Peripheral Interface flash memory
SST25VFXXX
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
Valid combinations SST25VF512 SST25VF512-20-4C-SA SST25VF512-20-4C-SAE SST25VF512-20-4C-QA SST25VF512-20-4C-QAE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
PACKAGING DIAGRAMS
Identifier
VIEW
SIDE VIEW
places
1.27
0.51 0.33
VIEW
0.25 0.10 1.75 1.35 0.25 0.19 1.27 0.40 places
4.00 3.80 6.20 5.80
Note: Complies with JEDEC publication MS-012 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends 0.25 between leads.
08-soic-5x6-SA-8
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) BODY WIDTH (4.9MM 6MM) PACKAGE CODE:
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
VIEW
SIDE VIEW
0.25 0.19
BOTTOM VIEW
Corner
1.27
5.00 0.10 0.076
4.00 0.10 3.40 0.10
0.48 0.35
6.00 0.10 0.80 0.70
0.05
0.70 0.50
CROSS SECTION
0.80 0.70
Note: linear dimensions millimeters (max/min).
8-wson-6x5-QA-8
8-CONTACT VERY-VERY-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE CODE:
©2005 Silicon Storage Technology, Inc.
S71192-08-000
11/05
Kbit Serial Flash SST25VF512
Data Sheet TABLE REVISION HISTORY
Number Description Date 2001 2002
Initial release Remove Cycles Read Write operations. Swapped Ready#/Busy logic. busy, busy) Change description Added protocol timing diagram. Updated timing diagrams Remove Reset# description. HOLD# description. Updated Transient Voltage parameter. Auto Address Increment (AAI) feature description. Global layout changes. Updated Instruction descriptions. Removed commands Read Moved Mbit Mbit parts data sheet S71231 Moved Mbit part data sheet S71233 Changed timing parameter TCES TCEH timings timing point corrected Figure Added RDSR instruction Figure Added System Power-up Timing Re-aligned with Mode figures Corrected block address range AMS-A15 "Block-Erase" page Removed Industrial temperature parts Updated Figures Aligned waveform with rising edge clock 2004 Data Book Added footnote Table page (PSN: C0250001) Added RoHS compliance information page "Product Ordering Information" page Updated surface mount lead temperature from 240°C 260°C time from seconds seconds page Revised Absolute Max. Stress Ratings Surface Mount Solder Reflow Temp.
2002 2003
2003 2003 2004 2005
2005
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2005 Silicon Storage Technology, Inc. S71192-08-000 11/05
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