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Stratix Device Handbook, Volume
SII5V2-4.3
Copyright 2007 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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Contents
Chapter Revision Dates About this Handbook xiii
Contact Altera xiii Typographic Conventions xiii
Section Clock Management
Revision History Section
Chapter PLLs Stratix Stratix Devices
Introduction Enhanced PLLs Enhanced Hardware Overview Enhanced Software Overview Enhanced Pins 1-12 Fast PLLs 1-15 Fast Hardware Overview 1-15 Fast Software Overview 1-16 Fast Pins 1-18 Clock Feedback Modes 1-20 Source-Synchronous Mode 1-20 Compensation Mode 1-21 Normal Mode 1-22 Zero Delay Buffer Mode 1-23 External Feedback Mode 1-24 Hardware Features 1-25 Clock Multiplication Division 1-26 Phase-Shift Implementation 1-27 Programmable Duty Cycle 1-29 Advanced Clear Enable Control 1-29 Advanced Features 1-32 Counter Cascading 1-32 Clock Switchover 1-33 Reconfigurable Bandwidth 1-44 Reconfiguration 1-51 Spread-Spectrum Clocking 1-51 Board Layout 1-56 VCCA GNDA 1-56
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Contents
Stratix Device Handbook, Volume
VCCD 1-58 External Clock Output Power 1-58 Guidelines 1-61 Specifications 1-62 Clocking 1-62 Global Hierarchical Clocking 1-62 Clock Sources Region 1-64 Clock Input Connections 1-69 Clock Source Control Enhanced PLLs 1-73 Clock Source Control Fast PLLs 1-73 Delay Compensation Fast PLLs 1-75 Clock Output Connections 1-76 Clock Control Block 1-86 clkena Signals 1-90 Conclusion 1-91 Document Revision History 1-92
Section Memory
Revision History Section II-1
Chapter TriMatrix Embedded Memory Blocks Stratix Stratix Devices
Introduction TriMatrix Memory Overview Parity Support Byte Enable Support Pack Mode Support Address Clock Enable Support Memory Modes Single-Port Mode 2-10 Simple Dual-Port Mode 2-12 True Dual-Port Mode 2-15 Shift-Register Mode 2-18 Mode 2-20 FIFO Buffers Mode 2-20 Clock Modes 2-20 Independent Clock Mode 2-21 Input/Output Clock Mode 2-23 Read/Write Clock Mode 2-26 Single-Clock Mode 2-28 Designing With TriMatrix Memory 2-31 Selecting TriMatrix Memory Blocks 2-31 Synchronous Pseudo-Asynchronous Modes 2-32 Power-up Conditions Memory Initialization 2-32 Read-During-Write Operation Same Address 2-33 Same-Port Read-During-Write Mode 2-33
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Contents
Contents
Mixed-Port Read-During-Write Mode 2-34 Conclusion 2-35 Document Revision History 2-36
Chapter External Memory Interfaces Stratix Stratix Devices
Introduction External Memory Standards DDR2 SDRAM RLDRAM QDRII SRAM 3-10 Stratix Stratix Memory Support Overview 3-13 Memory Interface Pins 3-14 Phase-Shift Circuitry 3-21 Logic Block 3-28 Registers 3-31 3-38 Enhancements Stratix Stratix Devices 3-38 Conclusion 3-38 Document Revision History 3-39
Section III. Standards
Revision History Section III-1
Chapter Selectable Standards Stratix Stratix Devices
Introduction Stratix Stratix Features Stratix Stratix Standards Support Single-Ended Standards Differential Standards 4-10 Stratix Stratix External Memory Interface 4-19 Stratix Stratix Banks 4-20 Programmable Standards 4-22 On-Chip Termination 4-27 On-Chip Series Termination without Calibration 4-28 On-Chip Series Termination with Calibration 4-30 On-Chip Parallel Termination with Calibration 4-31 Design Considerations 4-33 Termination 4-33 Banks Restrictions 4-34 Placement Guidelines 4-36 Guidelines 4-39 Conclusion 4-42 Further Information 4-42 References 4-43 Document Revision History 4-44
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Contents
Stratix Device Handbook, Volume
Chapter High-Speed Differential Interfaces with Stratix Stratix Devices
Introduction Banks Differential Transmitter Differential Receiver Receiver Data Realignment Circuit Dynamic Phase Aligner 5-10 Synchronizer 5-11 Differential Termination 5-12 Fast 5-12 Clocking 5-13 Source Synchronous Timing Budget 5-16 Differential Data Orientation 5-16 Differential Position 5-17 Receiver Skew Margin Non-DPA 5-18 Differential Placement Guidelines 5-20 High-Speed Differential I/Os Single-Ended I/Os 5-20 Usage Guidelines 5-21 Non-DPA Differential Usage Guidelines 5-25 Board Design Considerations 5-26 Conclusion 5-27 Document Revision History 5-28
Section Digital Signal Processing (DSP)
Revision History Section IV-1
Chapter Blocks Stratix Stratix Devices
Introduction Block Overview Architecture Multiplier Block Adder/Output Block 6-16 Operational Modes 6-21 Simple Multiplier Mode 6-22 Multiply Accumulate Mode 6-25 Multiply Mode 6-26 Software Support 6-32 Conclusion 6-32 Document Revision History 6-33
Section Configuration& Remote System Upgrades
Revision History Section
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Contents
Contents
Chapter Configuring Stratix Stratix Devices
Introduction Configuration Devices Configuration Features Configuration Data Decompression Design Security Using Configuration Bitstream Encryption Remote System Upgrade Power-On Reset Circuit VCCPD Pins 7-10 VCCSEL 7-10 Output Configuration Pins 7-13 Fast Passive Parallel Configuration 7-14 Configuration Using Device External Host 7-15 Configuration Using Microprocessor 7-26 Configuration Using Enhanced Configuration Device 7-26 Active Serial Configuration (Serial Configuration Devices) 7-34 Estimating Active Serial Configuration Time 7-43 Programming Serial Configuration Devices 7-43 Passive Serial Configuration 7-46 Configuration Using Device External Host 7-47 Configuration Using Microprocessor 7-54 Configuration Using Configuration Device 7-55 Configuration Using Download Cable 7-67 Passive Parallel Asynchronous Configuration 7-73 JTAG Configuration 7-84 STAPL 7-91 Device Configuration Pins 7-92 Conclusion 7-106 Document Revision History 7-106
Chapter Remote System Upgrades with Stratix Stratix Devices
Introduction Functional Description Configuration Image Types Pages Remote System Upgrade Modes Overview Remote Update Mode Local Update Mode 8-12 Dedicated Remote System Upgrade Circuitry 8-14 Remote System Upgrade Registers 8-15 Remote System Upgrade State Machine 8-19 User Watchdog Timer 8-20 Interface Signals between Remote System Upgrade Circuitry FPGA Logic Array 8-21 Remote System Upgrade Descriptions 8-23 Quartus Software Support 8-24 altremote_update Megafunction 8-24 Remote System Upgrade Atom 8-27
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Contents
Stratix Device Handbook, Volume
System Design Guidelines Remote System Upgrade With Serial Configuration Devices Remote System Upgrade With Device Microprocessor Flash Device Remote System Upgrade with Enhanced Configuration Devices Conclusion Document Revision History
8-27 8-28 8-28 8-29 8-30 8-31
Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Stratix Stratix Devices
Introduction IEEE Std. 1149.1 Architecture IEEE Std. 1149.1 Boundary-Scan Register Boundary-Scan Cells Stratix Stratix Device IEEE Std. 1149.1 Operation Control SAMPLE/PRELOAD Instruction Mode 9-11 Capture Phase 9-12 Shift Update Phases 9-12 EXTEST Instruction Mode 9-13 Capture Phase 9-14 Shift Update Phases 9-14 BYPASS Instruction Mode 9-15 IDCODE Instruction Mode 9-16 USERCODE Instruction Mode 9-16 CLAMP Instruction Mode 9-17 HIGHZ Instruction Mode 9-17 Voltage Support JTAG Chain 9-17 Using IEEE Std. 1149.1 Circuitry 9-19 Configured Devices 9-19 Disabling IEEE Std. 1149.1 Circuitry 9-20 Guidelines IEEE Std. 1149.1 Boundary-Scan Testing 9-20 Boundary-Scan Description Language (BSDL) Support 9-21 Conclusion 9-21 References 9-22 Document Revision History 9-22
Section Layout Guidelines
Revision History Section VI-1
Chapter Package Information Stratix Stratix Devices
Introduction Thermal Resistance Package Outlines 484-Pin FBGA Flip Chip 672-Pin FBGA Flip Chip 780-Pin FBGA Flip Chip 10-1 10-2 10-5 10-5 10-6 10-9
viii
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Contents
Contents
1,020-Pin FBGA Flip Chip 1,152-Pin FBGA Flip Chip 1,508-Pin FBGA Flip Chip Document Revision History
10-11 10-13 10-15 10-17
Chapter High-Speed Board Layout Guidelines
Introduction 11-1 Material Selection 11-1 Transmission Line Layout 11-3 Impedance Calculation 11-4 Propagation Delay 11-8 Pre-Emphasis 11-9 Routing Schemes Minimizing Crosstalk Maintaining Signal Integrity 11-11 Signal Trace Routing 11-13 Termination Schemes 11-19 Simple Parallel Termination 11-19 Thevenin Parallel Termination 11-20 Active Parallel Termination 11-21 Series-RC Parallel Termination 11-22 Series Termination 11-23 Differential Pair Termination 11-23 Simultaneous Switching Noise 11-24 Power Filtering Distribution 11-26 Electromagnetic Interference (EMI) 11-28 Additional FPGA-Specific Information 11-29 Configuration 11-29 JTAG 11-30 Test Point 11-30 Summary 11-30 References 11-31 Document Revision History 11-31
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Contents
Stratix Device Handbook, Volume
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Chapter Revision Dates
chapters this book, Stratix Device Handbook, Volume were revised following dates. Where chapters groups chapters available separately, part numbers listed.
Chapter PLLs Stratix Stratix Devices Revised: 2007 Part number: SII52001-4.4 Chapter TriMatrix Embedded Memory Blocks Stratix Stratix Devices Revised: 2007 Part number: SII52002-4.4 Chapter External Memory Interfaces Stratix Stratix Devices Revised: 2007 Part number: SII52003-4.4 Chapter Selectable Standards Stratix Stratix Devices Revised: 2007 Part number: SII52004-4.5 Chapter High-Speed Differential Interfaces with Stratix Stratix Devices Revised: 2007 Part number: SII52005-2.1 Chapter Blocks Stratix Stratix Devices Revised: February 2007 Part number: SII52006-2.1 Chapter Configuring Stratix Stratix Devices Revised: 2007 Part number: SII52007-4.4 Chapter Remote System Upgrades with Stratix Stratix Devices Revised: 2007 Part number: SII52008-4.4 Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Stratix Stratix Devices Revised: February 2007 Part number: SII52009-3.2
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Chapter Revision Dates
Stratix Device Handbook, Volume
Chapter Package Information Stratix Stratix Devices Revised: 2007 Part number: SII52010-4.3 Chapter High-Speed Board Layout Guidelines Revised: 2007 Part number: SII52012-1.4
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About this Handbook
This handbook provides comprehensive information about Altera® Stratix® family devices.
Contact Altera
most up-to-date information about Altera products, refer following table. Contact Method
Website Website Email Product literature Altera literature services Email Website
Contact
Technical support Technical training
Address
www.altera.com/support www.altera.com/training custrain@altera.com www.altera.com/literature literature@altera.com nacomp@altera.com authorization@altera.com
Non-technical support (General) Email (Software Licensing) Email Note table:
also contact your local Altera sales office sales representative.
Typographic Conventions
Visual
Bold Type with Initial Capital Letters bold type
This document uses typographic conventions shown below.
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \qdesigns directory, drive, chiptrip.gdf file. Document titles shown italic type with initial capital letters. Example: High-Speed Board Design.
Italic Type with Initial Capital Letters
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xiii Preliminary
Typographic Conventions
Stratix Device Handbook, Volume
Visual
Italic type
Meaning
Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file.
Initial Capital Letters "Subheading Title"
Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles on-line help topics shown quotation marks. Example: "Typographic Conventions." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., resetn. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Courier type
etc.
Numbered steps used list items when sequence items important, such steps listed procedure. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. caution indicates required information that needs special consideration understanding should read prior starting continuing with procedure process. warning indicates information that should read prior starting continuing procedure processes angled arrow indicates should press Enter key. feet direct more information particular topic.
Preliminary
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Section Clock Management
This section provides information different types phase-locked loops (PLLs). feature-rich enhanced PLLs assist designers managing clocks internally also have ability drive chip control system-level clock networks. fast PLLs offer general-purpose clock management with multiplication phase shifting well highspeed outputs manage high-speed differential interfaces. This section contains detailed information features, interconnections logic array chip, specifications both types PLLs. This section contains following chapter:
Chapter PLLs Stratix Stratix Devices
Revision History
Refer each chapter specific revision history. information when each chapter updated, refer Chapter Revision Dates section, which appears full handbook.
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Section
Clock Management
Stratix Device Handbook, Volume
Section
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PLLs Stratix Stratix Devices
SII52001-4.4
Introduction
Stratix® Stratix device phase-locked loops (PLLs) provide robust clock management synthesis device clock management, external system clock management, high-speed interfaces. Stratix devices have PLLs, Stratix devices have PLLs. Stratix Stratix PLLs highly versatile used zero delay buffer, jitter attenuator, skew buffer, frequency synthesizer. Stratix Stratix devices feature both enhanced PLLs fast PLLs. Stratix Stratix devices have four enhanced PLLs. Stratix devices have eight fast PLLs Stratix devices have four PLLs. Both enhanced fast PLLs feature rich, supporting advanced capabilities such clock switchover, reconfigurable phase shift, reconfiguration, reconfigurable bandwidth. PLLs used general-purpose clock management, supporting multiplication, phase shifting, programmable duty cycle. addition, enhanced PLLs support external clock feedback mode, spread-spectrum clocking, counter cascading. Fast PLLs offer high speed outputs manage high-speed differential interfaces. Stratix Stratix devices also support power-down mode where clock networks that being used easily turned off, reducing overall power consumption device. addition, Stratix Stratix PLLs support dynamic selection input clock from five possible sources, giving flexibility choose from multiple four) clock sources feed primary secondary clock input ports. Altera® Quartus® software enables PLLs their features without requiring external devices.
Altera Corporation 2007
Introduction
Tables show PLLs available each Stratix Stratix device, respectively.
Table 1-1. Stratix Device Availability Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Note Enhanced PLLs
Fast PLLs
Notes Table 1-1:
EP2S60 device 1,020-pin package contains PLLs. EP2S60 devices 484-pin 672-pin packages contain fast PLLs enhanced PLLs EP2S90 devices 1020-pin 1508-pin packages contain PLLs. EP2S90 devices 484-pin 780-pin packages contain fast PLLs enhanced PLLs EP2S130 devices 1020-pin 1508-pin packages contain PLLs. EP2S130 device 780-pin package contains fast PLLs enhanced PLLs
Table 1-2. Stratix Device Availability Fast PLLs Device
EP2SGX30 EP2SGX60 EP2SGX90 EP2SGX130
Note Enhanced PLLs
Notes Table 1-2:
global regional clocks fast PLL's transceiver block drive fast input. other must drive global regional source. source cannot driven internally generated logic before driving fast PLL. EP2SGX30C EP2SGX60C devices only have fast PLLs (PLLs connectivity from these PLLs global regional clock networks remains same shown this table. PLLs available Stratix devices. however, these PLLs listed Table because Stratix numbering scheme consistent with Stratix Stratix devices.
Stratix Device Handbook, Volume
Altera Corporation 2007
PLLs Stratix Stratix Devices
Table shows enhanced fast features Stratix Stratix devices.
Table 1-3. Stratix Stratix Features Feature
Clock multiplication division Phase shift Clock switchover reconfiguration Reconfigurable bandwidth Spread-spectrum clocking Programmable duty cycle Number clock outputs
Enhanced
m/(n post-scale counter) Down 125-ps increments
Fast
m/(n post-scale counter) Down 125-ps increments
Number dedicated external clock outputs Three differential single-ended Number feedback clock inputs Notes Table 1-3:
enhanced PLLs, range from with duty cycle. Post-scale counters range from with duty cycle. non-50% duty-cycle clock outputs, post-scale counters range from 256. fast PLLs, range from post-scale counters range from non-50% duty-cycle clock outputs, post-scale counters range from smallest phase shift determined voltage controlled oscillator (VCO) period divided eight. supported phase-shift range from Stratix Stratix devices shift output frequencies increments least Smaller degree increments possible depending frequency divide parameters. non-50% duty cycle clock outputs post-scale counters range from 256. Stratix Stratix fast PLLs only support manual clock switchover. clock outputs driven internal clock networks pin. clock outputs fast PLLs drive used external clock output. high-speed differential pins, device uses data channel generate transmitter output clock (txclkout). design uses external feedback input pins, will lose two, fBIN differential) dedicated output clock pin.
Figure shows top-level diagram Stratix device locations. Figure shows top-level diagram Stratix device locations. "Clock Control Block" page 1-86 more detail connections global regional clocks networks.
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Stratix Device Handbook, Volume
Introduction
Figure 1-1. Stratix Locations
Enhanced CLK12-15 Enhanced
FPLL7CLK
RCLK28-31 RCLK24-27
FPLL10CLK
GCLK12-15
RCLK0-3 Fast PLLs CLK0-3 Fast PLLs GCLK0-3 RCLK4-7
RCLK20-23 GCLK8-11 Fast PLLs CLK8-11 Fast PLLs
RCLK16-19
GCLK4-7
RCLK8-11 FPLL8CLK
RCLK12-15 FPLL9CLK
CLK4-7 Enhanced Enhanced
Stratix Device Handbook, Volume
Altera Corporation 2007
PLLs Stratix Stratix Devices
Figure 1-2. Stratix Locations
CLK[15.12]
FPLL7CLK
CLK[3.0]
PLLs
FPLL8CLK
CLK[7.4]
Enhanced PLLs
Stratix Stratix devices contain four enhanced PLLs with advanced clock management features. main goal synchronize phase frequency internal external clock input reference clock. There number components that comprise achieve this phase alignment.
Enhanced Hardware Overview
Stratix Stratix PLLs align rising edge reference input clock feedback clock using phase-frequency detector (PFD). falling edges determined duty-cycle specifications. produces down signal that determines whether needs operate higher lower frequency.
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Stratix Device Handbook, Volume
Enhanced PLLs
output applied charge pump loop filter, which produces control voltage setting frequency. produces signal, then frequency increases. down signal decreases frequency. outputs these down signals charge pump. charge pump receives signal, current driven into loop filter. Conversely, receives down signal, current drawn from loop filter. loop filter converts these down signals voltage that used bias VCO. loop filter also removes glitches from charge pump prevents voltage over-shoot, which filters jitter VCO. voltage from loop filter determines fast operates. implemented four-stage differential ring oscillator. divide counter inserted feedback loop increase frequency above input reference frequency. frequency (fVCO) equal times input reference clock (fREF). input reference clock (fREF) equal input clock (fIN) divided prescale counter (n). Therefore, feedback clock (fFB) applied input locked fREF that applied other input PFD. output feed post-scale counters (C0, C5). These post-scale counters allow number harmonically related frequencies produced within PLL. Figure shows simplified block diagram major components Stratix Stratix enhanced PLL. Figure shows enhanced PLL's outputs dedicated clock outputs.
Stratix Device Handbook, Volume
Altera Corporation 2007
PLLs Stratix Stratix Devices
Figure 1-3. Stratix Stratix Enhanced
Phase Selection Selectable Each Output Port From Adjacent Post-Scale Counters
Clock Switchover Circuitry INCLK[3.0]
Phase Frequency Detector
Spread Spectrum
Global Regional Clock
Charge Pump
Loop Filter
Global Clocks Regional Clocks
Buffers
FBIN
Lock Detect Filter
general routing
Shaded Portions Reconfigurable
Phase Selection Affecting Outputs
Notes Figure 1-3:
Each clock source come from four clock pins located same side device PLL. PLLs each have single-ended dedicated clock outputs three differential dedicated clock outputs. design uses external feedback input pins, will lose two, fBIN differential) dedicated output clock pin. Every Stratix Stratix device least enhanced PLLs with single-ended differential external feedback input PLL. global regional clock input driven output from another PLL, pin-driven dedicated global regional clock, through clock control block provided clock control block output from another pin-driven dedicated global regional clock. internally generated global signal cannot drive PLL.
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Stratix Device Handbook, Volume
Enhanced PLLs
External Clock Outputs
Enhanced PLLs each support single-ended clock outputs three differential pairs). Figure 1-4. Figure 1-4. External Clock Outputs Enhanced PLLs
Enhanced
extclken0 extclken1 PLL#_OUT0p PLL#_OUT0n
extclken2 extclken3 PLL#_OUT1p PLL#_OUT1n
extclken4 extclken5 PLL#_OUT2p (1), PLL#_OUT2n (1),
Notes Figure 1-4:
These clock output pins C[5.0] counters. These clock output pins used either external clock outputs external feedback. design uses external feedback input pins, will lose two, fBIN differential) dedicated output clock pin. These external clock enable signals available only when using altclkctrl megafunction.
output counters C[5.0] feed dedicated external clock outputs, shown Figure 1-5. Therefore, counter frequency drive output pins available from given PLL. dedicated output clock pins (PLL_OUT) from each enhanced powered separate power (e.g., VCC_PLL5_OUT, VCC_PLL6_OUT, etc.), reducing overall output jitter providing improved isolation from switching pins.
Stratix Device Handbook, Volume
Altera Corporation 2007
PLLs Stratix Stratix Devices
Figure 1-5. External Clock Output Connectivity Output Counters Enhanced PLLs Note
pins
From internal logic
Multiplexer Selection Configuration File
Note Figure 1-5:
design each external clock output general-purpose output from logic array. These pins multiplexed with element (IOE) outputs.
Each single-ended output pair either phase 180° phase. Quartus software places gate design into implement 180° phase with respect other pair. clock output pairs support same standards standard output pins bottom banks) well LVDS, LVPECL, differential HSTL, differential SSTL. Table 1-6, "Enhanced Pins" section page 1-12 determine which standards enhanced clock pins support. When single-ended differential mode, power supports single-ended three differential outputs. Both outputs same standard single-ended mode maintain performance. also external clock output pins user output pins external enhanced clocking needed. enhanced also drive regular through global regional clock network. this case, jitter output clock pending characterization
Enhanced Software Overview
Stratix Stratix enhanced PLLs enabled Quartus software using altpll megafunction. Figure shows available ports they named Quartus altpll megafunction) Stratix Stratix enhanced PLL.
Altera Corporation 2007
Stratix Device Handbook, Volume
Enhanced PLLs
Figure 1-6. Enhanced Ports
(2), (2),
pllena inclk0 inclk1 locked scanclk scanwrite scanread scandata clkloss activeclock scandataout clkbad[1.0] scandone Physical C[5.0]
Signal Driven Internal Logic Signal Driven Internal Logic Internal Clock Signal
fbin
clkswitch areset pfdena pll_out0p pll_out0n pll_out1p pll_out1n pll_out2p pll_out2n
Notes Figure 1-6:
Enhanced fast PLLs share this input pin. These either single-ended differential pins. primary secondary clock input from four clock pins located same side device PLL. drive global regional clock networks dedicated external clock output pins. These dedicated output clocks C[5.0] counters.
Tables describe enhanced ports.
Table 1-4. Enhanced Input Signals (Part Port inclk0 inclk1 fbin pllena clkswitch Description
Primary clock input PLL. Secondary clock input PLL. External feedback input PLL. Enable enabling disabling PLLs. Active high. Switch-over signal used initiate external clock switch-over control. Active high.
Source
another another Logic array
Destination
counter counter General control signal switch-over circuit
1-10 Stratix Device Handbook, Volume
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PLLs Stratix Stratix Devices
Table 1-4. Enhanced Input Signals (Part Port areset Description
Signal used reset which resynchronizes counter outputs. Active high. Enables outputs from phase frequency detector. Active high. Serial clock signal real-time reconfiguration feature.
Source
Logic array
Destination
General control signal Reconfiguration circuit Reconfiguration circuit Reconfiguration circuit Reconfiguration circuit
pfdena scanclk scandata scanwrite scanread
Logic array Logic array
Serial input data stream real- Logic array time reconfiguration feature. Enables writing data scan chain into PLL. Active high. Enables scan data written into scan chain. Active high. Logic array Logic array
Table 1-5. Enhanced Output Signals (Part Port
c[5.0] pll_out [2.0]p pll_out [2.0]n
Description
Source
Destination
Internal external clock Pin(s)
output counters driving regional, counter global external clocks. counter These three differential single-ended external clock output pins from C[5.0] counters, every output driven counter. positive negative pins differential pins. Signal indicating switch-over circuit detected switch-over condition. Signals indicating which reference clock longer toggling. clkbad1 indicates inclk1 status, clkbad0 indicates inclk0 status. good; 0=bad Lock gated lock output from lock detect circuit. Active high. switch-over circuit switch-over circuit
clkloss
Logic array
clkbad[1.0]
Logic array
locked
lock detect
Logic array Logic array
activeclock
clock Signal indicate which clock multiplexer inclk0 inclk1) driving PLL. this signal low, inclk0 drives PLL, this signal high, inclk1 drives
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1-11 Stratix Device Handbook, Volume
Enhanced PLLs
Table 1-5. Enhanced Output Signals (Part Port scandataout scandone Description Source Destination
Logic array Logic array
Output last shift register scan chain scan chain. Signal indicating when completed reconfiguration. transition indicates that been reconfigured. scan chain
Enhanced Pins
Table lists standards support enhanced clock outputs.
Table 1-6. Standards Supported Enhanced Pins (Part Note Input Standard INCLK
LVTTL LVCMOS 3.3-V 3.3-V PCI-X SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL Class 1.2-V HSTL Class
Output FBIN EXTCLK
1-12 Stratix Device Handbook, Volume
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PLLs Stratix Stratix Devices
Table 1-6. Standards Supported Enhanced Pins (Part Note Input Standard INCLK
Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class Differential SSTL-18 Class 1.8-V differential HSTL Class 1.8-V differential HSTL Class 1.5-V differential HSTL Class 1.5-V differential HSTL Class LVDS HyperTransport technology Differential LVPECL Note Table 1-6:
enhanced external clock output bank does allow mixture both single-ended differential standards.
Output FBIN EXTCLK
Table shows physical pins their purpose Stratix Stratix enhanced PLLs. inclk port connections pins "Clock Control Block" page 1-86.
Table 1-7. Stratix Stratix Enhanced Pins (Part
CLK4p/n CLK5p/n CLK6p/n CLK7p/n CLK12p/n CLK13p/n CLK14p/n CLK15p/n PLL5_FBp/n
Note
Description
Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive fbin port
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1-13 Stratix Device Handbook, Volume
Enhanced PLLs
Table 1-7. Stratix Stratix Enhanced Pins (Part
PLL6_FBp/n PLL11_FBp/n PLL12_FBp/n PLL_ENA PLL5_OUT[2.0]p/n PLL6_OUT[2.0]p/n PLL11_OUT[2.0]p/n PLL12_OUT[2.0]p/n VCCA_PLL5 GNDA_PLL5 VCCA_PLL6 GNDA_PLL6 VCCA_PLL11 GNDA_PLL11 VCCA_PLL12 GNDA_PLL12 VCCD_PLL VCC_PLL5_OUT
Note
Description
Single-ended differential pins that drive fbin port Single-ended differential pins that drive fbin port Single-ended differential pins that drive fbin port Dedicated input that drives pllena port PLLs. this pin, connect ground. Single-ended differential pins driven C[5.0] ports from Single-ended differential pins driven C[5.0] ports from Single-ended differential pins driven C[5.0] ports from Single-ended differential pins driven C[5.0] ports from Analog power must connect this even used. Analog ground connect this plane board. Analog power must connect this even used. Analog ground connect this plane board. Analog power must connect this even used. Analog ground connect this plane board. Analog power must connect this even used. Analog ground connect this plane board. Digital power PLLs. must connect this even used. External clock output VCCIO power PLL5_OUT0p, PLL5_OUT0n, PLL5_OUT1p, PLL5_OUT1n, PLL5_OUT2p, PLL5_OUT2n outputs from External clock output VCCIO power PLL6_OUT0p, PLL6_OUT0n, PLL6_OUT1p, PLL6_OUT1n PLL6_OUT2p, PLL6_OUT2n outputs from External clock output VCCIO power PLL11_OUT0p, PLL11_OUT0n, PLL11_OUT1p, PLL11_OUT1n PLL11_OUT2p, PLL11_OUT2n outputs from
VCC_PLL6_OUT
VCC_PLL11_OUT
1-14 Stratix Device Handbook, Volume
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PLLs Stratix Stratix Devices
Table 1-7. Stratix Stratix Enhanced Pins (Part
VCC_PLL12_OUT
Note
Description
External clock output VCCIO power PLL12_OUT0p, PLL12_OUT0n, PLL12_OUT1p, PLL12_OUT1n PLL12_OUT2p, PLL12_OUT2n outputs from
Note Table 1-7:
negative pins (CLKn, PLL_FBn, PLL_OUTn) only required with differential signaling.
Fast PLLs
Stratix devices contain eight fast PLLs Stratix devices contain four fast PLLs. Fast PLLs have high-speed differential interface capability along with general-purpose features.
Fast Hardware Overview
Figure shows diagram fast PLL. Figure 1-7. Stratix Stratix Fast Block Diagram
Phase Selection Selectable each Output Port Post-Scale Counters
Global regional clock
Clock Switchover Circuitry
Phase Frequency Detector
diffioclk0 Global clocks block Regional clocks loaden0 diffioclk1 loaden1
Clock Input
Charge Pump
Loop Filter
Global regional clock
Shaded Portions Reconfigurable
Notes Figure 1-7:
Stratix Stratix fast PLLs only support manual clock switchover. global regional clock input driven output from another PLL, pin-driven dedicated global regional clock, through clock control block provided clock control block output from another pin-driven dedicated global regional clock. internally generated global signal cannot drive PLL. high-speed differential support mode, this high-speed clock feeds SERDES. Stratix devices only support rate data transfer fast high-speed differential support mode. This signal high-speed differential support SERDES control signal. design enables this counter, then device frequency range MHz.
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Fast PLLs
External Clock Outputs
Each fast supports differential single-ended outputs source-synchronous transmitters general-purpose external clocks. There dedicated external clock output pins. fast global regional outputs drive external clock output pin. standards supported particular bank determines what standards possible external clock output driven fast that bank.
more information, Selectable Standards Stratix Stratix Devices chapter volume Stratix Device Handbook Stratix Device Handbook.
Fast Software Overview
Stratix Stratix fast PLLs enabled Quartus software using altpll megafunction. Figure shows available ports they named Quartus altpll megafunction) Stratix Stratix fast PLL. Figure 1-8. Stratix Stratix Fast Ports Physical Destinations
inclk0 inclk1 pllena locked areset pfdena scanclk scandata scanwrite scanread scandataout scandone C[3.0] Physical Signal Driven Internal Logic Signal Driven Internal Logic Internal Clock Signal
Notes Figure 1-8:
This input either single-ended differential. This input shared enhanced fast PLLs.
Tables show description fast ports.
Table 1-8. Fast Input Signals (Part Name inclk0 inclk1 Description
Primary clock input fast PLL. Secondary clock input fast PLL.
Source
another another
Destination
counter counter
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Table 1-8. Fast Input Signals (Part Name pllena clkswitch areset pfdena scanclk scandata scanwrite scanread Description
Enable enabling disabling PLLs. Active high.
Source
Destination
control signal Reconfiguration circuit control signal Reconfiguration circuit Reconfiguration circuit Reconfiguration circuit Reconfiguration circuit
Switch-over signal used initiate external clock Logic array switch-over control. Active high. Enables up/down outputs from phase-frequency detector. Active high. Enables up/down outputs from phase-frequency detector. Active high. Serial clock signal real-time control feature. Serial input data stream real-time control feature. Enables writing data scan chain into Active high. Enables scan data written into scan chain Active high. Logic array Logic array Logic array Logic array Logic array Logic array
Table 1-9. Fast Output Signals Name
c[3.0]
Description
outputs driving regional global clock. Lock gated lock output from lock detect circuit. Active high. Output last shift register scan chain. Signal indicating when completed reconfiguration. transition indicates been reconfigured.
Source
counter lock detect scan chain scan chain
Destination
Internal clock Logic array Logic array Logic array
locked scandataout scandone
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Fast PLLs
Fast Pins
Table 1-10 shows standards supported fast input pins.
Table 1-10. Standards Supported Stratix Stratix Fast Pins Standard
LVTTL LVCMOS 3.3-V 3.3-V PCI-X SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class Differential SSTL-18 Class 1.8-V differential HSTL Class 1.8-V differential HSTL Class 1.5-V differential HSTL Class 1.5-V differential HSTL Class LVDS HyperTransport technology Differential LVPECL
INCLK
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Table 1-11 shows physical pins their purpose fast PLLs. inclk port connections pins, "Clocking" page 1-62.
Table 1-11. Fast Pins (Part
CLK0p/n CLK1p/n CLK2p/n CLK3p/n CLK8p/n CLK9p/n CLK10p/n CLK11p/n FPLL7CLKp/n FPLL8CLKp/n FPLL9CLKp/n FPLL10CLKp/n PLL_ENA VCCD_PLL VCCA_PLL1 GNDA_PLL1 VCCA_PLL2 GNDA_PLL2 VCCA_PLL3 GNDA_PLL3 VCCA_PLL4 GNDA_PLL4 GNDA_PLL7 VCCA_PLL8 GNDA_PLL8 VCCA_PLL9 GNDA_PLL9 VCCA_PLL10
Note Description
Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port PLLs Single-ended differential pins that drive inclk port Single-ended differential pins that drive inclk port Single-ended differential pins that drive inclk port Single-ended differential pins that drive inclk port Dedicated input that drives pllena port PLLs. this pin, connect GND. Digital power PLLs. must connect this even used. Analog power must connect this even used. Analog ground Your connect this plane board. Analog power must connect this even used. Analog ground connect this plane board. Analog power must connect this even used. Analog ground connect this plane board. Analog power must connect this even used. Analog ground connect this plane board. Analog ground connect this plane board. Analog power must connect this even used. Analog ground connect this plane board. Analog power must connect this even used. Analog ground connect this plane board. Analog power must connect this even used.
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Clock Feedback Modes
Table 1-11. Fast Pins (Part
GNDA_PLL10 Note Table 1-11:
Note Description
Analog ground connect this plane board.
negative pins (CLKn FPLL_CLKn) only required with differential signaling.
Clock Feedback Modes
Stratix Stratix PLLs support five different clock feedback modes. Each mode allows clock multiplication division, phase shifting, programmable duty cycle. Each must driven dedicated clock input pins proper clock compensation. clock input connections each listed Table 1-20 page 1-70. Table 1-12 shows which modes supported which type.
Table 1-12. Clock Feedback Mode Availability Mode Available Clock Feedback Mode Enhanced PLLs
Source synchronous mode compensation mode Normal mode Zero delay buffer mode External feedback mode
Fast PLLs
Source-Synchronous Mode
data clock arrive same time input pins, they guaranteed keep same phase relationship clock data ports input register. Figure shows example waveform clock data this mode. This mode recommended sourcesynchronous data transfers. Data clock signals experience similar buffer delays long same standard used.
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Figure 1-9. Phase Relationship Between Clock Data Source-Synchronous Mode
Data
inclk
Data register
Clock register
source-synchronous mode, enhanced PLLs compensate clock delay bottom registers fast PLLs compensate clock delay side registers. While implementing source-synchronous receivers these banks, corresponding type best matching between clock data delays (from input pins register ports). input register delay chain within zero Quartus software data pins clocked source-synchronous mode PLL.
Compensation Mode
this mode, does compensate clock networks. This provides better jitter performance because clock feedback into does pass through much circuitry. Both internal external clock outputs phase shifted with respect clock input. Figure 1-10 shows example waveform clocks' phase relationship this mode.
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Clock Feedback Modes
Figure 1-10. Phase Relationship between Clocks Compensation Mode
Phase Aligned
Reference Clock Input Clock Register Clock Port (1),
External Clock Outputs
Notes Figure 1-10.
Internal clocks phase-aligned each other. clock outputs lead input clocks.
Normal Mode
internal clock normal mode phase-aligned input clock pin. external clock output will have phase delay relative clock input connected this mode. normal mode, delay introduced GCLK RCLK network fully compensated. Figure 1-11 shows example waveform clocks' phase relationship this mode.
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Figure 1-11. Phase Relationship Between Clocks Normal Mode
Phase Aligned
Reference Clock Input
Clock Register Clock Port
External Clock Outputs
Note Figure 1-11:
external clock output lead internal clock signals.
Zero Delay Buffer Mode
zero delay buffer mode, external clock output phase-aligned with clock input zero delay through device. Figure 1-12 shows example waveform clocks' phase relationship this mode. When using this mode, Altera requires that same standard input clock, output clocks. When using single-ended standards, inclk port must dedicated CLKp input pin.
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Clock Feedback Modes
Figure 1-12. Phase Relationship Between Clocks Zero Delay Buffer Mode
Phase Aligned
Reference Clock Input
Clock Register Clock Port
External Clock Outputs
Note Figure 1-12:
internal clock output lead external clock outputs.
External Feedback Mode
external feedback mode, external feedback input pin, fbin, phase-aligned with clock input pin, (see Figure 1-13). Aligning these clocks allows remove clock delay skew between devices. This mode possible enhanced PLLs. PLLs support feedback dedicated external outputs, either single-ended differential pair. this mode, counter feeds back fbin input, becoming part feedback loop. this mode, will using dedicated external clock outputs (two differential standard used) fbin input pin. When using this mode, Altera requires that same standard input clock, feedback input, output clocks. When using single-ended standards, inclk port must dedicated CLKp input pin.
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Figure 1-13. Phase Relationship Between Clocks External Feedback Mode
Phase Aligned
Reference Clock Input
Clock Register Clock Port
External Clock Outputs
fBIN Clock Input
Note Figure 1-13:
clock outputs lead fBIN clock input.
Hardware Features
Stratix Stratix PLLs support number features general-purpose clock management. This section discusses clock multiplication division implementation, phase-shifting implementations programmable duty cycles. Table 1-13 shows which feature available which type Stratix Stratix PLL.
Table 1-13. Stratix Stratix Hardware Features (Part Availability Hardware Features Enhanced
Clock multiplication division counter value counter value Post-scale counter values post-scale counter) Ranges from through Ranges from through Ranges from through
Fast
post-scale counter) Ranges from through Ranges from through Ranges from through
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Hardware Features
Table 1-13. Stratix Stratix Hardware Features (Part Availability Hardware Features Enhanced
Phase shift Programmable duty cycle Notes Table 1-13:
Post-scale counters range from through output clock uses duty cycle. output clocks using non-50% duty cycle, post-scale counters range from through 256. Post-scale counters range from through output clock uses duty cycle. output clocks using non-50% duty cycle, post-scale counters range from through smallest phase shift determined period divided degree increments, Stratix device shift output frequencies increments least Smaller degree increments possible depending frequency divide parameters.
Fast
Down 125-ps increments
Down 125-ps increments
Clock Multiplication Division
Each Stratix provides clock synthesis output ports using m/(n post-scale counter) scaling factors. input clock divided pre-scale factor, then multiplied feedback factor. control loop drives match (m/n). Each output port unique post-scale counter that divides down high-frequency VCO. multiple outputs with different frequencies, least common multiple output frequencies that meets frequency specifications. example, output frequencies required from MHz, then Quartus software sets (the least common multiple within range). Then, post-scale counters scale down frequency each output port. There pre-scale counter, multiply counter, PLL, with range both enhanced PLLs. fast PLLs, ranges from while ranges from There generic post-scale counters enhanced PLLs that feed regional clocks, global clocks, external clock outputs, ranging from with duty cycle setting each PLL. post-scale counters range from with non-50% duty cycle setting. fast PLLs, there four post-scale counters (C0, regional global clock output ports. post-scale counters range from with duty cycle setting. non-50% duty cycle clock outputs, post-scale counters range from design uses high-speed interface, connect dedicated dffioclk clock output port allow high-speed frequency drive serializer/deserializer (SERDES).
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Quartus software automatically chooses appropriate scaling factors according input frequency, multiplication, division values entered into altpll megafunction.
Phase-Shift Implementation
Phase shift used implement robust solution clock delays Stratix Stratix devices. Phase shift implemented using combination phase output counter starting time. phase output counter starting time most accurate method inserting delays, since purely based counter settings, which independent process, voltage, temperature. Stratix Stratix PLLs support programmable delay elements because these delay elements require considerable area sensitive process, voltage, temperature.
phase shift output clocks from Stratix Stratix enhanced either:
Fine resolution using phase taps Coarse resolution using counter starting time
phase counter starting time implemented allowing output counters (C[5.0] eight phases reference clock. This allows adjust delay time with fine resolution. minimum delay time that insert using this method defined
fine 8fVCO 8MfREF
where fREF input reference clock frequency. example, fREF MHz, then fVCO fINE equals 156.25 This phase shift defined operating frequency, which governed reference clock frequency counter settings. also delay start counters predetermined number counter clocks. express phase shift
coarse
fVco MfREF
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Hardware Features
where count value counter delay time, (this initial setting usage section compilation report Quartus software). initial value phase shift. Figure 1-14 shows example phase shift insertion using fine resolution using phase taps method. eight phases from shown labeled reference. this example, CLK0 based phase from value counter one. CLK1 signal divided four, clocks high time clocks time. CLK1 based 135° phase from also value counter one. CLK1 signal also divided this case, clocks offset FINE. CLK2 based 0phase from value counter three. This creates delay COARSE, (two complete periods). Figure 1-14. Delay Insertion Using Phase Output Counter Delay Time
tVCO
tVCO
CLK0
td0-1
CLK1
td0-2
CLK2
coarse fine phase shifts described above implement clock delays Stratix Stratix devices. phase-shift parameters Quartus software.
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Programmable Duty Cycle
programmable duty cycle allows enhanced fast PLLs generate clock outputs with variable duty cycle. This feature supported each enhanced fast post-scale counter C[]. duty cycle setting achieved high time count setting post-scale counters. Quartus software uses frequency input required multiply divide rate determine duty cycle choices. post-scale counter value determines precision duty cycle. precision defined divided post-scale counter value. closest value 100% achievable given counter value. example, counter ten, then steps possible duty cycle choices between 90%. device uses external feedback, must duty cycle counter driving fbin 50%. Combining programmable duty cycle with programmable phase shift allows generation precise non-overlapping clocks.
Advanced Clear Enable Control
There several control signals clearing enabling PLLs their outputs. these signals control resynchronization gate output clocks low-power applications.
Enhanced Lock Detect Circuit
lock output indicates that locked onto reference clock. Without additional circuitry, lock signal toggle begins tracking reference clock. need gate lock signal system control. Either gated lock signal ungated lock signal from locked port drive logic array output pin. Stratix Stratix enhanced fast PLLs include programmable counter that holds lock signal user-selected number input clock transitions. This allows lock before enabling lock signal. Quartus software 20-bit counter value.
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Hardware Features
Figure 1-15 shows timing waveform lock gated lock signals. Figure 1-15. Timing Waveform Lock Gated Lock Signals
PLL_ENA
Reference Clock
Feedback Clock
Lock
Filter Counter Reaches Value Count
Gated Lock
device resets enables both counter simultaneously when pllena signal asserted areset signal deasserted. Enhanced PLLs fast PLLs support this feature. ensure correct circuit operation, ensure that output clocks have correct phase relationship with respect input clock, Altera recommends that input clock running before Stratix device finished configuring.
PLL_ENA
PLL_ENA dedicated that enables disables PLLs Stratix Stratix device. When PLL_ENA low, clock output ports driven PLLs lock. When PLL_ENA goes high again, PLLs relock resynchronize input clocks. choose which PLLs controlled pllena signal connecting pllena input port altpll megafunction common PLL_ENA input pin. Also, whenever loses lock reason excessive inclk jitter, clock switchover, reconfiguration, power supply noise, etc.), must reset with areset signal guarantee correct phase relationship between output clocks. phase relationship between input clock versus output clock, between different output clocks from important your design, need reset.
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level VCCSEL selects PLL_ENA input buffer power. Therefore, VCCSEL high, PLL_ENA pin's 1.8/1.5-V input buffer powered VCCIO bank that PLL_ENA resides VCCSEL (GND), PLL_ENA pin's 3.3/2.5-V input buffer powered VCCPD.
more information VCCSEL pin, refer Configuring Stratix Stratix Devices chapter volume Stratix Device Handbook Stratix Device Handbook.
pfdena
pfdena signals control phase frequency detector (PFD) output with programmable gate. disable PFD, operates last value control voltage frequency with some long-term drift lower frequency. system continues running when goes lock input clock disabled. maintaining last locked frequency, system time store current settings before shutting down. either your control signal clkloss gated locked status signals, trigger pfdena.
areset
areset signal reset resynchronization input each PLL. device input pins internal logic drive these input signals. When driven high, counters reset, clearing output placing lock. back nominal setting (~700 MHz). When driven again, will resynchronize input relocks. target frequency below this nominal frequency, then output frequency starts higher value than desired locks. areset signal should asserted every time loses lock guarantee correct phase relationship between input clock output clocks. Users should include areset signal designs following conditions true:
reconfiguration clock switchover enabled design. Phase relationships between input clock output clocks need maintained after loss lock condition. input clock toggling unstable upon power assert areset signal after input clock toggling, making sure stay within input jitter specification. Altera recommends that areset locked signals your designs control observe status your PLL.
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Advanced Features
clkena
system cannot tolerate higher output frequencies when using pfdena higher value, clkena signals disable output clocks until locks. clkena signals control regional, global, external clock outputs. clkena signals registered falling edge counter output clock enable disable clock without glitches. Figure 1-56 "Clock Control Block" section page 1-86 this document more information clkena signals.
Advanced Features
Stratix Stratix PLLs offer variety advanced features, such counter cascading, clock switchover, reconfiguration, reconfigurable bandwidth, spread-spectrum clocking. Table 1-14 shows which advanced features available which type Stratix Stratix PLL.
Table 1-14. Stratix Stratix Advanced Features Availability Advanced Feature Enhanced PLLs
Counter cascading Clock switchover reconfiguration Reconfigurable bandwidth Spread-spectrum clocking Note Table 1-14:
Stratix Stratix fast PLLs only support manual clock switchover, automatic clock switchover.
Fast PLLs
Counter Cascading
Stratix Stratix enhanced supports counter cascading create post-scale counters larger than 512. This implemented feeding output counter into input next counter cascade chain, shown Figure 1-16.
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Figure 1-16. Counter Cascading
Output
Output
Output
Output Output
Output
When cascading counters implement larger division high-frequency clock, cascaded counters behave counter with product individual counter settings. example, then cascaded value Stratix Stratix fast PLLs does support counter cascading.
Counter cascading configuration file, meaning they cascaded using reconfiguration.
Clock Switchover
clock switchover feature allows switch between reference input clocks. this feature clock redundancy dual clock domain application such system that turns redundant clock primary clock stops running. design perform clock switchover automatically, when clock longer toggling, based user control signal, clkswitch. Enhanced PLLs support both automatic manual switchover, while fast PLLs only support manual switchover.
Automatic Clock Switchover
Stratix Stratix device PLLs support fully configurable clock switchover capability. Figure 1-17 shows block diagram switch-over circuit built into enhanced PLL. When primary clock signal present, clock sense block automatically switches from
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Advanced Features
primary secondary clock reference. design sends clk0_bad, clk1_bad, clk_loss signals from implement custom switchover circuit. Figure 1-17. Automatic Clock Switchover Circuit Block Diagram
clk0_bad clksw clk0_bad Activeclock clkloss
Clock Sense
Switch-Over State Machine
clkswitch Provides manual switchover support. inclk0 inclk1 muxout Counter refclk fbclk
There possible ways clock switchover feature.
switchover circuitry switching from primary secondary input same frequency. example, applications that require redundant clock with same frequency primary clock, switchover state machine generates signal that controls multiplexer select input shown bottom Figure 1-17. this case, secondary clock becomes reference clock PLL. This automatic switchover feature only works switching from primary secondary clock. CLKSWITCH input user- system-controlled switch conditions. This possible same-frequency switchover switch between inputs different frequencies. example, inclk0 inclk1 MHz, must control switchover because automatic clock-sense circuitry cannot monitor primary secondary clock frequencies with frequency difference more than 20%. This feature useful when clock sources originate from multiple cards backplane, requiring system-controlled switchover between frequencies operation. should choose secondary clock frequency
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operates within recommended range 1,000 MHz. should also counters accordingly keep operating frequency recommended range. Figure 1-18 shows example waveform switchover feature when using automatic clkloss detection. Here, inclk0 signal gets stuck low. After inclk0 signal stuck approximately clock cycles, clock sense circuitry drives clk0_bad signal high. Also, because reference clock signal toggling, clk_loss signal goes low, indicating switch condition. Then, switchover state machine controls multiplexer through clksw signal switch secondary clock.
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Advanced Features
Figure 1-18. Automatic Switchover Upon Clock Loss Detection
inclk0
inclk1
muxout
refclk
fbclk
clk0bad
clk1bad
lock
activeclock
clkloss
Clock Output
Notes Figure 1-18:
number clock edges before allowing switchover determined counter setting. Switchover enabled falling edge INCLK1. rising edge FBCLK causes frequency decrease. rising edge REFCLK starts lock process again, frequency increases.
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switch-over state machine counters that count edges primary secondary clocks; counter0 counts number inclk0 edges counter1 counts number inclk1 edges. counters reset zero when count values reach inclock0 inclock1, respectively. example, counter0 counts edges, count counter1 counts edges before counter0 sees another edge, they both reset some reason counters counts three, means other clock missed edge. clkbad0 clkbad1 signal goes high, switchover circuitry signals switch condition. Figure 1-19. Figure 1-19. Clock-Edge Detection Switchover
Count three single clock indicates other missed edge.
Reset
inclk0
inclk1
clkbad0
Manual Override When using automatic switchover, switch input clocks using manual override feature with clkswitch input. manual override feature available automatic clock switchover different from manual clock switchover.
Figure 1-20 shows example waveform illustrating switchover feature when controlled clkswitch. this case, both clock sources functional inclk0 selected primary clock. clkswitch goes high, which starts switchover sequence. falling edge inclk0, counter's reference clock, muxout, gated prevent clock glitching. falling edge inclk1, reference clock multiplexer switches from inclk0 inclk1 reference. This also when clksw signal changes indicate which clock selected primary which secondary. clkloss signal mirrors clkswitch signal activeclock mirrors clksw this mode. Since both clocks still functional during manual switch, neither clk_bad signal goes high. Since
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Advanced Features
switchover circuit edge-sensitive, falling edge clkswitch signal does cause circuit switch back from inclk1 inclk0. When clkswitch signal goes high again, process repeats. clkswitch automatic switch only work clock being switched available. clock available, state machine waits until clock available. Figure 1-20. Clock Switchover Using CLKSWITCH Control
inclk0
inclk1
muxout
clkswtch
activeclock
clkloss
clk0bad
clk1bad
Figure 1-21 shows simulation using switchover different reference frequencies. this example simulation, reference clock either MHz. begins with allowed lock. clock switched secondary clock, which MHz.
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Figure 1-21. Switchover Simulation
Output Frequency (x10 MHz)
Note
Time
Note Figure 1-21:
This simulation performed under following conditions: counter counter output counter Therefore, operates 100-MHz input references 66-MHz reference input.
Lock Signal-Based Switchover
lock circuitry initiate automatic switchover. This useful cases where input clock still clocking, characteristics have changed that locked switchover enable based both gated ungated lock signals. ungated lock low, switchover enabled until gated lock reached terminal count. must activate switchover enable gated lock high, ungated lock goes low. switchover timing this mode similar waveform shown Figure 1-20 clkswitch control, except switchover enable replaces clkswitch. Figure 1-17 shows switchover enable circuit when controlled lock gated lock. Figure 1-22. Switchover Enable Circuit
Lock Gated Lock Switchover Enable
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Advanced Features
Manual Clock Switchover
Stratix Stratix enhanced fast PLLs support manual switchover, where clkswitch signal controls whether inclk0 inclk1 input clock PLL. clkswitch low, then inclk0 selected; clkswitch high, then inclk1 selected. Figure 1-23 shows block diagram manual switchover circuit fast PLLs. block diagram manual switchover circuit enhanced PLLs shown Figure 1-23. Figure 1-23. Manual Clock Switchover Circuitry Fast PLLs
clkswitch
inclk0 inclk1 muxout
Counter
refclk fbclk
Figure 1-24 shows example waveform illustrating switchover feature when controlled clkswitch. this case, both clock sources functional inclk0 selected primary clock. clkswitch goes high, which starts switch-over sequence. falling edge inclk0, counter's reference clock, muxout, gated prevent clock glitching. rising edge inclk1, reference clock multiplex switches from inclk0 inclk1 reference. When clkswitch signal goes low, process repeats, causing circuit switch back from inclk1 inclk0. Figure 1-24. Manual Switchover
inclk0
inclk1
muxout
clkswitch
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Software Support
Table 1-15 summarizes signals used clock switchover.
Table 1-15. altpll Megafunction Clock Switchover Signals Port
inclk0 inclk1 clkbad0(1) clkbad1(1) clkswitch
Description
Reference clk0 PLL. Reference clk1 PLL.
Source
Destination
Clock switchover circuit Clock switchover circuit Logic array Logic array Clock switchover circuit
Signal indicating that inclk0 longer Clock switchover toggling. circuit Signal indicating that inclk1 longer Clock switchover toggling. circuit Switchover signal used initiate clock Logic array switchover asynchronously. When used manual switchover, clkswitch used select signal between inclk0 inclk1 clswitch inclk0 selected vice versa. Signal indicating that switchover circuit detected switch condition. Signal indicating that lost lock. Clock switchover circuit
clkloss(1) locked activeclock(1)
Logic array Clock switchover circuit Logic array
Signal indicate which clock inclk0, inclk1) driving PLL.
Note Table 1-15:
These ports only available enhanced PLLs auto mode when using automatic switchover.
switchover ports shown Table 1-15 supported altpll megafunction Quartus software. altpll megafunction supports methods clock switchover:
When selecting enhanced PLL, enable both automatic manual switchover, making clock switchover ports available. When selecting fast PLL, only enable manual clock switchover option select between inclk0 inclk1. clkloss, activeclock clkbad0, clkbad1 signals available when manual switchover selected.
primary secondary clock frequencies different, Quartus software selects proper parameters keep within recommended frequency range.
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Advanced Features
more information software support Quartus software, altpll Megafunction User Guide.
Guidelines
following guidelines design with clock switchover PLLs.
When using automatic switchover, clkswitch signal minimum pulse width based reference clock periods. CLKSWITCH pulse width must greater than equal period current reference clock (tfrom_clk) multiplied plus rounded-up version ratio reference clock periods. example, tto_clk equal tfrom_clk, then CLKSWITCH pulse width should least three times period clock pulse. tCLKSWITCHCHmin tfrom_clk intround_up (tto_clk tfrom_clk)]
Applications that require clock switchover feature small frequency drift should low-bandwidth PLL. low-bandwidth reacts slower than high-bandwidth reference input clock changes. When switchover happens, low-bandwidth propagates stopping clock output slower than high-bandwidth PLL. low-bandwidth filters jitter reference clock. However, aware that low-bandwidth also increases lock time. Stratix Stratix device PLLs both automatic clock switchover clkswitch input simultaneously. Therefore, switchover circuitry automatically switch from primary secondary clock. Once primary clock stabilizes again, clkswitch signal switch back primary clock. During switchover, PLL_VCO continues slows down, generating frequency drift outputs. clkswitch signal controls switchover with rising edge only. clock switchover event glitch-free, after switch occurs, there still finite resynchronization period lock onto clock ramps exact amount time takes relock dependent configuration. programmable bandwidth feature adjust relock time. phase relationship between input clock output clock from important your design, assert areset 10ns after performing clock switchover. Wait locked signal gated lock) high before re-enabling output clocks from PLL.
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Figure 1-25 shows frequency gradually decreases when primary clock lost then increases locks secondary clock. After locks secondary clock, some overshoot occur over-frequency condition) frequency.
Figure 1-25. Switchover Operating Frequency
Primary Clock Stops Running Frequency Overshoot
Switchover Occurs Tracks Secondary Clock
Fvco
Disable system during switchover tolerant frequency variations during resynchronization period. There ways disable system. First, system require some time stop before switchover occurs. switchover circuitry includes optional five-bit counter delay when reference clock switched. have option control time-out setting this counter cycles latency) before clock source switches. these cycles disaster recovery. clock output frequency varies slightly during those cycles since still drift without input clock. Programmable bandwidth control response limit drift during this cycle period. second option available ability enable signal (pfdena) along with user-defined control logic. this case clk0_bad clk1_bad status signals turn maintains last frequency. also state machine switch over secondary clock. Upon re-enabling PFD, output clock enable signals (clkena) disable clock outputs during switchover resynchronization period. Once lock indication stable, system re-enable output clock(s).
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Reconfigurable Bandwidth
Reconfigurable Bandwidth
Stratix Stratix enhanced fast PLLs provide advanced control bandwidth using loop's programmable characteristics, including loop filter charge pump.
Background
bandwidth measure PLL's ability track input clock jitter. closed-loop gain 3-dB frequency determines bandwidth. bandwidth approximately unity gain point open loop response. Figure 1-26 shows, these points correspond approximately same frequency. Figure 1-26. Open- Closed-Loop Response Bode Plots
Open-Loop Reponse Bode Plot
Increasing PLL's bandwidth effect pushes open loop response out.
Gain
Frequency
Closed-Loop Reponse Bode Plot
Gain
Frequency
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high-bandwidth provides fast lock time tracks jitter reference clock source, passing through output. low-bandwidth filters reference clock, increases lock time. Stratix Stratix enhanced fast PLLs allow control bandwidth over finite range customize characteristics particular application. programmable bandwidth feature Stratix Stratix PLLs benefits applications requiring clock switchover (e.g., TDMA frequency hopping wireless, redundant clocking). bandwidth stability such system determined charge pump current, loop filter resistor value, high-frequency capacitor value loop filter), m-counter value. Quartus software control these factors bandwidth desired value within given range. bandwidth appropriate value balance need jitter filtering lock time. Figures 1-27 1-28 show output low- high-bandwidth PLL, respectively, locks onto input clock.
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Reconfigurable Bandwidth
Figure 1-27. Low-Bandwidth Lock Time
Lock Time
Frequency (MHz)
Time
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Figure 1-28. High-Bandwidth Lock Time
Lock Time
Frequency (MHz)
Time
high-bandwidth benefit system that cascaded PLLs. first uses spread spectrum user-induced jitter), second track jitter that feeding using high-bandwidth setting. low-bandwidth can, this case, lose lock spread-spectrum-induced jitter input clock. low-bandwidth benefits system using clock switchover. When clock switchover happens, input temporarily stops. low-bandwidth would react more slowly changes input clock take longer drift lower frequency (caused input stopping) than high-bandwidth PLL. Figures 1-29 1-30 demonstrate this property. plots show effects clock switchover with low- high-bandwidth PLL. When clock switchover happens, output low-bandwidth (see Figure 1-29) drifts lower frequency more slowly than high-bandwidth output (see Figure 1-30).
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Reconfigurable Bandwidth
Figure 1-29. Effect Bandwidth Clock Switchover
Frequency (MHz) Input Clock Stops Re-lock
Initial Lock
Switchover
Time
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Figure 1-30. Effect High Bandwidth Clock Switchover
Input Clock Stops Re-lock
Initial Lock
Frequency (MHz)
Switchover
Time
Implementation
Traditionally, external components such loop filter control PLL's bandwidth. Most loop filters made passive components such resistors capacitors that take unnecessary board space increase cost. With Stratix Stratix PLLs, components contained within device increase performance decrease cost. Stratix Stratix device PLLs implement reconfigurable bandwidth giving control charge pump current loop filter resistor high-frequency capacitor values (see Table 1-16). Stratix Stratix device enhanced bandwidth ranges from 16.9 MHz. Stratix Stratix device fast bandwidth ranges from 1.16 MHz.
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Reconfigurable Bandwidth
charge pump current directly affects bandwidth. higher charge pump current, higher bandwidth. choose from fixed values charge pump current. Figure 1-31 shows loop filter components that through Quartus software. components loop filter resistor, high frequency capacitor, charge pump current, IDN. Figure 1-31. Loop Filter Programmable Components
Software Support
Quartus software provides levels bandwidth control. Megafunction-Based Bandwidth Setting first level programmable bandwidth allows enter value desired bandwidth directly into Quartus software using altpll megafunction. also bandwidth parameter altpll megafunction desired bandwidth. Quartus software selects best bandwidth parameters available match your bandwidth request. individual bandwidth setting request available, Quartus software selects closest achievable value. Advanced Bandwidth Setting advanced level control also possible using advanced loop filter parameters. dynamically change charge pump current, loop filter resistor value, loop filter (high frequency) capacitor value.
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parameters these changes are: charge_pump_current, loop_filter_r, loop_filter_c. Each parameter supports specific range values listed Table 1-16.
Table 1-16. Advanced Loop Filter Parameters Parameter
Resistor values High-frequency capacitance values (pF) Charge pump current settings Note Table 1-16:
more information, 367: Implementing Reconfiguration Stratix Devices.
Values
more information Quartus software support reconfigurable bandwidth, Reconfiguration section Quartus Handbook. PLLs several divide counters different phase taps perform frequency synthesis phase shifts. Stratix Stratix enhanced fast PLLs, counter value phase configurable real time. addition, change loop filter charge pump components, which affect bandwidth, fly. control these components update output clock frequency, bandwidth, phase-shift variation real time, without need reconfigure entire FPGA. more information reconfiguration, 367: Implementing Reconfiguration Stratix Devices.
Reconfiguration
SpreadSpectrum Clocking
Digital clocks square waves with short rise times duty cycle. These high-speed clocks concentrate significant amount energy narrow bandwidth target frequency higher frequency harmonics. This results high energy peaks increased electromagnetic interference (EMI). radiated noise from energy peaks travels free and, minimized, lead corrupted data intermittent system errors, which jeopardize system reliability. Traditional methods limiting include shielding, filtering, multi-layer printed circuit boards (PCBs). However, these methods significantly increase overall system cost sometimes enough meet compliance. Spread-spectrum technology provides with simple effective technique reducing without additional cost trouble re-designing board.
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Spread-Spectrum Clocking
Spread-spectrum technology modulates target frequency over small range. example, 100-MHz signal 0.5% down-spread modulation, then frequency swept from 99.5 MHz. Figure 1-32 gives graphical representation energy present spread-spectrum signal non-spread spectrum-signal. apparent that instead concentrating energy target frequency, energy re-distributed across wider band frequencies, which reduces peak energy. only there reduction fundamental peak components, there also reduction higher order harmonics. Since some regulations focus peak emissions, rather than average emissions, spread-spectrum technology valuable method reduction. Figure 1-32. Spread-Spectrum Signal Energy Versus Non-Spread-Spectrum Signal Energy
Spread-Spectrum Signal Non-Spread-Spectrum Signal
Amplitude (dB)
0.5%
Frequency (MHz)
Spread-spectrum technology would benefit design with high emissions and/or strict requirements. Device-generated dependent frequency output voltage swing amplitude edge rate. example, design using LVDS already emissions because low-voltage swing. differential LVDS signal also allows rejection within signal. Therefore, this situation require spread-spectrum technology. Spread-spectrum clocking only supported Stratix enhanced PLLs, fast PLLs.
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Implementation
Stratix Stratix device enhanced PLLs feature spread-spectrum technology reduce EMIs emitted from device. enhanced provides approximately 0.5% down spread using triangular, also known linear, modulation profile. modulation frequency programmable ranges from approximately kHz. spread percentage based clock input settings. Spread-spectrum technology reduces peak energy four target frequency. However, this number dependent bandwidth counter values vary from design design. Spread percentage, also known modulation width, defined percentage that design modulates target frequency. negative percentage indicates down spread, positive percentage indicates spread, indicates center spread. Modulation frequency frequency spreading signal, fast signal sweeps from minimum maximum frequency. Down-spread modulation shifts target frequency down half spread percentage, centering modulated waveforms target frequency. counter values toggled same time between fixed values. loop filter then slowly changes frequency provide spreading effect, which results triangular modulation. additional spread-spectrum counter (shown Figure 1-33) sets modulation frequency. Figure 1-33 shows spread-spectrum technology implemented Stratix Stratix device enhanced PLL.
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Spread-Spectrum Clocking
Figure 1-33. Stratix Stratix Spread-Spectrum Circuit Block Diagram
refclk Down SpreadSpectrum Counter count1 count2
count1
count2
Figure 1-34 shows frequency waveform when toggling between different counter values. Since enhanced switches between different values, result straight line between frequencies, which gives linear modulation. magnitude modulation determined ratio sets. percent spread determined percent spread (fVCOmax fVCOmin)/fVCOmax [(m2 n1)/(m1 n2)]. maximum minimum frequency defined fVCOmax (m1/n1) fREF fVCOmin (m2/n2) fREF Figure 1-34. Frequency Modulation Waveform
count2 values count1 values
Frequency
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Software Support
enter desired down-spread percentage modulation frequency altpll megafunction through Quartus software. Alternatively, downspread parameter altpll megafunction desired down-spread percentage. Timing analysis ensures design operates maximum spread frequency meets timing requirements.
more information software support Quartus software, altpll Megafunction User Guide.
Guidelines
design cascades PLLs, source (upstream) should have low-bandwidth setting, while destination (downstream) should have high-bandwidth setting. upstream must have low-bandwidth setting because does generate jitter higher than bandwidth. downstream must have high bandwidth setting track jitter. design must spread-spectrum feature low-bandwidth PLL, and, therefore, Quartus software automatically sets spread-spectrum bandwidth low. programmable reconfigurable bandwidth features used, then cannot spread spectrum.
Stratix Stratix devices accept spread-spectrum input with typical modulation frequencies. However, device cannot automatically detect that input spread-spectrum signal. Instead, input signal looks like deterministic jitter input downstream PLL. Spread spectrum have minor effect output clock increasing period jitter. Period jitter deviation clock's cycle time from previous cycle position. Period jitter measures variation clock output transition from ideal position over consecutive edges. With down-spread modulation, peak modulated waveform actual target frequency. Therefore, system never exceeds maximum clock speed. maintain reliable communication, entire system subsystem should Stratix Stratix device clock source. Communication could fail Stratix Stratix logic array clocked spread-spectrum clock, data receives from another device clocked spread spectrum.
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Board Layout
Since spread spectrum affects counter values, spread-spectrum outputs effected. Therefore, only spread-spectrum signal needed, clock signal should separate without other outputs from that PLL. special considerations needed when using spread spectrum with clock switchover feature. This because clock switchover feature does affect counter values, which counter values switching when using spread spectrum.
Board Layout
enhanced fast circuits Stratix Stratix devices contain analog components embedded digital device. These analog components have separate power ground pins minimize noise generated digital components. Stratix Stratix enhanced fast PLLs separate ground pins isolate circuitry improve noise resistance.
VCCA GNDA
Each enhanced fast uses separate ground pairs their analog circuitry. analog circuit power ground each called VCCA_PLL<PLL number> GNDA_PLL<PLL number>. Connect VCCA power 1.2-V power supply, even PLL. Isolate power connected VCCA from power rest Stratix Stratix device other digital device board. three different methods isolating VCCA pin: separate VCCA power planes, partitioned VCCA island within VCCINT plane, thick VCCA traces.
Separate VCCA Power Plane
mixed signal system already partitioned into analog digital sections, each with power planes board. isolate VCCA using separate VCCA power plane, connect VCCA analog 1.2-V power plane.
Partitioned VCCA Island Within VCCINT Plane
Fully digital systems have separate analog power plane board. Since expensive planes board, create islands VCCA_PLL. Figure 1-35 shows example board layout with analog power island. dielectric boundary that creates island should mils thick. Figure 1-36 shows partitioned plane within VCCINT VCCA.
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Figure 1-35. VCCINT Plane Partitioned VCCA Island
Thick VCCA Trace
Because board constraints, able partition VCCA island. Instead, thick trace from power supply each VCCA pin. traces should least mils thick. each these three cases, should filter each VCCA_PLL with decoupling circuit, shown Figure 1-36. Place ferrite bead that exhibits high impedance frequencies higher 10-F tantalum parallel capacitor where power enters board. Decouple each VCCA_PLL with 0.1-F 0.001-F parallel combination ceramic capacitors located close possible Stratix Stratix device. connect GNDA_PLL pins directly same ground plane device's digital ground.
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Board Layout
Figure 1-36. Power Schematic Stratix Stratix PLLs
Ferrite Bead
1.2-V Supply
VCCA_PLL
0.001
GNDA_PLL
VCCINT VCCD_PLL
Repeat Each Power Ground
Stratix Device
Note Figure 1-36
Applies PLLs through
VCCD
digital power ground pins labeled VCCD_PLL<PLL number> GND. VCCD supplies power digital circuitry PLL. Connect these VCCD pins quietest digital supply board. most systems, this digital 1.2-V supply supplied device's VCCINT pins. Connect VCCD pins power supply even PLL. When connecting VCCD pins VCCINT, need filtering isolation. connect pins directly same ground plane device's digital ground. Figure 1-36.
External Clock Output Power
Enhanced PLLs also have isolated power pins their dedicated external clock outputs (VCC_PLL5_OUT, VCC_PLL6_OUT, VCC_PLL11_OUT VCC_PLL12_OUT, respectively). Since
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dedicated external clock outputs from particular enhanced powered separate power pins, they less susceptible noise. They also reduce overall jitter output clock providing improved isolation from switching pins. pins that reside banks through powered VCC_PLL<5, 12>_OUT pins, respectively. EP2S60F484, EP2S60F780, EP2S90H484, EP2S90F780, EP2S130F780 devices support PLLs Therefore, pins that reside bank powered VCCIO3 pin, pins that reside bank powered VCCIO8 pin.
VCC_PLL_OUT pins powered 3.3, 2.5, 1.8, depending standard clock output from particular enhanced PLL, shown Figure 1-37.
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Board Layout
Figure 1-37. External Clock Output Association with Output Power
VCC_PLL5_OUT
PLL5_OUT0p
PLL5_OUT0n
PLL5_OUT1p
PLL5_OUT1n
PLL5_OUT2p
PLL5_OUT2n
Filter each isolated power with decoupling circuit shown Figure 1-38. Decouple isolated power pins with parallel combination 0.1- 0.001-F ceramic capacitors located close possible Stratix Stratix device.
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Figure 1-38. Stratix Stratix External Clock Output Power Ball Connection Note
VCCIO Supply
VCC_PLL#_OUT
0.001
VCC_PLL#_OUT
0.001
Stratix Stratix Device
Note Figure 1-38:
Applies only enhanced PLLs
Guidelines
following guidelines optimal jitter performance external clock outputs from enhanced PLLs outputs running same frequency, these guidelines necessary improve performance.
phase shift ensure edges coincident clock outputs. phase shift skew clock edges with respect each other best jitter performance.
cannot drive multiple clocks different frequencies phase shifts isolate banks, should control drive capability lower-frequency clock. Reducing much current output buffer supply reduce noise. Minimize capacitive load slower frequency output configure output buffer lower current strength. higher-frequency output should have improved performance, this degrade performance your lowerfrequency clock output.
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Specifications
Specifications
Switching Characteristics chapter volume Stratix Device Handbook Stratix Device Handbook information timing specifications Stratix Stratix devices provide hierarchical clock structure multiple PLLs with advanced features. large number clocking resources combination with clock synthesis precision provided enhanced fast PLLs provides complete clock-management solution.
Clocking
Global Hierarchical Clocking
Stratix Stratix devices provide dedicated global clock networks regional clock networks. These clocks organized into hierarchical clock structure that allows unique clock sources device quadrant with skew delay. This hierarchical clocking scheme provides unique clock domains within entire Stratix Stratix device. Table 1-17 lists clock resources available Stratix devices. There dedicated clock pins (CLK[15.0]) Stratix Stratix devices drive either global regional clock networks. Four clock pins drive each side Stratix device, shown Figures 1-39 1-40. Enhanced fast outputs also drive global regional clock networks.
Table 1-17. Clock Resource Availability Stratix Stratix Devices (Part Description
Number clock input pins Number global clock networks Number regional clock networks Global clock input sources Regional clock input sources Number unique clock sources quadrant Number unique clock sources entire device Clock input pins, outputs, logic array Clock input pins, outputs, logic array global clocks regional clocks) global clocks regional clocks)
Stratix Device Availability
Stratix Device Availability
Clock input pins, outputs, logic array, inter-transceiver clocks Clock input pins, outputs, logic array, inter-transceiver clocks GCLK RCLK clocks) GCLK RCLK clocks)
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Table 1-17. Clock Resource Availability Stratix Stratix Devices (Part Description
Power-down mode Clocking regions high fan-out applications
Stratix Device Availability
Stratix Device Availability
Global clock networks, regional clock GCLK, RCLK networks, dual-regional networks, dual-regional clock region clock region Quadrant region, dual-regional, entire device global clock regional clock networks Quadrant region, dual-regional, entire device GCLK RCLK networks
Global Clock Network
Global clocks drive throughout entire device, feeding device quadrants. resources within device IOEs, adaptive logic modules (ALMs), digital signal processing (DSP) blocks, memory blocks global clock networks clock sources. These resources also used control signals, such clock enables synchronous asynchronous clears external pin. Internal logic also drive global clock networks internally generated global clocks asynchronous clears, clock enables, other control signals with large fanout. Figure 1-39 shows dedicated pins driving global clock networks. Figure 1-39. Global Clocking Note
CLK12-15 GCLK12
CLK0-3
GCLK0-3
GCLK8-11
CLK8-11
GCLK4-7
CLK4-7
Note Figure 1-39:
Stratix devices have PLLs clock pins
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Clocking
Regional Clock Network
Eight regional clock networks within each quadrant Stratix Stratix device driven dedicated CLK[15.0]input pins from outputs. regional clock networks only pertain quadrant they drive into. regional clock networks provide lowest clock delay skew logic contained within single quadrant. Internal logic also drive regional clock networks internally generated regional clocks asynchronous clears, clock enables, other control signals with large fanout.The clock pins symmetrically drive RCLK networks within particular quadrant, shown Figure 1-40. Refer Table 1-18 page 1-67 Table 1-19 page 1-68 RCLK connections from pins PLLs. Figure 1-40. Regional Clocking Note
CLK12-15
RCLK24-27
RCLK28-31
RCLK0-3
RCLK20-23
CLK0
RCLK4-7
RCLK16-19
CLK8-11
RCLK8-11 RCLK12-15
CLK4-7
Note Figure 1-40:
Stratix devices have PLLs clock pins
Clock Sources Region
Each Stratix Stratix device global clock networks regional clock networks that provide unique clock domains entire device. There unique clocks available each quadrant global clocks regional clocks) input resources registers (see Figure 1-41).
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Figure 1-41. Hierarchical Clock Networks Quadrant
Clocks Available Quadrant Half-Quadrant
Global Clock Network [15.0] Clock [23.0] Regional Clock Network [7.0] Cell IO_CLK[7.0] Clock [5.0] Column Cell IO_CLK[7.0]
Stratix Stratix clock networks provide three different clocking regions:
Entire device clock region Quadrant clock region Dual-regional clock region
These clock network options provide more flexibility routing signals that have high fan-out improve interface timing. having various sized clock regions, possible prioritize number registers network reach versus total delay network. first clock scheme, source (not necessarily clock signal) drives global clock network that routed through entire device. This maximum delay skew high fan-out signal allows signal reach every block within device. This good option routing global resets clear signals. second clock scheme, source drives single-quadrant region. This represents fastest, low-skew, high-fan-out signal-routing resource within quadrant. limitation this resource that only covers single quadrant. third clock scheme, single source (clock output) generate dual-regional clock driving regional clock network lines (one from each quadrant). This allows logic that spans multiple quadrants utilize same low-skew clock. routing this signal entire side approximately same speed quadrant clock region. internal logic-array routing that drive regional clock also supports this feature. This means internal logic drive
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Clocking
dual-regional clock network. Corner fast outputs only span quadrant hence cannot form dual-regional clock network. Figure 1-42 shows this feature pictorially. Figure 1-42. Stratix Stratix Dual-Regional Clock Region
Clock pins outputs drive half device create dual-reginal clocking regions improved interface timing.
clock input pins, enhanced fast outputs, internal logic array clock input sources drive onto either global regional clock networks. CLKn pins also drive global clock network shown Table 1-22 page 1-72. Tables 1-18 1-19 connectivity between pins well global regional clock networks. Clock Inputs clock input pins CLK[15.0] also used high fan-out control signals, such asynchronous clears, presets, clock enables, protocol signals such TRDY IRDY through global regional clock networks. Internal Logic Array Each global regional clock network also driven logic-array routing enable internal logic drive high fan-out, low-skew signal. Outputs clock networks driven counter outputs.
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Table 1-18 shows connection clock pins global clock resources. reason higher level connectivity support user controllable global clock multiplexing.
Table 1-18. Clock Input Connectivity Global Clock Networks CLK(p) (Pin) Clock Resource
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 GCLK8 GCLK9 GCLK10 GCLK11 GCLK12 GCLK13 GCLK14 GCLK15 Note Table 1-18:
Clock pins available Stratix devices. Therefore, these connections exist Stratix devices.
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Clocking
Table 1-19 summarizes connectivity between clock pins regional clock networks. Here, each clock drive regional clock networks, facilitating stitching clock networks support ability drive quadrants with same clock signal.
Table 1-19. Clock Input Connectivity Regional Clock Networks (Part CLK(p) (Pin) Clock Resource
RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 RCLK16 RCLK17 RCLK18 RCLK19 RCLK20 RCLK21 RCLK22
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Table 1-19. Clock Input Connectivity Regional Clock Networks (Part CLK(p) (Pin) Clock Resource
RCLK23 RCLK24 RCLK25 RCLK26 RCLK27 RCLK28 RCLK29 RCLK30 RCLK31 Note Table 1-19:
Clock pins available Stratix devices. Therefore, these connections exist Stratix devices.
Clock Input Connections
Four pins drive each enhanced PLL. pins clock switchover inputs into PLL. pins primary clock source clock switchover, which controlled Quartus software. Enhanced PLLs also have feedback input pins, shown Table 1-20. Input clocks fast PLLs come from pins. multiplexer chooses possible pins drive each PLL. This multiplexer clock switchover multiplexer only used clock input connectivity. Either FPLLCLK input drive fast PLLs corners when used general-purpose applications. pins cannot drive these fast PLLs high-speed differential mode.
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Clocking
Tables 1-20 1-21 show which PLLs available each Stratix Stratix device, respectively, which input clock drives which PLLs.
Table 1-20. Stratix Device PLLs Clock Drivers (Part Devices Input
CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLK11 CLK12 CLK13 CLK14 CLK15 PLL5_FB PLL6_FB PLL11_FB PLL12_FB PLL_ENA FPLL7CLK FPLL8CLK FPLL9CLK
EP2S60 EP2S180 Devices Enhanced PLLs Fast PLLs Enhanced PLLs
Fast PLLs
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Table 1-20. Stratix Device PLLs Clock Drivers (Part Devices Input
FPLL10CLK Notes Table 1-20:
Clock connection available. more information maximum frequency, contact Altera Applications. This dedicated high-speed clock input. more information maximum frequency, contact Altera Applications.
EP2S60 EP2S180 Devices Enhanced PLLs Fast PLLs
Fast PLLs
Enhanced PLLs
Table 1-21. Stratix Device PLLs Clock Drivers (Part Devices Input
CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 (3), CLK10 CLK11 (3), CLK12 CLK13 CLK14 CLK15 PLL5_FB PLL6_FB PLL11_FB
EP2SGX60 EP2SGX130 Devices Enhanced PLLs
v(2) v(2) v(2) v(2)
Fast PLLs
Fast PLLs
v(2) v(2) v(2) v(2)
Enhanced PLLs
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Clocking
Table 1-21. Stratix Device PLLs Clock Drivers (Part Devices Input
PLL12_FB PLL_ENA FPLL7CLK FPLL8CLK FPLL9CLK FPLL10CLK Notes Table 1-21:
PLLs available Stratix devices. Clock connection available. more information maximum frequency, contact Altera Applications. This dedicated high-speed clock input. more information maximum frequency, contact Altera Applications. Input pins CLK[11.8] available Stratix devices.
EP2SGX60 EP2SGX130 Devices Enhanced PLLs
Fast PLLs
Fast PLLs
Enhanced PLLs
CLK(n) Connectivity Global Clock Networks
Stratix Stratix devices, clk(n) pins also feed global clock network. Table 1-22 shows clk(n) connectivity global clock networks.
Table 1-22. CLK(n) Connectivity Global Clock Network
Clock Resource
CLK(n)
GCLK4 GCLK5 GCLK6 GCLK7 GCLK12 GCLK13 GCLK14 GCLK15
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Clock Source Control Enhanced PLLs
clock input multiplexer enhanced PLLs shown Figure 1-43. This block allows selection clock reference from several different sources. clock source enhanced come from four clock input pins CLK[3.0], from logic-array clock, provided logic array clock driven output from another PLL, pin-driven dedicated global regional clock, through clock control block, provided clock control block output from another pin-driven dedicated global regional clock. internally generated global signal cannot drive PLL. clock input connections respective enhanced PLLs shown Table 1-20 above. multiplexer select lines configuration file only. Once programmed, this block cannot changed without loading configuration file. Quartus software automatically sets multiplexer select signals depending clock sources that user selects design. Figure 1-43. Enhanced Clock Input Multiplex Logic
clk[3.0] core_inclk inclk0
Clock Switchover Block
inclk1
Note Figure 1-43:
input clock multiplexing controlled through configuration file only cannot dynamically controlled user mode.
Clock Source Control Fast PLLs
Each center fast five clock input sources, four from clock input pins, from logic array signal, provided logic array signal driven output from another PLL, pin-driven dedicated global regional clock, through clock control block, provided clock control block output from another pin-driven dedicated global regional clock. internally generated global signal cannot drive PLL. When using clock input pins clock source, perform manual clock switchover among input clock sources.
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Clocking
clock input multiplexer control signals performing clock switchover from core signals. Figure 1-44 shows clock input multiplexer control circuit center fast PLL. Figure 1-44. Center Fast Clock Input Multiplexer Control
core_inclk clk[3.0] inclk0
Clock Switchover Block
inclk1
core_inclk
Note Figure 1-44:
input clock multiplexing controlled through configuration file only cannot dynamically controlled user mode.
Each corner fast three clock input sources, from dedicated corner clock input pin, from center clock input pin, from logic array clock, provided logic array signal driven output from another PLL, pin-driven dedicated global regional clock, through clock control block, provided clock control block output from another pin-driven dedicated global regional clock. internally generated global signal cannot drive PLL. Figure 1-45 shows block diagram showing clock input multiplexer control circuit corner fast PLL. Only corner FPLLCLK fully compensated. Figure 1-45. Corner Fast Clock Input Multiplexer Control
core_inclk
FPLLCLK inclk0
Center Clocks
Clock Switchover Block
inclk1
core_inclk
Note Figure 1-45:
input clock multiplexing controlled through configuration file only cannot dynamically controlled user mode.
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Delay Compensation Fast PLLs
Each center fast four possible input clock pins. Among four clock input signals, only fully compensated, i.e., clock delay fast matches delay data input path when used LVDS receiver mode. clock inputs that match data input path located right next fast PLL. clock inputs that match data input path located next neighboring fast PLL. Figure 1-46 shows above description left-side center fast pair. used non-LVDS modes, then four dedicated clock inputs used compensated. Fast choose among CLK[3.0] clock input source. However, fast only CLK0 CLK1 have their delay matched data input path delay when used LVDS receiver mode operation. delay from CLK2 CLK3 fast does match data input delay. fast only CLK2 CLK3 have their delay matched data input path delay LVDS receiver mode operation. delay from CLK0 CLK1 fast does match data input delay. same arrangement applies right side center fast pair. corner fast PLLs, only corner FPLLCLK pins fully compensated. LVDS receiver operation, recommended delay compensated clock pins only. Figure 1-46. Delay Compensated Clock Input Pins Center Fast Pair
CLK0
CLK1
Fast
Fast
CLK2
CLK3
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Clocking
Clock Output Connections
Enhanced PLLs have outputs eight regional clock outputs four global clock outputs. There line sharing between clock pins, global regional clock networks outputs. Tables 1-18 through 1-23 Figures 1-47 through 1-53 validate your clocking scheme. Quartus software automatically maps regional global clocks avoid restrictions. Enhanced PLLs drive single-ended pins shown Table 1-23. connect each fast output (C0, either global regional clock. There line sharing between clock pins, FPLLCLK pins, global regional clock networks, outputs. Quartus software will automatically regional global clocks avoid restrictions. Figure 1-47 shows clock input output connections from enhanced PLLs. EP2S15, EP2S30, EP2SGX30 devices have only enhanced PLLs connectivity from these PLLs global regional clock networks remains same. EP2S60 device 1,020-pin package contains PLLs. EP2S60 devices 484-pin 672-pin packages contain fast PLLs enhanced PLLs EP2S90 devices 1020-pin 1508-pin packages contain PLLs. EP2S90 devices 484-pin 780-pin packages contain fast PLLs enhanced PLLs EP2S130 devices 1020-pin 1508-pin packages contain PLLs. EP2S130 device 780-pin package contains fast PLLs enhanced PLLs
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Figure 1-47. Stratix Stratix Bottom Enhanced PLLs, Clock Logic Array Signal Connectivity Global Regional Clock Networks Notes
CLK13 CLK12 CLK15 CLK14
PLL11_FB
PLL5_FB
PLL11_OUT[2.0]p PLL11_OUT[2.0]n
PLL5_OUT[2.0]p PLL5_OUT[2.0]n RCLK31 RCLK30 RCLK29 RCLK28
Regional Clocks
RCLK27 RCLK26 RCLK25 RCLK24
Global Clocks
Regional Clocks
RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 PLL6_OUT[2.0]p PLL6_OUT[2.0]n
PLL12_OUT[2.0]p PLL12_OUT[2.0]n
PLL12_FB CLK4 CLK5 CLK6 CLK7
PLL6_FB
Note Figure 1-47:
redundant connection dots facilitate stitching clock networks support ability drive quadrants with same clock. enhanced PLLs also driven through global regional clock networks. global regional clock input driven output from another PLL, pin-driven dedicated global regional clock, through clock control block, provided clock control block output from another pin-driven dedicated global regional clock. internally generated global signal cannot drive PLL.
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Clocking
Tables 1-23 1-24 show global regional clocks that outputs drive.
Table 1-23. Stratix Global Regional Clock Outputs From PLLs (Part Number Type EP2S15 through EP2S30 Devices Clock Network Fast PLLs
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 GCLK8 GCLK9 GCLK10 GCLK11 GCLK12 GCLK13 GCLK14 GCLK15 RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RCLK9
EP2S60 through EP2S180 Devices Fast PLLs
Enhanced PLLs
Enhanced PLLs
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Table 1-23. Stratix Global Regional Clock Outputs From PLLs (Part Number Type EP2S15 through EP2S30 Devices Clock Network Fast PLLs
RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 RCLK16 RCLK17 RCLK18 RCLK19 RCLK20 RCLK21 RCLK22 RCLK23 RCLK24 RCLK25 RCLK26 RCLK27 RCLK28 RCLK29 RCLK30 RCLK31
EP2S60 through EP2S180 Devices Fast PLLs Enhanced PLLs
Enhanced PLLs
External Clock Output
PLL5_OUT[3.0]p/ PLL6_OUT[3.0]p/
Altera Corporation 2007
1-79 Stratix Device Handbook, Volume
Clocking
Table 1-23. Stratix Global Regional Clock Outputs From PLLs (Part Number Type EP2S15 through EP2S30 Devices Clock Network Fast PLLs
PLL11_OUT[3.0]p PLL12_OUT[3.0]p
EP2S60 through EP2S180 Devices Fast PLLs Enhanced PLLs
Enhanced PLLs
Table 1-24. Stratix Global Regional Clock Outputs From PLLs (Part Number Type EP2SGX30 Devices Clock Network Fast PLLs
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 GCLK8 GCLK9 GCLK10 GCLK11 GCLK12 GCLK13 GCLK14 GCLK15
EP2SGX60 through EP2SGX130 Devices Notes (2), (3), Fast PLLs
Enhanced PLLs
Enhanced PLLs
10(1)
1-80 Stratix Device Handbook, Volume
Altera Corporation 2007
PLLs Stratix Stratix Devices
Table 1-24. Stratix Global Regional Clock Outputs From PLLs (Part Number Type EP2SGX30 Devices Clock Network Fast PLLs
RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 RCLK16 RCLK17 RCLK18 RCLK19 RCLK20 RCLK21 RCLK22 RCLK23 RCLK24 RCLK25 RCLK26 RCLK27
EP2SGX60 through EP2SGX130 Devices Notes (2), (3), Fast PLLs
Enhanced PLLs
Enhanced PLLs
10(1)
Altera Corporation 2007
1-81 Stratix Device Handbook, Volume
Clocking
Table 1-24. Stratix Global Regional Clock Outputs From PLLs (Part Number Type EP2SGX30 Devices Clock Network Fast PLLs
RCLK28 RCLK29 RCLK30 RCLK31
EP2SGX60 through EP2SGX130 Devices Notes (2), (3), Fast PLLs 10(1) Enhanced PLLs
Enhanced PLLs
External Clock Output
PLL5_OUT[3.0]p PLL6_OUT[3.0]p PLL11_OUT[3.0] PLL12_OUT[3.0]
Note Table 1-24:
PLLs available Stratix devices. EP2S60 device 1
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