SII52004-4.5 This chapter provides guidelines using industry stan

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

SII52004-4.5 This chapter provides guidelines using industry stan

Datasheet Thumbnail

Top Searches for this datasheet

Selectable Standards Stratix Stratix Devices
SII52004-4.5
This chapter provides guidelines using industry standards Stratix® Stratix devices, including:
features standards External memory interfaces banks Design considerations
Stratix Stratix Features
Stratix Stratix devices contain abundance adaptive logic modules (ALMs), embedded memory, high-bandwidth digital signal processing (DSP) blocks, extensive routing resources, which operate very high core speed. Stratix Stratix devices structure designed ensure that these internal capabilities fully utilized. There numerous features assist high-speed data transfer into device including:
Single-ended, non-voltage-referenced voltage-referenced standards High-speed differential standards featuring serializer/deserializer (SERDES), dynamic phase alignment (DPA), capable gigabit second (Gbps) performance low-voltage differential signaling (LVDS), Hypertransport technology, HSTL, SSTL, LVPECL
HSTL SSTL standards used only clock inputs outputs differential mode. LVPECL supported clock input outputs bottom banks.
Double data rate (DDR) pins Programmable output drive strength voltage-referenced non-voltage-referenced single-ended standards Programmable bus-hold Programmable pull-up resistor Open-drain output On-chip series termination On-chip parallel termination
Altera Corporation 2007
Stratix Stratix Standards Support
On-chip differential termination Peripheral component interconnect (PCI) clamping diode socketing
detailed description each feature, refer Stratix Architecture chapter volume Stratix Device Handbook Stratix Architecture chapter volume Stratix Device Handbook. Stratix Stratix devices support wide range industry standards. Table shows which standards Stratix devices support well typical applications.
Stratix Stratix Standards Support
Table 4-1. Stratix Stratix Standard Applications (Part Standard
LVTTL LVCMOS 3.3-V 3.3-V PCI-X SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class Differential SSTL-18 Class 1.8-V differential HSTL Class 1.8-V differential HSTL Class 1.5-V differential HSTL Class
Application
General purpose General purpose General purpose General purpose General purpose embedded system embedded system SDRAM SDRAM DDR2 SDRAM DDR2 SDRAM QDRII SRAM/RLDRAM II/SRAM QDRII SRAM/RLDRAM II/SRAM QDRII SRAM/SRAM QDRII SRAM/SRAM General purpose SDRAM SDRAM DDR2 SDRAM DDR2 SDRAM Clock interfaces Clock interfaces Clock interfaces
Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Table 4-1. Stratix Stratix Standard Applications (Part Standard
1.5-V differential HSTL Class LVDS HyperTransporttechnology Differential LVPECL
Application
Clock interfaces High-speed communications interfaces Video graphics clock distribution
Single-Ended Standards
non-voltage-referenced single-ended standards, voltage input must above voltage considered "on" (high, logic value below another voltage considered "off" (low, logic value Voltages between limits undefined logically, fall into either logic value non-voltage-referenced single-ended standards supported Stratix Stratix devices are:
Low-voltage transistor-transistor logic (LVTTL) Low-voltage complementary metal-oxide semiconductor (LVCMOS) 3.3-V 3.3-V PCI-X
Voltage-referenced, single-ended standards provide faster data rates. These standards constant reference voltage input levels. incoming signals compared with this constant voltage difference between defines "on" "off" states. Stratix Stratix devices support stub series terminated logic (SSTL) high-speed transceiver logic (HSTL) voltage-referenced standards.
LVTTL
LVTTL standard formulated under EIA/JEDEC Standard, JESD8-B (Revision JESD8-A): Interface Standard Nominal 3-V/3.3-V Supply Digital Integrated Circuits. standard defines interface parameters digital circuits operating from 3.0- 3.3-V power supply driving being driven LVTTL-compatible devices. 3.3-V LVTTL standard
Altera Corporation 2007
Stratix Device Handbook, Volume
Stratix Stratix Standards Support
general-purpose, single-ended standard used 3.3-V applications. This standard does require input reference voltages (VREF) termination voltages (VTT). Stratix Stratix devices support both input output levels 3.3-V LVTTL operation.
Stratix Stratix devices support VCCIO voltage level specified narrow range voltage supply EIA/JEDEC standard. LVCMOS LVCMOS standard formulated under EIA/JEDEC Standard, JESD8-B (Revision JESD8-A): Interface Standard Nominal 3-V/3.3-V Supply Digital Integrated Circuits. standard defines interface parameters digital circuits operating from 3.0- 3.3-V power supply driving being driven LVCMOS-compatible devices. 3.3-V LVCMOS standard general-purpose, single-ended standard used 3.3-V applications. While LVCMOS output specification, specifies same input voltage requirements LVTTL. These standards require VREF VTT. Stratix Stratix devices support both input output levels 3.3-V LVCMOS operation.
Stratix Stratix devices support VCCIO voltage level specified narrow range voltage supply EIA/JEDEC standard.
2.5-V standard formulated under EIA/JEDEC Standard, EIA/JESD8-5: 2.5-V± 0.2-V (Normal Range), 1.8-V 2.7-V (Wide Range) Power Supply Voltage Interface Standard Non-Terminated Digital Integrated Circuit. standard defines interface parameters high-speed, low-voltage, non-terminated digital circuits driving being driven other 2.5-V devices. This standard general-purpose, single-ended standard used 2.5-V applications. does require VREF VTT.
Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Stratix Stratix devices support both input output levels 2.5-V operation with VCCIO voltage level support which narrower than defined Normal Range EIA/JEDEC standard.
1.8-V standard formulated under EIA/JEDEC Standard, EIA/JESD8-7: 1.8-V± 0.15-V (Normal Range), 1.2-V 1.95-V (Wide Range) Power Supply Voltage Interface Standard Non-Terminated Digital Integrated Circuit. standard defines interface parameters high-speed, low-voltage, non-terminated digital circuits driving being driven other 1.8-V devices. This standard general-purpose, single-ended standard used 1.8-V applications. does require VREF VTT. Stratix Stratix devices support both input output levels 1.8-V operation with VCCIO voltage level support which narrower than defined Normal Range EIA/JEDEC standard.
1.5-V standard formulated under EIA/JEDEC Standard, JESD8-11: 1.5-V± 0.1-V (Normal Range) 0.9-V 1.6-V (Wide Range) Power Supply Voltage Interface Standard Non-Terminated Digital Integrated Circuit. standard defines interface parameters high-speed, low-voltage, non-terminated digital circuits driving being driven other 1.5-V devices. This standard general-purpose, single-ended standard used 1.5-V applications. does require VREF VTT. Stratix Stratix devices support both input output levels 1.5-V operation VCCIO voltage level support which narrower than defined Normal Range EIA/JEDEC standard.
3.3-V
3.3-V standard formulated under Local Specification Revision developed Special Interest Group (SIG).
Altera Corporation 2007
Stratix Device Handbook, Volume
Stratix Stratix Standards Support
local specification used applications that interface local bus, which provides processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, processor/memory systems. conventional specification revision defines hardware environment including protocol, electrical, mechanical, configuration specifications devices expansion boards. This standard requires 3.3-V VCCIO. Stratix Stratix devices fully compliant with 3.3-V Local Specification Revision meet 64-bit/66-MHz operating frequency timing requirements. 3.3-V standard does require input reference voltages board terminations. Stratix Stratix devices support both input output levels.
3.3-V PCI-X
3.3-V PCI-X standard formulated under PCI-X Local Specification Revision 1.0a developed SIG. PCI-X standard used applications that interface local bus. standard enables design systems devices that operate clock speeds MHz, Gbps 64-bit bus. PCI-X protocol enhancements enable devices operate much more efficiently, providing more usable bandwidth clock frequency. using PCI-X standard, design devices meet PCI-X requirements operate conventional 66-MHz devices when installed those systems. This standard requires 3.3-V VCCIO. Stratix Stratix devices fully compliant with 3.3-V PCI-X Specification Revision 1.0a meet 133-MHz operating frequency timing requirements. 3.3-V PCI-X standard does require input reference voltages board terminations. Stratix Stratix devices support both input output levels operation.
SSTL-2 Class SSTL-2 Class
2.5-V SSTL-2 standard formulated under JEDEC Standard, JESD8-9A: Stub Series Terminated Logic 2.5-V (SSTL_2). SSTL-2 standard 2.5-V memory standard used applications such high-speed SDRAM interfaces. This standard defines input output specifications devices that operate SSTL-2 logic switching range This standard improves
Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
operation conditions where must isolated from large stubs. SSTL-2 requires 1.25-V VREF 1.25-V which series termination resistors connected (Figures 4-2). Stratix Stratix devices support both input output levels operation.
Figure 4-1. 2.5-V SSTL Class Termination
1.25 Output Buffer VREF 1.25 Input Buffer
Figure 4-2. 2.5-V SSTL Class Termination
1.25 1.25
Output Buffer
VREF 1.25
Input Buffer
SSTL-18 Class SSTL-18 Class
1.8-V SSTL-18 standard formulated under JEDEC Standard, JESD8-15: Stub Series Terminated Logic 1.8-V (SSTL_18). SSTL-18 standard 1.8-V memory standard used applications such high-speed DDR2 SDRAM interfaces. This standard similar SSTL-2 defines input output specifications devices that designed operate SSTL-18 logic switching range SSTL-18 requires 0.9-V VREF 0.9-V which series termination resistors connected. There class definitions SSTL-18 standard JEDEC specification. specification this standard based environment that consists both series parallel terminating resistors. Altera provides solutions derived applications JEDEC specification, names them Class Class consistent with other SSTL standards. Figures show SSTL-18 Class termination, respectively.
Altera Corporation 2007
Stratix Device Handbook, Volume
Stratix Stratix Standards Support
Stratix Stratix devices support both input output levels operation.
Figure 4-3. 1.8-V SSTL Class Termination
Output Buffer
VREF
Input Buffer
Figure 4-4. 1.8-V SSTL Class Termination
Output Buffer
VREF
Input Buffer
1.8-V HSTL Class 1.8-V HSTL Class
HSTL standard technology-independent standard developed JEDEC provide voltage scalability. used applications designed operate 0.0- 1.8-V HSTL logic switching range such quad data rate (QDR) memory clock interfaces. Although JEDEC specifies maximum VCCIO value there various memory chip vendors with HSTL standards that require VCCIO Stratix Stratix devices support interfaces chips with VCCIO HSTL. Figures show nominal VREF required track higher value VCCIO. value VREF selected provide optimum noise margin system. Stratix Stratix devices support both input output levels operation.
Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Figure 4-5. 1.8-V HSTL Class Termination
Output Buffer
VREF
Input Buffer
Figure 4-6. 1.8-V HSTL Class Termination
VREF
Output Buffer
Input Buffer
1.5-V HSTL Class 1.5-V HSTL Class
1.5-V HSTL standard formulated under EIA/JEDEC Standard, EIA/JESD8-6: 1.5-V Output Buffer Supply Voltage Based Interface Standard Digital Integrated Circuits. 1.5-V HSTL standard used applications designed operate 0.0- 1.5-V HSTL logic nominal switching range. This standard defines single-ended input output specifications HSTL-compliant digital integrated circuits. 1.5-V HSTL standard Stratix Stratix devices compatible with 1.8-V HSTL standard APEX20KE, APEX 20KC, Stratix Stratix devices themselves because input output voltage thresholds compatible (Figures 4-8). Stratix Stratix devices support both input output levels with VREF VTT.
Altera Corporation 2007
Stratix Device Handbook, Volume
Stratix Stratix Standards Support
Figure 4-7. 1.5-V HSTL Class Termination
0.75
Output Buffer
VREF 0.75
Input Buffer
Figure 4-8. 1.5-V HSTL Class Termination
0.75 0.75 VREF 0.75
Output Buffer
Input Buffer
1.2-V HSTL
Although there EIA/JEDEC standard available 1.2-V HSTL standard, Altera supports applications that operate 1.2-V HSTL logic nominal switching range. 1.2-V HSTL terminated through series parallel on-chip termination (OCT). Figure shows termination scheme. Figure 4-9. 1.2-V HSTL Termination
Output Buffer VREF Input Buffer
Differential Standards
Differential standards used achieve even faster data rates with higher noise immunity. Apart from LVDS, LVPECL, HyperTransport technology, Stratix Stratix devices also support differential versions SSTL HSTL standards.
4-10 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
detailed information differential standards, refer High-Speed Differential Interfaces with Stratix Devices chapter volume Stratix Device Handbook High-Speed Differential Interfaces with Stratix Devices chapter volume Stratix Device Handbook.
Differential SSTL-2 Class Differential SSTL-2 Class
2.5-V differential SSTL-2 standard formulated under JEDEC Standard, JESD8-9A: Stub Series Terminated Logic 2.5-V (SSTL_2). This standard 2.5-V standard used applications such high-speed SDRAM clock interfaces. This standard supports differential signals systems using SSTL-2 standard supplements SSTL-2 standard differential clocks. Stratix Stratix devices support both input output levels. Figures 4-10 4-11 shows details differential SSTL-2 termination. Stratix Stratix devices support differential SSTL-2 standards pseudo-differential mode, which implemented using SSTL-2 single-ended buffers.
Quartus® software only supports pseudo-differential standards INCLK, FBIN EXTCLK ports enhanced PLL, well pins when megafunction (ALTDQS, Bidirectional Data Strobe) used. single-ended output buffers automatically programmed have opposite polarity implement pseudo-differential output. proper VREF voltage required single-ended input buffers implement pseudo-differential input. this case, only positive polarity input used speed path while negative input connected internally. other words, only non-inverted required specified your design, while Quartus software automatically generates inverted you. Although Quartus software does support pseudo-differential SSTL-2 standards left right banks, implement these standards these banks. need create pins designs configure pins with single-ended SSTL-2 standards. However, this limited only pins that support differential pin-pair function dependent single-ended SSTL-2 standards support these banks.
Altera Corporation 2007
4-11 Stratix Device Handbook, Volume
Stratix Stratix Standards Support
Figure 4-10. Differential SSTL-2 Class Termination
1.25 1.25
Differential Transmitter
Differential Receiver
Figure 4-11. Differential SSTL-2 Class Termination
1.25 1.25 1.25 1.25
Differential Transmitter
Differential Receiver
Differential SSTL-18 Class Differential SSTL-18 Class
1.8-V differential SSTL-18 standard formulated under JEDEC Standard, JESD8-15: Stub Series Terminated Logic 1.8-V (SSTL_18). differential SSTL-18 standard 1.8-V standard used applications such high-speed DDR2 SDRAM interfaces. This standard supports differential signals systems using SSTL-18 standard supplements SSTL-18 standard differential clocks. Stratix Stratix devices support both input output levels operation.
4-12 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Figures 4-12 4-13 shows details differential SSTL-18 termination. Stratix Stratix devices support differential SSTL-18 standards pseudo-differential mode, which implemented using SSTL-18 single-ended buffers. Quartus software only supports pseudo-differential standards INCLK, FBIN EXTCLK ports enhanced PLL, well pins when megafunction (ALTDQS, Bidirectional Data Strobe) used. single-ended output buffers automatically programmed have opposite polarity implement pseudo-differential output. proper VREF voltage required single-ended input buffers implement pseudo-differential input. this case, only positive polarity input used speed path while negative input connected internally. other words, only non-inverted required specified your design, while Quartus software automatically generates inverted you. Although Quartus software does support pseudo-differential SSTL-18 standards left right banks, implement these standards these banks. need create pins designs configure pins with single-ended SSTL-18 standards. However, this limited only pins that support differential pin-pair function dependent single-ended SSTL-18 standards support these banks. Figure 4-12. Differential SSTL-18 Class Termination
Differential Transmitter
Differential Receiver
Altera Corporation 2007
4-13 Stratix Device Handbook, Volume
Stratix Stratix Standards Support
Figure 4-13. Differential SSTL-18 Class Termination
Differential Transmitter
Differential Receiver
1.8-V Differential HSTL Class 1.8-V Differential HSTL Class
1.8-V differential HSTL specification same 1.8-V single-ended HSTL specification. used applications designed operate 0.0- 1.8-V HSTL logic switching range such memory clock interfaces. Stratix Stratix devices support both input output levels operation. Figures 4-14 4-15 show details 1.8-V differential HSTL termination. Stratix Stratix devices support 1.8-V differential HSTL standards pseudo-differential mode, which implemented using 1.8-V HSTL single-ended buffers. Quartus software only supports pseudo-differential standards INCLK, FBIN EXTCLK ports enhanced PLL, well pins when megafunction (ALTDQS, Bidirectional Data Strobe) used. single-ended output buffers automatically programmed have opposite polarity implement pseudo-differential output. proper VREF voltage required single-ended input buffers implement pseudo-differential input. this case, only positive polarity input used speed path while negative input connected internally. other words, only non-inverted required specified your design, while Quartus software automatically generates inverted you. Although Quartus software does support 1.8-V pseudo-differential HSTL standards left/right banks, implement these standards these banks. need create pins designs configure pins with single-ended 1.8-V HSTL standards. However, this limited only pins that support differential pin-pair function dependent single-ended 1.8-V HSTL standards support these banks.
4-14 Stratix Device Handbook, Volume Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Figure 4-14. 1.8-V Differential HSTL Class Termination
Differential Transmitter
Differential Receiver
Figure 4-15. 1.8-V Differential HSTL Class Termination
Differential Transmitter
Differential Receiver
1.5-V Differential HSTL Class 1.5-V Differential HSTL Class
1.5-V differential HSTL standard formulated under EIA/JEDEC Standard, EIA/JESD8-6: 1.5-V Output Buffer Supply Voltage Based Interface Standard Digital Integrated Circuits. 1.5-V differential HSTL specification same 1.5-V single-ended HSTL specification. used applications designed operate 0.0- 1.5-V HSTL logic switching range, such memory clock interfaces. Stratix Stratix devices support both input output levels operation. Figures 4-16 4-17 show details 1.5-V differential HSTL termination. Stratix Stratix devices support 1.5-V differential HSTL standards pseudo-differential mode, which implemented using 1.5-V HSTL single-ended buffers.
Altera Corporation 2007
4-15 Stratix Device Handbook, Volume
Stratix Stratix Standards Support
Quartus software only supports pseudo-differential standards INCLK, FBIN EXTCLK ports enhanced PLL, well pins when megafunction (ALTDQS, Bidirectional Data Strobe) used. single-ended output buffers automatically programmed have opposite polarity implement pseudo-differential output. proper VREF voltage required single-ended input buffers implement pseudo-differential input. this case, only positive polarity input used speed path while negative input connected internally. other words, only non-inverted required specified your design, while Quartus software automatically generates inverted you. Although Quartus software does support 1.5-V pseudo-differential HSTL standards left/right banks, implement these standards these banks. need create pins designs configure pins with single-ended 1.5-V HSTL standards. However, this limited only pins that support differential pin-pair function dependent single-ended 1.8-V HSTL standards support these banks. Figure 4-16. 1.5-V Differential HSTL Class Termination
0.75 0.75
Differential Transmitter
Differential Receiver
4-16 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Figure 4-17. 1.5-V Differential HSTL Class Termination
0.75 0.75 0.75 0.75
Differential Transmitter
Differential Receiver
LVDS
LVDS standard formulated under ANSI/TIA/EIA Standard, ANSI/TIA/EIA-644: Electrical Characteristics Voltage Differential Signaling Interface Circuits. LVDS standard differential high-speed, low-voltage swing, low-power, general-purpose interface standard. Stratix devices, LVDS standard requires 2.5-V VCCIO level side pins banks bottom banks have different VCCIO requirements LVDS standard. LVDS clock pins banks through require 3.3-V VCCIO level. Within these banks, PLL[5,6,11,12]_OUT[1,2] pins support output only LVDS operations. PLL[5,6,11,12]_FB/OUT2 pins support LVDS input output operations cannot configured bidirectional LVDS operations. LVDS clock input pins banks VCCINT have dependency VCCIO voltage level. This standard used applications requiring high-bandwidth data transfer, backplane drivers, clock distribution. ANSI/TIA/EIA-644 standard specifies LVDS transmitters receivers capable operating recommended maximum data signaling rates megabit second (Mbps). However, devices operate slower speeds needed, there theoretical maximum 1.923 Gbps. Stratix Stratix devices capable running maximum data rate Gbps still meet ANSI/TIA/EIA-644 standard. Because low-voltage swing LVDS standard, electromagnetic interference (EMI) effects much smaller than complementary metal-oxide semiconductor (CMOS), transistor-to-transistor logic (TTL), positive psuedo) emitter coupled logic (PECL). This makes LVDS ideal applications
Altera Corporation 2007
4-17 Stratix Device Handbook, Volume
Stratix Stratix Standards Support
with requirements noise immunity requirements. LVDS standard does require input reference voltage. However, does require 100- termination resistor between signals input buffer. Stratix Stratix devices provide optional 100- differential LVDS termination resistor device using on-chip differential termination. Stratix Stratix devices support both input output levels operation.
Differential LVPECL
low-voltage positive pseudo) emitter coupled logic (LVPECL) standard differential interface standard requiring 3.3-V VCCIO. standard used applications involving video graphics, telecommunications, data communications, clock distribution. high-speed, low-voltage swing LVPECL standard uses positive power supply similar LVDS. However, LVPECL larger differential output voltage swing than LVDS. LVPECL standard does require input reference voltage, does require 100- termination resistor between signals input buffer. Figures 4-18 4-19 show alternate termination schemes LVPECL. Stratix Stratix devices support both input output levels operation.
Figure 4-18. LVPECL Coupled Termination
Output Buffer
Input Buffer
Figure 4-19. LVPECL Coupled Termination
VCCIO VCCIO
Output Buffer
Input Buffer
4-18 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
HyperTransport Technology
HyperTransport standard formulated HyperTransport Consortium. HyperTransport standard differential high-speed, high-performance interface standard requiring 2.5- 3.3-V VCCIO. This standard used applications such high-performance networking, telecommunications, embedded systems, consumer electronics, Internet connectivity devices. HyperTransport standard point-to-point standard which each HyperTransport consists point-to-point unidirectional links. Each link bits. HyperTransport standard does require input reference voltage. However, does require 100- termination resistor between signals input buffer. Figure 4-20 shows HyperTransport termination. Stratix Stratix devices include optional 100- differential HyperTransport termination resistor device using on-chip differential termination. Stratix Stratix devices support both input output levels operation.
Figure 4-20. HyperTransport Termination
Output Buffer
Input Buffer
Stratix Stratix External Memory Interface
increasing demand higher-performance data processing systems often requires memory-intensive applications. Stratix Stratix devices interface with many types external memory.
Refer External Memory Interfaces chapter volume Stratix Device Handbook External Memory Interfaces chapter volume Stratix Device Handbook more information external memory interface support Stratix Stratix devices.
Altera Corporation 2007
4-19 Stratix Device Handbook, Volume
Stratix Stratix Banks
Stratix Stratix Banks
Stratix devices have eight general banks four enhanced phase-locked loop (PLL) external clock output banks (Figure 4-21). banks left right sides device banks through bottom device.
Figure 4-21. Stratix Banks Notes (1), (2), (3), (4), (5), (6),
DQS8T VREF0B3 DQS7T VREF1B3 DQS6T VREF3B3 DQS5T VREF4B3 VREF2B3
PLL11
Bank
PLL5
Bank
DQS4T VREF0B4
DQS3T VREF1B4
DQS2T VREF2B4
DQS1T VREF3B4
DQS0T VREF4B4
PLL7 Bank
VREF
PLL10 Bank
VREF
Bank
Bank
PLL4 PLL3
EF2B2
EF1B2
VREF
PLL1
PLL2
EF4B1
banks support LVTTL, LVCMOS, 2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class HSTL-18 Class HSTL-15 Class LVDS, HyperTransport standards input output operations. HSTL-18 Class HSTL-15-Class SSTL-18 Class standards only supported input operations.
EF3B1
Bank
Bank
PLL9
VREF
This bank supports LVDS LVPECL standards input clock operations. Differential HSTL differential SSTL standards supported both input output operations.
This bank supports LVDS LVPECL standards input clock operations. Differential HSTL differential SSTL standards supported both input output operations.
VREF
VREF
Bank PLL8
VREF4B8 DQS8B VREF3B8 VREF2B8 VREF1B8 VREF0B8 DQS5B DQS7B DQS6B
Bank
Bank
VREF4B7 DQS4B VREF3B7 DQS3B
Bank
VREF2B7 DQS2B VREF1B7 DQS1B VREF0B7 DQS0B
PLL12
PLL6
Notes Figure 4-21:
Figure 4-21 view silicon that corresponds reverse view flip-chip packages. graphical representation only. Refer list Quartus software exact locations. Depending size device, different device members have different numbers VREF groups. Banks through enhanced external clock output banks. These banks utilize adjacent VREF group when voltage-referenced standards implemented. example, SSTL input implemented bank voltage level VREFB7 reference voltage level SSTL input. Differential HSTL differential SSTL standards available bidirectional operations input-only operations clock input pins; LVDS, LVPECL, HyperTransport standards available input-only operations clock input pins. Refer "Differential Standards" page 4-10 more details. Quartus software does support differential SSTL differential HSTL standards left/right banks. Refer "Differential Standards" page 4-10 need implement these standards these banks. Banks available only EP2S60, EP2S90, EP2S130, EP2S180 devices. PLLs available only EP2S60, EP2S90, EP2S130, EP2S180 devices.
4-20 Stratix Device Handbook, Volume
Altera Corporation 2007
VREF
VREF
VREF
banks support single-ended standards differential standards except HyperTransport technology both input output operations.
EF1B6
EF0B6
VREF
EF3B5
EF2B5
This bank supports LVDS LVPECL standards input clock operations. Differential HSTL differential SSTL standards supported both input output operations.
banks support single-ended standards differential standards except HyperTransport technology both input output operations.
This bank supports LVDS LVPECL standards input clock operations. Differential HSTL differential SSTL standards supported both input output operations.
EF3B
EF1B
Selectable Standards Stratix Stratix Devices
Stratix devices have general banks enhanced phase-locked loop (PLL) external clock output banks (Figure 4-22). banks through enhanced external clock output banks located bottom device. Figure 4-22. Stratix Banks Notes (1), (2), (3),
DQSx8
PLL7 VREF0B2 VREF1B2 VREF2B2 VREF3B2 VREF4B2
DQSx8
DQSx8
Bank
DQSx8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
PLL11 Bank
PLL5 Bank
DQSx8
DQSx8
DQSx8
DQSx8
Bank
DQSx8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
This bank supports LVDS LVPECL This bank supports LVDS LVPECL standards input clock operations. standards input clock operation. Differential HSTL differential SSTL Differential HSTL differential SSTL standards supported both input standards supported both input output operations. output operations. Banks support single-ended standards both input output operation. differential standards supported both input output operation banks Banks support LVTTL, LVCMOS, -]V, SSTL SSTL-18 class LVDS, pseudo-differential SSTL pseudo-differential SSTL-18 class standards both input output operations. HSTL, SSTL-18 class pseudo-differential HSTL, pseudo-differential SSTL-18 class standards only supported input operations. Banks support single-ended standards both input output operation. differential standards supported both input output operations bank
Bank
PLL1
PLL2
VREF0B1 VREF1B1 VREF2B1 VREF3B1 VREF4B1
Bank
This bank supports LVDS LVPECL standards input clock operations. Differential HSTL differential SSTL standards supported both input output operations.
This bank supports LVDS LVPECL standards input clock operations. Differential HSTL differential SSTL standards supported both input output operations.
Bank
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
Bank
PLL8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
Bank PLL12 DQSx8
Bank PLL6 DQSx8 DQSx8
DQSx8
DQSx8
DQSx8
DQSx8
DQSx8
DQSx8
Notes Figure 4-22:
Figure 4-22 view silicon which corresponds reverse view flip-chip packages. graphical representation only. Depending size device, different device members have different number VREF groups. Refer list Quartus software exact locations. Banks through enhanced external clock output banks. Horizontal banks feature transceiver circuitry high speed differential standards. Refer High Speed Differential Interfaces Stratix Devices chapter volume Stratix Device Handbook, Stratix Transceiver User Guide more information differential standards. Quartus software does support differential SSTL differential HSTL standards left/right banks. Refer "Differential Standards" page 4-10 need implement these standards these banks. Banks available only EP2SGX60C/D/E, EP2SGX90E/F, EP2SGX130G. PLLs 7,8,11, available only EP2SGX60C/D/E, EP2SGXE/F, EP2SGX130G.
Altera Corporation 2007
4-21 Stratix Device Handbook, Volume
Bank
Bank
Bank
Bank
Bank
Stratix Stratix Banks
Programmable Standards
Stratix Stratix device programmable standards deliver high-speed high-performance solutions many complex design systems. This section discusses standard support banks Stratix Stratix devices.
Regular Pins
Most Stratix Stratix device pins multi-function pins. These pins support regular inputs outputs their primary function, offer optional function such DQS, differential pin-pair, external clock outputs. example, configure multi-function enhanced external clock output bank external clock output when used regular pin. pins that reside banks through powered VCC_PLL<5, 12>_OUT pins, respectively. EP2S60F484, EP2S60F780, EP2S90H484, EP2S90F780, EP2S130F780 devices support PLLs Therefore, pins that reside bank powered VCCIO3 pin, pins that reside bank powered VCCIO8 pin.
Table shows standards supported when used regular banks Stratix Stratix devices.
Table 4-2. Stratix Stratix Regular Standards Support (Part General Bank Standard
LVTTL LVCMOS 3.3-V 3.3-V PCI-X SSTL-2 Class SSTL-2 Class
Enhanced External Clock Output Bank
5(1) 6(1)
4-22 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Table 4-2. Stratix Stratix Regular Standards Support (Part General Bank Standard
SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class Differential SSTL-18 Class 1.8-V differential HSTL Class 1.8-V differential HSTL Class 1.5-V differential HSTL Class 1.5-V differential HSTL Class LVDS HyperTransport technology Differential LVPECL Notes Table 4-2:
This bank available Stratix Devices. mixture single-ended differential standards allowed enhanced external clock output bank. This standard only supported input operation this bank. Although Quartus software does support pseudo-differential SSTL-2 standards left right banks, implement these standards these banks. Refer "Differential Standards" page 4-10 details. This standard supported both input output operations pins that support function. Refer "Differential Standards" page 4-10 details. This standard only supported input operation pins that support INCLK function this bank.
Enhanced External Clock Output Bank
5(1) 6(1)
Altera Corporation 2007
4-23 Stratix Device Handbook, Volume
Stratix Stratix Banks
Clock Pins
clock pins consist clock inputs (INCLK), external feedback inputs (FBIN), external clock outputs (EXTCLK). Clock inputs located left right banks (banks support fast PLLs, bottom banks (banks support enhanced PLLs. Both external clock outputs external feedback inputs located enhanced external clock output banks (banks support enhanced PLLs. Table shows clock support banks Stratix Stratix devices.
Table 4-3. Standards Supported Stratix Stratix Pins (Part Enhanced Standard INCLK
LVTTL LVCMOS 3.3-V 3.3-V PCI-X SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class Differential SSTL-18 Class
Fast Output Input INCLK
Input FBIN
EXTCLK
4-24 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Table 4-3. Standards Supported Stratix Stratix Pins (Part Enhanced Standard INCLK
1.8-V differential HSTL Class 1.8-V differential HSTL Class 1.5-V differential HSTL Class 1.5-V differential HSTL Class LVDS HyperTransport technology Differential LVPECL Note Table 4-3:
enhanced external clock output bank does allow mixture both single-ended differential standards. Altera does support 1.2-V HSTL input pins column pins.
Fast Output Input INCLK
Input FBIN
EXTCLK
more information, refer PLLs chapter volume Stratix Device Handbook Stratix Device Handbook.
Voltage Levels
Stratix device specify range allowed voltage levels supported standards. Table shows only typical values input output VCCIO, VREF, well board VTT.
Table 4-4. Stratix Stratix Standards Voltage Levels (Part Note Stratix Stratix VCCIO Standard Input Operation Bottom Banks
LVTTL LVCMOS 3.3/2.5 3.3/2.5 3.3/2.5 1.8/1.5
VREF Output Operation Input
Left Right Bottom Left Right Banks Banks Banks(3)
3.3/2.5 3.3/2.5 3.3/2.5 1.8/1.5
Termination
Altera Corporation 2007
4-25 Stratix Device Handbook, Volume
Stratix Stratix Banks
Table 4-4. Stratix Stratix Standards Voltage Levels (Part Note Stratix Stratix VCCIO Standard Input Operation Bottom Banks
3.3-V 3.3-V PCI-X SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL(4) Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class Differential SSTL-18 Class 1.8-V differential HSTL Class 1.8-V differential HSTL Class 1.5-V differential HSTL Class 1.5-V differential HSTL Class LVDS HyperTransport technology 1.8/1.5 3.3/2.5/1.8/1.5
VREF Output Operation Input
Left Right Bottom Left Right Banks Banks Banks(3)
1.8/1.5
Termination
1.25 1.25 0.90 0.90 0.90 0.90 0.75 0.75 1.25 1.25 0.90 0.90 0.90 0.90 0.75 0.75
1.25 1.25 0.90 0.90 0.90 0.90 0.75 0.75 1.25 1.25 0.90 0.90 0.90 0.90 0.75 0.75
4-26 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Table 4-4. Stratix Stratix Standards Voltage Levels (Part Note Stratix Stratix VCCIO Standard Input Operation Bottom Banks
Differential LVPECL Notes Table 4-4:
input pins with PCI-clamping diode will clamp VCCIO LVDS LVPECL output operation bottom banks only supported banks 9-12. VCCIO level differential output operation banks VCCIO level output operation left right banks right bank does apply Stratix right Bank Stratix devices consists transceivers. 1.2-V HSTL only supported banks 4,7,
VREF Output Operation Input
Left Right Bottom Left Right Banks Banks Banks(3)
Termination
3.3/2.5/1.8/1.5
Refer Switching Characteristics chapter volume Stratix Device Handbook Switching Characteristics chapter volume Stratix Handbook detailed electrical characteristics each standard. Stratix Stratix devices feature on-chip termination provide impedance matching termination capabilities. Apart from maintaining signal integrity, this feature also minimizes need external resistor networks, thereby saving board space reducing costs. Stratix Stratix devices support on-chip series (RS) parallel (RT) termination single-ended standards on-chip differential termination (RD) differential standards. This section discusses on-chip series termination support.
On-Chip Termination
more information differential on-chip termination, Refer High-Speed Differential Interfaces with chapter volume Stratix Device Handbook High-Speed Differential Interfaces with chapter volume Stratix Device Handbook.
Altera Corporation 2007
4-27 Stratix Device Handbook, Volume
On-Chip Termination
Stratix Stratix devices supports driver on-chip series (RS) parallel (RT) termination through drive strength control single-ended I/Os. There three ways implement (RT) Stratix Stratix devices:
without calibration both I/Os column I/Os with calibration only column I/Os with calibration only column I/Os
On-Chip Series Termination without Calibration
Stratix Stratix devices support driver impedance matching provide driver with controlled output impedance that closely matches impedance transmission line. result, reflections significantly reduced. Stratix Stratix devices support on-chip series termination single-ended standards (see Figure 4-23). shown Figure 4-23 intrinsic impedance transistors. typical values Once matching impedance selected, current drive strength longer selectable. On-chip series termination without calibration supported output pins output function bidirectional pins.
Figure 4-23. Stratix Stratix On-Chip Series Termination without Calibration
Stratix Driver Series Impedance VCCIO Receiving Device
4-28 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Table shows list output standards that support on-chip series termination without calibration.
Table 4-5. Selectable Drivers with On-Chip Series Termination without Calibration On-chip Series Termination Setting Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL
Column
Unit
1.8-V LVCMOS
1.5-V LVTTL 1.5-V LVCMOS SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL Note Table 4-5:
1.2-V HSTL only supported banks 4,7,
on-chip termination SSTL Class standard, users should select on-chip series termination setting replacing external match transmission line). SSTL Class standard, users should select on-chip series termination setting match transmission line near pull-up VTT).
Altera Corporation 2007
4-29 Stratix Device Handbook, Volume
On-Chip Termination
more information tolerance specifications on-chip termination without calibration, refer Switching Characteristics chapter volume Stratix Device Handbook Switching Characteristics chapter volume Stratix Device Handbook.
On-Chip Series Termination with Calibration
Stratix Stratix devices support on-chip series termination with calibration column I/Os bottom banks. Every column buffer consists group transistors parallel. Each transistor individually enabled disabled. on-chip series termination calibration circuit compares total impedance transistor group external resistors connected pins, dynamically enables disables transistors until they match shown Figure 4-24). shown Figure 4-24 intrinsic impedance transistors. Calibration happens device configuration. Once calibration circuit finds correct impedance, powers down stops changing characteristics drivers. On-chip series termination with calibration supported output pins output function bidirectional pins.
Figure 4-24. Stratix Stratix On-Chip Series Termination with Calibration
Stratix Driver Series Impedance VCCIO Receiving Device
4-30 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Table shows list output standards that support on-chip series termination with calibration.
Table 4-6. Selectable Drivers with On-Chip Series Termination with Calibration Standard
3.3-V LVTTL
On-Chip Series Termination Setting (Column I/O)
Unit
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
LVTTL LVCMOS SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL Note Table 4-6:
1.2-V HSTL only supported banks 4,7,
On-Chip Parallel Termination with Calibration
Stratix Stratix devices support on-chip parallel termination with calibration column I/Os bottom banks. Every column buffer consists group transistors parallel. Each transistor individually enabled disabled. on-chip parallel termination calibration circuit compares total impedance transistor group
Altera Corporation 2007
4-31 Stratix Device Handbook, Volume
On-Chip Termination
external resistors connected pins dynamically enables disables transistors until they match. Calibration happens device configuration. Once calibration circuit finds correct impedance, powers down stops changing characteristics drivers.
Table 4-7. Selectable Drivers with On-Chip Parallel Termination with Calibration Standard
SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL Note Table 4-7:
1.2-V HSTL only supported banks 4,7,
On-Chip Parallel Termination Setting (Column I/O)
Unit
There separate sets calibration circuits Stratix Stratix devices:
calibration circuit banks calibration circuit bottom banks
Calibration circuits rely external pull-up reference resistor (RUP) pull-down reference resistor (RDN) achieve accurate on-chip series parallel termination. There pair pins bank calibration circuit banks Similarly, there pair pins bank calibration circuit bottom banks banks share same calibration circuitry, they must have same VCCIO voltage both banks enable on-chip series parallel termination with calibration. banks have different VCCIO voltages, only bank enable on-chip series parallel termination with calibration because pins located bank Bank still on-chip series termination, without calibration. same rule applies banks
4-32 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
On-chip parallel termination with calibration only supported input pins. Pins configured bidirectional support on-chip parallel termination.
pins dual-purpose I/Os, which means they used regular I/Os calibration circuit used. When used calibration, connected VCCIO through external resistor on-chip series termination value respectively. connected through external resistor on-chip series termination value respectively. on-chip parallel termination, connected VCCIO through external resistor, connected through external resistor.
more information tolerance specifications on-chip termination with calibration, refer Switching Characteristics chapter volume Stratix Device Handbook Switching Characteristics chapter volume Stratix Device Handbook. While Stratix Stratix devices feature various capabilities high-performance high-speed system designs, there several other considerations that require attention ensure success those designs.
Design Considerations
Termination
termination requirements single-ended differential standards discussed this section.
Single-Ended Standards
Although single-ended, non-voltage-referenced standards require termination, impedance matching necessary reduce reflections improve signal integrity. Voltage-referenced standards require both input reference voltage, VREF, termination voltage, VTT. reference voltage receiving device tracks termination voltage transmitting device. Each voltage-referenced standard requires unique termination setup. example, proper resistive signal termination scheme critical SSTL standards produce reliable memory system with superior noise margin.
Altera Corporation 2007
4-33 Stratix Device Handbook, Volume
Design Considerations
Stratix Stratix on-chip series parallel termination provides convenience external components. External pull-up resistors used terminate voltage-referenced standards such SSTL-2 HSTL.
Refer "Stratix Stratix Standards Support" page more information termination scheme various single-ended standards.
Differential Standards
Differential standards typically require termination resistor between signals receiver. termination resistor must match differential load impedance bus. Stratix Stratix devices provide optional differential on-chip resistor when using LVDS HyperTransport standards.
Banks Restrictions
Each bank simultaneously support multiple standards. following sections provide guidelines mixing non-voltage-referenced voltage-referenced standards Stratix Stratix devices.
Non-Voltage-Referenced Standards
Each Stratix Stratix device bank VCCIO pins supports only VCCIO, either 1.5, 1.8, 2.5, bank simultaneously support number input signals with different standard assignments, shown Table 4-8. output signals, single bank supports non-voltage-referenced output signals that driving same voltage VCCIO. Since bank only have VCCIO value, only drive that value non-voltage-referenced signals. example, bank with 2.5-V VCCIO setting support 2.5-V standard inputs outputs 3.3-V LVCMOS inputs (not output bidirectional pins).
Table 4-8. Acceptable Input Levels LVTTL LVCMOS Bank VCCIO
(Part
Acceptable Input Levels
4-34 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Table 4-8. Acceptable Input Levels LVTTL LVCMOS Bank VCCIO
(Part
Acceptable Input Levels
Notes Table 4-8:
Because input signal does drive rail, input buffer does completely shut off, current slightly higher than default value. These input values overdrive input buffer, leakage current slightly higher than default value. drive inputs higher than VCCIO less than disable clamping diode select Allow LVTTL LVCMOS input levels overdrive input buffer option Quartus software.
Voltage-Referenced Standards
accommodate voltage-referenced standards, each Stratix Stratix device's bank supports multiple VREF pins feeding common VREF bus. number available VREF pins increases device density increases. these pins used VREF pins, they cannot used generic pins. However, each bank only have single VCCIO voltage level single VREF voltage level given time. bank featuring single-ended differential standards support voltage-referenced standards long voltage-referenced standards same VREF setting. Because performance reasons, voltage-referenced input standards their VCCIO level power source. example, only place 1.5-V HSTL input pins bank with 1.5-V VCCIO.
Refer "Stratix Stratix Banks" page 4-20 details input VCCIO voltage-referenced standards. Voltage-referenced bidirectional output signals must same bank's VCCIO voltage. example, only place SSTL-2 output pins bank with 2.5-V VCCIO.
Refer "I/O Placement Guidelines" page 4-36 details voltage-referenced standards placement.
Altera Corporation 2007
4-35 Stratix Device Handbook, Volume
Design Considerations
Mixing Voltage-Referenced Non-Voltage-Referenced Standards
bank support both non-voltage-referenced voltage-referenced pins applying each rule sets individually. example, bank support SSTL-18 inputs 1.8-V inputs outputs with 1.8-V VCCIO 0.9-V VREF. Similarly, bank support 1.5-V standards, 2.5-V (inputs, outputs), HSTL standards with 1.5-V VCCIO 0.75-V VREF.
Placement Guidelines
placement guidelines help reduce noise issues that associated with design such that Stratix Stratix FPGAs maintain acceptable noise level VCCIO supply. Because Stratix Stratix devices require each bank powered separately VCCIO, these noise issues have effect when crossing bank boundaries and, such, these rules need applied. This section provides placement guidelines programmable standards supported Stratix Stratix devices includes essential information designing systems using their devices' selectable capabilities.
VREF Placement Restrictions
There least dedicated VREF pins bank drive VREF bus. Larger Stratix Stratix devices have more VREF pins bank. VREF pins within bank shorted together device level. There limits number pins that VREF support. example, each output adds some noise VREF level excessive number outputs make level unstable used incoming signals. Restrictions placement single-ended voltage-referenced pads with respect VREF pins help maintain acceptable noise level VCCIO supply prevent output switching noise from shifting VREF rail. Input Pins Each VREF supports maximum input pads.
4-36 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Output Pins When voltage-referenced input bidirectional does exist bank, number output pads that used that bank depends total number available pads that same bank. However, when voltage-referenced input exists, design output pads VREF bank. Bidirectional Pins Bidirectional pads must satisfy both input output guidelines simultaneously. general formulas input output rules shown Table 4-9.
Table 4-9. Bidirectional Limitation Formulas Rules
Input Output
Formulas
<Total number bidirectional pins> <Total number VREF input pins, any> VREF <Total number bidirectional pins> <Total number output pins, any> <Total number pins from smallest group, more than groups> VREF
same output enable (OE) controls bidirectional pads (bidirectional pads same group driving same time) there other outputs voltage-referenced inputs bank, then voltage-referenced input never active same time output. Therefore, output limitation rule does apply. However, since bidirectional pads linked same bidirectional pads will inputs same time. Therefore, there limit input pads, follows: <Total number bidirectional pins> <Total number VREF input pins> VREF
bidirectional pads controlled different there other outputs voltage-referenced inputs bank, then group bidirectional pads used inputs another group used outputs. such cases, formula output rule simplified, follows: <Total number bidirectional pins> <Total number pins from smallest group> VREF
Altera Corporation 2007
4-37 Stratix Device Handbook, Volume
Design Considerations
Consider case where eight bidirectional pads controlled OE1, eight bidirectional pads controlled OE2, bidirectional pads controlled OE3, there other outputs voltage-referenced inputs bank. While this totals bidirectional pads, safely allowable because there would possible maximum outputs VREF pin, assuming worst case where active inactive. This useful SDRAM applications. When least additional voltage-referenced input other outputs exist same VREF group, bidirectional limitation must simultaneously adhere input output limitations. input rule becomes: <Total number bidirectional pins> <Total number VREF input pins> VREF Whereas output rule simplified <Total number bidirectional pins> VREF
When least additional output exists voltage-referenced inputs exist, output rule becomes: <Total number bidirectional pins> <Total number output pins> <Total number pins from smallest group> VREF
When additional voltage-referenced inputs other outputs exist same VREF group, then bidirectional limitation must again simultaneously adhere input output limitations. input rule <Total number bidirectional pins> <Total number VREF input pins> VREF Whereas output rule given <Total number bidirectional pins> <Total number output pins> <Total number pins from smallest group> VREF
Placement with Respect High-Speed Differential Pins
Regardless whether SERDES circuitry utilized, there restriction placement single-ended output pins with respect high-speed differential pins. shown Figure 4-25,
4-38 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
single-ended outputs must placed least away from differential pins. There restrictions placement single-ended input pins with respect differential pins. Single-ended input pins placed within same differential pins. However, single-ended input's register available. input must implemented within core logic. This single-ended output placement restriction only applies when using LVDS HyperTransport standards left right banks. There restrictions single-ended output placement with respect differential clock pins bottom banks. Figure 4-25. Single-Ended Output Placement with Respect Differential Pins
Single-Ended Output Differential Single_Ended Input
Single-Ended Outputs Allowed
Boundary
Guidelines
Power budgets essential ensure reliability functionality system application. often required perform power dissipation analysis each device system come with total power dissipated that system, which composed static component dynamic component. static power consumption device total current flowing from VCCIO ground.
Altera Corporation 2007
4-39 Stratix Device Handbook, Volume
Design Considerations
consecutive pads bank Stratix Stratix devices, Altera recommends maximum current shown Figure 4-26, because placement VCCIO/ground (GND) bumps regular, pins pair power pins. This limit static power consumed standard, shown Table 4-10. Limiting static power improve reliability over lifetime device. Figure 4-26. Current Density Restriction Notes (1),
Sequence Bank
Consecutive Output Pins
pin+9
250mA
Notes Figure 4-26:
consecutive pads cross banks. VREF pins affect current calculation because there VREF pads.
4-40 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
Table 4-10 shows standard current specification.
Table 4-10. Stratix Stratix Standard Current Specification (Part Standard
LVTTL LVCMOS 3.3-V 3.3-V PCI-X SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class Differential SSTL-18 Class 1.8-V differential HSTL Class 1.8-V differential HSTL Class 1.5-V differential HSTL Class 1.5-V differential HSTL Class
Note
IPIN (mA), Bottom Banks
IPIN (mA), Left Right Banks(2)
Altera Corporation 2007
4-41 Stratix Device Handbook, Volume
Conclusion
Table 4-10. Stratix Stratix Standard Current Specification (Part Standard
Notes Table 4-10:
Note
IPIN (mA), Bottom Banks
IPIN (mA), Left Right Banks(2)
current value obtained differential HSTL differential SSTL standards differential pair, opposed per-pair current value LVDS HyperTransport standards. This does apply right banks Stratix devices. Stratix devices have transceivers right banks. power specification each standard depends current sourcing sinking capabilities buffer programmed with that standard, well load being driven. LVTTL, LVCMOS, 2.5-V, 1.8-V, 1.5-V outputs included static power calculations because they normally have resistor loads real applications. voltage swing rail-to-rail with capacitive load only. There current system. This IPIN value represents current specification default current strength standard. IPIN varies with programmable drive strength same drive strength Quartus software. Refer Stratix Architecture chapter volume Stratix Device Handbook Stratix Architecture chapter volume Stratix Device Handbook detailed description programmable drive strength feature voltage-referenced standards.
Table 4-10 only shows limit static power consumed standard. amount power used moment could much higher, based switching activities.
Conclusion
Stratix Stratix devices provide capabilities that allow work compliance with current emerging standards requirements. With Stratix Stratix devices features, such programmable driver strength, reduce board design interface costs increase development flexibility. Refer following sources more information:
Further Information
Stratix Device Family Data Sheet volume Stratix Device Handbook Stratix Device Family Data Sheet volume Stratix Device Handbook PLLs Stratix Devices chapter volume Stratix Device Handbook. PLLs Stratix Devices chapter volume Stratix Device Handbook. High-Speed Board Layout Guidelines chapter volume Stratix Device Handbook High-Speed Board Layout Guidelines chapter volume Stratix Device Handbook
4-42 Stratix Device Handbook, Volume
Altera Corporation 2007
Selectable Standards Stratix Stratix Devices
References
Refer following references more information:
Interface Standard Nominal 3.3-V Supply Digital Integrated Circuits, JESD8-B, Electronic Industries Association, September 1999. 2.5-V 0.2V (Normal Range) 1.8-V 2.7V (Wide Range) Power Supply Voltage Interface Standard Non-terminated Digital Integrated Circuits, JESD8-5, Electronic Industries Association, October 1995. 1.8-V 0.15 (Normal Range) 1.95 (Wide Range) Power Supply Voltage Interface Standard Non-terminated Digital Integrated Circuits, JESD8-7, Electronic Industries Association, February 1997. 1.5-V (Normal Range) (Wide Range) Power Supply Voltage Interface Standard Non-terminated Digital Integrated Circuits, JESD8-11, Electronic Industries Association, October 2000. Local Specification, Revision 2.2, Special Interest Group, December 1998. PCI-X Local Specification, Revision 1.0a, Special Interest Group. Stub Series Terminated Logic 2.5-V (SSTL-2), JESD8-9A, Electronic Industries Association, December 2000. Stub Series Terminated Logic (SSTL-18), Preliminary JC42.3, Electronic Industries Association. High-Speed Transceiver Logic (HSTL)-A 1.5-V Output Buffer Supply Voltage Based Interface Standard Digital Integrated Circuits, EIA/JESD8-6, Electronic Industries Association, August 1995. Electrical Characteristics Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunications Industry/Electronic Industries Association, October 1995.
Altera Corporation 2007
4-43 Stratix Device Handbook, Volume
Document Revision History
Document Revision History
Table 4-11 shows revision history this chapter.
Table 4-11. Document Revision History Date Document Version
2007 v4.5
Changes Made
Added note "On-Chip Series Termination with Calibration" section. Added note "On-Chip Series Termination without Calibration" section Updated note "Stratix Stratix Features" section. Updated "LVDS" section. Updated note "1.5 section
Summary Changes
Updated Note Table Updated Note Table
Updated Table 4-2, column heading columns Updated Table 4-10. Fixed typo "Stratix Stratix Features" section February 2007 Added "Document Revision History" section v4.4 this chapter. August 2006 v4.3 Updated Table 9-2, Table 9-4, Table 9-5, Table 9-6, Table 9-7.
April 2006 v4.2 Chapter updated part Stratix Device Handbook update. change Formerly chapter Chapter number change only chapter addition Section February 2006; content change. Chapter updated part Stratix Device Handbook update. Added chapter Stratix Device Handbook.
December 2005 v4.1 October 2005 v4.0
4-44 Stratix Device Handbook, Volume
Altera Corporation 2007

SII52004-4.5 This chapter provides guidelines using industry stan

Top Searches for this datasheet

Other recent searches