Chapter Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
|
|
|
Top Searches for this datasheet
This section provides documentation some functions offered Altera® Stratix® devices. (Also Intellectual Property section Altera site complete offering cores Stratix devices.) last chapter details design considerations migrating from APEXarchitecture. This section contains following chapters:
Chapter Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices Chapter Implementing SFI-4 Stratix Stratix Devices Chapter Transitioning APEX Designs Stratix Stratix Devices
Chapter
table below shows revision history Chapters through
Date/Version
July 2005, v2.0 September 2004, v1.2
Changes Made
Updated Stratix device information. Table page 8-10: updated table, deleted Note updated Note Updated Table page 8-12. Removed support series parallel on-chip termination. changes Stratix Device Handbook v2.0. Updated Stratix device information. Table page 9-9: updated table, deleted Note updated Note Updated Table page 9-10. changes Stratix Device Handbook v2.0.
November 2003, v1.1 April 2003, v1.0 July 2005, v2.0 September 2004, v1.1
April 2003, v1.0
Altera Corporation
Section
Design Considerations
Stratix Device Handbook, Volume
Chapter
Date/Version
July 2005, v3.0 September 2004, v2.1 April 2004, v2.0 November 2003, v1.2 October 2003, v1.1 April 2003, v1.0
Changes Made
Updated Stratix device information. Updated Table 10-9 page 10-26. Synchronous occurrences renamed pipelined. Asynchronous occurrences renamed flow-through. Removed support series parallel on-chip termination. Updated Table 10-6. changes Stratix Device Handbook v2.0.
Section
Altera Corporation
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
S52010-2.0
Introduction
Ethernet evolved meet ever-increasing bandwidth demands most prevalent local-area network (LAN) communications protocol. 10-Gigabit Ethernet extends that protocol higher bandwidth future high-speed applications. accelerated growth network traffic resulting increase bandwidth requirements driving service providers enterprise network architects towards high-speed network solutions. Potential applications 10-Gigabit Ethernet include private campus backbones, high-speed access links between service providers enterprises, aggregation transport metropolitan area networks (MANs). features Stratix® Stratix devices enable support 10Gigabit Ethernet, supporting 10-Gigabit 16-bit interface (XSBI) 10Gigabit medium independent interface (XGMII). Stratix devices additionally support 10-gigabit attachment unit interface (XAUI) using embedded 3.125-Gbps transceivers. find more information XAUI support Section Stratix Transceiver User Guide, Stratix Device Handbook, Volume This chapter discusses following topics:
Fundamentals 10-Gigabit Ethernet Description implementation XSBI Description implementation XGMII Description XAUI characteristics XSBI, XGMII, XAUI
Related Links
10-Gigabit Ethernet Alliance www.10gea.org Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Differential Interfaces Stratix Devices chapter
10-Gigabit Ethernet
Ethernet speed increased keep pace with demand, initially megabits second (Mbps), later Mbps, recently gigabit second (Gbps). Ethernet dominant network technology LANs, with advent 10-Gigabit Ethernet, entering wide area network (WAN) markets.
Altera Corporation July 2005
10-Gigabit Ethernet
purpose 10-Gigabit Ethernet proposed standard extend operating speed Gbps defined protocol IEEE 802.3 include applications. These additions provide significant increase bandwidth while maintaining maximum compatibility with current IEEE 802.3 interfaces. Since inception March 1999, 10-Gigabit Ethernet Task Force been working IEEE 802.3ae Standard. Some information following sections derived from Clauses IEEE Draft P802.3ae/D3.1 document. fully ratified standard expected first half 2002. Figure shows relationship 10-Gigabit Ethernet Open Systems Interconnection (OSI) protocol stack. Figure 8-1. 10-Gigabit Ethernet Protocol Relation Protocol Stack
Higher Layers Reference Model Layers Application Reconciliation Presentation XGMII Session XSBI Data Link Physical Medium
Transport
Network
Notes Figure 8-1:
LLC: logical link controller MAC: media access controller PCS: physical coding sublayer PHY: physical layer PMA: physical medium attachment PMD: physical medium dependent MDI: medium dependent interface
Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Ethernet (layer model) connects media (optical copper) (layer Ethernet architecture further divides (layer into sublayer, sublayer, PCS. example, optical transceivers sublayers. converts data between sublayer sublayer. made coding (e.g., 8b/10b, 64b/66b) serializer multiplexing functions. Figure shows components 10-Gigabit Ethernet Altera implements certain blocks interfaces. 10-Gigabit Ethernet three different implementations PHY: 10GBASE-X, 10GBASE-R, 10GBASE-W. 10GBASE-X implementation that supports XAUI interface. XAUI interface used conjunction with XGMII extender sublayer (XGXS) allows more separation distance between PHY. 10GBASE-X uses four lanes 8b/10b coded data rate 3.125 Gbps. 10GBASE-X wide wave division multiplexing (WWDM) PHY. 10GBASE-R 10GBASE-W serial PHYs serial PHYs, respectively. Unlike 10GBASE-X, 10GBASE-R 10GBASE-W implementations have XSBI interface described more detail following section.
Altera Corporation July 2005
Stratix Device Handbook, Volume
10-Gigabit Ethernet
Figure 8-2. 10-Gigabit Ethernet Block Diagram
Interface directly covered this application note Interface indirectly covered this application note implemented Altera PLDs
XGMII Bits 156.25 Mbps 1.5-V HSTL)
XGXS
8b/10b
XAUI Bits 3.125 Gbps PCML)
XGXS
8b/10b
XGMII Bits 156.25 Mbps 1.5-V HSTL)
8B/10B
64b/66b
64b/66b
OC-192 Framing XSBI Bits 622.08 Mbps LVDS)
XSBI Bits 644.5 Mbps LVDS)
10GBASE-X 10GBASE-R
10GBASE-W
Notes Figure 8-2:
reconciliation sublayer (RS) interfaces serial data stream parallel data XGMII. XGMII extender sublayer (XGXS) extends distance XGMII when used with XUAI provides data conversion between XGMII XAUI. interface sublayer (WIS) implements OC-192 framing scrambling functions.
Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Interfaces
following sections discuss XSBI, PCS, XGMII, XAUI.
XSBI
blocks 10-Gigabit Ethernet XSBI interface. XSBI interface between sublayers layer model. XSBI supports types layers, PHY. part 10GBASE-R, supports existing Gigabit Ethernet applications times bandwidth. part 10GBASE-W, supports connections existing future installations SONET/SDH circuit-switched access equipment. 10GBASE-R physical layer implementation that comprised sublayer, PMA, PMD. 10GBASE-R based upon 64b/66b data coding. 10GBASE-W layer implementation that comprised sublayer, interface sublayer (WIS), PMA, PMD. 10GBASE-W based STS-192c/SDH VC-4-64c encapsulation 64b/66b encoded data. Figure shows construction these layers. Figure 8-3. XSBI Interface Layers
XSBI
Medium
Medium
10GBASE-R
10GBASE-W
Altera Corporation July 2005
Stratix Device Handbook, Volume
Interfaces
Functional Description
XSBI uses 16-bit LVDS data interface between sublayer. Figure shows XSBI between these sublayers. Figure 8-4. XSBI Functional Block Diagram
REFCLK Transmitter TX_D[15.0] PMA_TXCLK PMA_TXCLK_SRC Receiver RX_D[15.0] PMA_RXCLK Sync_Err (optional) Receiver Transmitter
transmitter side, transmit data (TX_D[15.0]) output input using transmitter clock (PMA_TXCLK), which derived from source clock (PMA_TXCLK_SRC). source clock generated from with reference clock (REFCLK). receiver side, receiver data (RX_D[15.0]) output input using PMA-generated receiver clock (PMA_RXCLK). SYNC_ERR optional signal sent fails recover clock from serial data stream. ratios these clocks data dependent type used. Table shows rates both types.
Table 8-1. XSBI Clock Data Rates Parameter
TX_D[15.0] PMA_TXCLK PMA_TXCLK_SRC RX_D[15.0] PMA_RXCLK
622.08 622.08 622.08 622.08 622.08
644.53125 644.53125 644.53125 644.53125 644.53125
Unit
Mbps Mbps
Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Implementation
16-bit full duplex LVDS implementation XSBI Stratix devices shown Figure 8-5. source-synchronous implemented Stratix devices optionally includes dynamic phase alignment (DPA). automatically continuously tracks fluctuations caused system variations self-adjusts eliminate phase skew between multiplied clock serial data, allowing data rates Gbps. mode behaves similarly that Stratix I/O. This document assumes that disabled. However, simple implement same system with enabled take advantage features. more information DPA, Stratix Transceivers chapter Stratix Device Handbook, Volume Figure 8-5. Stratix Stratix Device XSBI Implementation
Data Transmitter SERDES TX_D[15.0]
Stratix Stratix PLL1 Stratix Stratix Logic Array Transmitter
PMA_TXCLK
PMA_TXCLK_SRC
Transmitter Receiver PLL2 Phase Shift 180° PMA_RXCLK
Receiver SERDES Data
RX_D[15.0]
Receiver
Altera Corporation July 2005
Stratix Device Handbook, Volume
Interfaces
transmit serializer/deserializer (SERDES) clock comes from transmitter clock source (PMA_TXCLK_SRC). receiver SERDES clock comes from receiver recovered clock (PMA_RXCLK). Figure shows transmitter output XSBI core. Data transmitted from starts core Stratix Stratix device travels Stratix Stratix transmitter SERDES block. transmitter SERDES block converts parallel data serial data individual channels (TX_D[15.0]). source clock (PMA_TXCLK_SRC) used clock signal data. PMA_TXCLK generated from same phase-locked loop (PLL) data, travels same rate data. using data channels middle clock this case, eighth channel CH8), clock-to-data skew improves. Figure 8-6. Stratix Stratix Device XSBI Transmitter Implementation
Stratix Stratix Transmitter Stratix Stratix SERDES Parallel Register Parallel-to-Serial Register
TX_D[0] Mbps
Stratix Stratix Logic Array
TX_D[7] PMA_TXCLK TX_D[8] Transmitter
CH16
TX_D[15]
Fast
PMA_TXCLK_SRC
Figure shows receiver input XSBI core. From receiver side, data (RX_D[15.0]) comes from Stratix Stratix receiver SERDES block along with receiver clock (PMA_RXCLK). receiver clock used convert serial data parallel data. phase shift inversion receiver clock needed capture receiver data.
Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Stratix Stratix devices contain eight fast PLLs. These PLLs provide high-speed outputs high-speed differential support well general- purpose clocking with multiplication phase shifting. fast incorporates this 180° phase shift. Stratix Stratix device's data realignment feature enables save more logic elements (LEs). This feature provides byte-alignment capability, which embedded inside SERDES. data realignment circuitry correct misalignments slipping data bits.
more information about fast PLLs, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume
Figure 8-7. Stratix Stratix Device XSBI Receiver Implementation
Stratix Stratix Receiver Stratix Stratix SERDES
Parallel Register
Parallel-to-Serial Register
RX_D[0] Mbps
Stratix Stratix Logic Array Receiver RX_D[15]
CH15
Fast
PMA_RXCLK_SRC
Altera Corporation July 2005
Stratix Device Handbook, Volume
Interfaces
With this XSBI transmitter receiver block implementation, each XSBI core requires fast PLLs. potential number XSBI cores device corresponds number fast PLLs each Stratix Stratix device contains. Tables show number LVDS channels, number fast PLLs, number XSBI cores that supported each Stratix Stratix device.
Table 8-2. Stratix Device XSBI Core Support Number LVDS Channels Number Fast (Receive/Transmit) PLLs
44/44 66/66 78/78 82/82 90/90 116/116 152/156
Stratix Device
Number XSBI Interfaces (Maximum)
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Note Table 8-2:
LVDS channels Mbps flip-chip packages Mbps wire-bond packages. This number includes both high speed speed channels. high speed LVDS channels Mbps. speed LVDS channels Mbps. High-Speed Differential Support chapter Stratix Device Handbook, Volume device pin-outs (www.altera.com) specify which channels high speed.
8-10 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Table 8-3. Stratix Device XSBI Core Support Number LVDS Channels Number Fast (Receive/Transmit) PLLs
22/22 39/39 45/45
Stratix Device
Number XSBI Interfaces (Maximum)
EP1SGX10 EP1SGX25 EP1SGX40 Note Table 8-3:
LVDS channels Mbps flip-chip packages Mbps wire-bond packages. This number includes both high speed speed channels. high speed LVDS channels Mbps. speed LVDS channels Mbps. High-Speed Differential Support chapter Stratix Device Handbook, Volume device pin-outs (www.altera.com) specify which channels high speed.
Timing Specifications
Stratix Stratix devices support interface. Figures Tables illustrate timing characteristics transmitter receiver interfaces. Figure shows timing diagram Stratix Stratix transmitter. determine channel-to-channel skew adding data invalid window before rising edge (Tcq_pre) data invalid window after rising edge (Tcq_post). Figure 8-8. Transmitter Timing Diagram
Tperiod PMA_TX_CLK
TX_DATA[15.0] Tcq_pre
Valid Data Tcq_post Tsetup Thold
Altera Corporation July 2005
8-11 Stratix Device Handbook, Volume
Interfaces
Table lists timing specifications transmitter.
Table 8-4. Transmitter Timing Specifications Value Parameter
PMA_TX_CLK Tperiod (WAN) PMA_TX_CLK Tperiod (LAN)
Data invalid window before rising edge (Tcq_pre) Data invalid window after rising edge (Tcq_post)
Unit
1,608 1,552
PMA_TX_CLK duty cycle
transmitter channel-to-channel skew
Figure shows timing diagram Stratix Stratix receiver interface. determine sampling window adding Tsetup Thold. Receiver skew margin (RSKM) refers amount skew tolerated printed circuit board (PCB). Figure 8-9. Receiver Timing Diagram
Tperiod PMA_RX_CLK PMA_RX_CLK Tperiod
RX_DATA[15.0] Tcq_pre
Valid Data Tcq_post Tsetup Thold
RX_DATA[15.0] Transmitter Channel-to-Channel Skew/2
RSKM Sampling Window
RSKM Transmitter Channel-to-Channel Skew/2
Table lists timing specifications receiver interface.
Table 8-5. Receiver Timing Specifications (Part Value Parameter
PMA_RX_CLK Tperiod (WAN) PMA_RX_CLK Tperiod (LAN)
Data invalid window before rising edge (Tcq_pre) Data invalid window after rising edge (Tcq_post)
Unit
1,608 1,552
8-12 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Table 8-5. Receiver Timing Specifications (Part Value Parameter
PMA_RX_CLK duty cycle
Data set-up time (Tsetup) Data hold time (Thold) sampling window RSKM (WAN) RSKM (LAN)
Unit
XGMII
purpose XGMII provide simple, inexpensive, easy implement interconnection between sublayer PHY. Though XGMII optional interface, used extensively 10-Gigabit Ethernet standard basis specification. conversion between parallel data paths XGMII serial data stream carried reconciliation sublayer. reconciliation sublayer maps signal provided XGMII physical layer signaling (PLS) service primitives provided MAC. XGMII supports 10-Gbps data rate.
Functional Description
XGMII composed independent transmit receive paths. Each direction uses data signals, TXD[31.0] RXD[31.0], control signals, TXC[3.0] RXC[3.0], clock TX_CLK RX_CLK. Figure 8-10 shows XGMII functional block diagram.
Altera Corporation July 2005
8-13 Stratix Device Handbook, Volume
Interfaces
Figure 8-10. XGMII Functional Block Diagram
TXC[3.0] XGMII RXC[3.0]
TXD[31.0]
TX_CLK RX_CLK
RXD[31.0]
Transmit
Receive
tx_data[15.0]
XSBI
rx_data[15.0]
four signals well four signals organized into four data lanes. four lanes each direction share common clock (TX_CLK transmit RX_CLK receive). four lanes used round-robin sequence carry octet stream bits data lane). reconciliation sublayer generates continuous data control characters transmit path expects continuous data control characters receive path.
Implementation
XGMII uses 1.5-V HSTL standard. Stratix Stratix devices support 1.5-V HSTL Class Class standard (EIA/JESD8-6). standard requires differential input with external reference voltage (VREF) 0.75 well termination voltage 0.75 which termination resistors connected. HSTL Class standard requires 1.5-V VCCIO voltage, which supported Stratix Stratix devices. Figure 8-11 shows 32-bit full-duplex 1.5-V HSTL implementation XGMII.
8-14 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Figure 8-11. Stratix Stratix XGMII Implementation
Stratix Stratix Output Circuitry RX_D[31.0] Shift Register RX_C[3.0] (RS)
Data
MAC_RXCLK
PLL1 Stratix Stratix Logic Array Receiver Transmitter PLL2 MAC_TXCLK
Receiver
TX_D[31.0] Data Input Circuitry Shift Register TX_C[3.0]
Transmitter
this implementation, shift register clocks either generated from divided down reconciliation sublayer transmitter clock (MAC_TXCLK), asynchronous core clock, both using FIFO buffer. Figure 8-12 shows channel output half XGMII. Data that transmitted from reconciliation sublayer starts core Stratix Stratix device travels shift register. shift register takes parallel data (even bits sent register bits sent bottom register) serializes data. After data serialized, travels double data rate (DDR) output circuitry, which clocked with clock from PLL. output circuitry, data drives off-chip along with clock. This transaction creates relationship between clock data output. This implementation only shows channel, duplicated include bits RX_D signal bits RX_C signal.
Altera Corporation July 2005
8-15 Stratix Device Handbook, Volume
Interfaces
Figure 8-12. Stratix Stratix XGMII Output Implementation (One Channel)
Stratix Stratix Output
D0,D2,D4,D6
Output Circuitry
Shift Register RX_D[0] DATA 312.5 Mbps Stratix Stratix Logic Array
D1,D3,D5,D7
DATA
Shift Register
Receiver
39.0625
156.25
MAC_RXCLK 156.25
Figure 8-13 shows channel input half XGMII interface. From receiver side, data captured from Stratix Stratix input circuitry. serial data separated into individual data streams with even bits routed register bits routed bottom register. input circuitry produces output data streams that into shift registers. From shift registers, data deserialized using clock from MAC, combining into 8-bit word. This parallel data goes register that clocked divide-by-4 clock from PLL. This data clock Stratix Stratix core. This implementation shows only channel, duplicated include bits TX_D signal bits TX_C signal.
8-16 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Figure 8-13. Stratix Stratix XGMII Input Implementation (One Channel)
Stratix Stratix Input Input Circuitry TX_D[0] DATA 312.5 Mbps
D0,D2,D4,D6
Shift Register
DATA
D1,D3,D5,D7
Transmitter
Latch
Shift Register Stratix Stratix Logic Array 156.25
MAC_TXCLK 156.25 39.0625
Stratix Stratix devices contain four enhanced PLLs. These PLLs provide features such clock switchover, spread-spectrum clocking, programmable bandwidth, phase delay control, reconfiguration. Since maximum clock rate 156.25 MHz, fast enhanced both XGMII output input blocks.
more information about fast PLLs, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume With this implementation XGMII output input blocks, number XGMII cores device corresponds number PLLs each Stratix Stratix device contains. Tables show number 1.5-V HSTL pins, PLLs, XGMII cores that supported each Stratix Stratix device. Each core requires 1.5-
Altera Corporation July 2005
8-17 Stratix Device Handbook, Volume
Interfaces
HSTL pins data control clock pins transmitter receiver clocks. Each XGMII core also needs PLLs (one each direction).
Table 8-6. Stratix XGMII Core Support Stratix Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Number 1.5-V HSTL Class Pins
1,014 1,195
Number Fast Enhanced PLLs
Number XGMII Interfaces
Table 8-7. Stratix XGMII Core Support Stratix Device
EP1SGX10 EP1SGX25 EP1SGX25 EP1SGX40
Number 1.5-V HSTL Class Pins
Number Fast Enhanced PLLs
Number XGMII Interfaces
Reduced System Noise output buffer each Stratix Stratix device programmable drive strength control certain standards. 1.5V HSTL Class standard supports minimum setting, which lowest drive strength that guarantees standard. Using minimum settings provides signal slew rate control reduce system noise signal overshoot.
more information values, Operating Conditions Switching Characteristics chapter Stratix Device Handbook, Volume Operating Conditions Switching Characteristics chapter Stratix Device Handbook, Volume
8-18 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Timing XGMII signals must meet timing requirements shown Figure 8-14. Make XGMII timing measurements driver output (shown Figure 8-14) capacitive load from sources that specified relative VIL_AC(max) VIH_AC(min) thresholds. Figure 8-14. XGMII Timing Diagram
TX_CLK RX_CLK
VIH_AC(min) VIL_AC(max)
TXC, TXD, RXC,
VIH_AC(min)
tsetup thold
VIL_AC(max)
tsetup thold
Table shows XGMII timing specifications.
Table 8-8. XGMII Timing Specifications Note Symbol
Tsetup Thold Note Table 8-8:
actual set-up hold times will made available after device characterization complete.
Driver
Receiver
Unit
Stratix Stratix devices support data with clock rates MHz, well above XGMII clock rate 156.25 MHz. HSTL Class standard, Stratix Stratix device drivers provide 1.0-V/ns slew rate input buffer receiving device.
XAUI
XAUI (pronounced Zowie) located between XGMII reconciliation sublayer XGMII layer. Figure 8-15 shows location XAUI. XAUI designed either extend replace XGMII chip-to-chip applications most Ethernet interconnects.
Altera Corporation July 2005
8-19 Stratix Device Handbook, Volume
Interfaces
Figure 8-15. XAUI Location
Reconciliation
XGMII
XGMII Extender Sublayer (XGXS)
XAUI
XGXS
XGMII
Functional Description
XAUI replace bits parallel data required XGMII transmission with just lanes serial data. XAUI uses clock data recovery (CDR) eliminate need separate clock signals. 8b/10b encoding employed data stream embed clock data. 8b/10b protocol encode 8-bit word stream 10-bit codes that results DC-balanced serial stream eases receiver synchronization. support 10-Gigabit Ethernet, each lane must speed least Gbps. Using 8b/10b encoding increases rate each lane 3.125 Gbps, which will supported Stratix Gbps devices. This circuitry supported embedded 3.125 Gbps transceivers within Stratix architecture. find more
8-20 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
information XAUI support Section Stratix Transceiver User Guide Stratix Device Handbook, Volume Figure 8-16 shows XAUI implemented. Figure 8-16. Stratix XAUI Implementation
Stratix XAUI
TX_D[0]
Stratix Logic Array
TX_D[3] Transmitter
RX_D[0]
RX_D[3] 3.125 Gbps Receiver
Characteristics XSBI, XGMII XAUI
three interfaces 10-Gigabit Ethernet (XSBI, XGMII, XAUI) each have different rates standards. Table shows characteristics each interface.
Table 8-9. 10-Gigabit Ethernet Interfaces Characteristics Interface
XGMII XSBI
Width
Clock Rate (MHz)
156.25 644.5 622.08 None
Data Rate Channel
312.5 Mbps 644.5 622.08 Mbps 3.125 Gbps
Clocking Scheme
Type
source 1.5-V synchronous HSTL source LVDS synchronous Clock data recovery (CDR) 1.5-V PCML
XAUI
Altera Corporation July 2005
8-21 Stratix Device Handbook, Volume
Characteristics XSBI, XGMII XAUI
Software Implementation
Assignment Organizer Altera® Quartus® software implement standards particular interface. example, standard LVDS XSBI HSTL Class XGMII. MegaWizard® Plug-In Manager create PLLs transmitter receiver SERDES blocks XSBI implementation PLLs input output circuitry XGMII implementation. more information Assignment Organizer MegaWizard Plug-In Manager, Quartus Software Help.
AC/DC Specifications
Table 8-10 lists XSBI electrical characteristics, similar Stratix Stratix devices, that based ANSI/TIA-644 LVDS specification.
Table 8-10. XSBI Specifications Value Parameter
Output differential voltage (VOD) Output offset voltage (VOS) Output Impedance, single ended Change between Change between Input voltage range (VI) Differential impedance Input differential voltage (VID) Receiver differential input impedance Ground potential difference (between PMA) Rise fall times (20% 80%) Note Table 8-10:
Larger possible better signal intensity.
Unit
1,375 1,600 1,125
characteristics 1.5-V HSTL standard Stratix Stratix devices shown Figure 8-17 comply with XGMII electrical specifications available 10-Gigabit Ethernet draft IEEE P802.3ae.
8-22 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Figure 8-17. Electrical Characteristics Stratix Stratix Devices (1.5-V HSTL Class
tz(min) V/ns tf(min) V/ns VSWING
VSWING Input Output tPH2 Tri-Stated Output tPL2 VIH(AC) 0.95
VREF VSWING VCCN VCCN/2 0.75
0.75 VIL(AC) 0.55
HSTL Load Circuit Class
VOUT 20pF Input Buffer VREF
Output Buffer
HSTL Waveform Interface
Altera Corporation July 2005
8-23 Stratix Device Handbook, Volume
Characteristics XSBI, XGMII XAUI
Table 8-11 lists specifications Stratix Stratix devices (1.5-V HSTL Class
Table 8-11. Specifications Stratix Stratix Devices (1.5-V HSTL Class Note Symbol
VCCIO VREF (DC) (DC) (AC) (AC)
Parameter
supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage Input leakage current High-level output voltage Low-level output voltage Output leakage current (when output high
Conditions
Minimum
0.68 VREF -0.3 VREF
Typical
0.75 0.75
Maximum
Units
VREF
VREF VCCIO VOUT VCCIO VCCIO
Note Table 8-11:
Drive strength programmable according values shown Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume
10-Gigabit Ethernet Core
Altera Megafunction Partners Program (AMPPSM) member, MorethanIP provides 10-Gigabit Ethernet core Altera customers. MorethanIP's 10-Gigabit Ethernet core implements layer, user-programmable FIFO buffers clock data decoupling.
Core Features
MorethanIP's 10-Gigabit Ethernet core provides following features:
Includes automatic pause frame generation (per IEEE 802.3 with user-programmable pause quanta pause-frame termination Includes programmable 48-bit address with promiscuous mode option, programmable Ethernet frame length that supports IEEE 802.1Q VLAN-tagged frames jumbo Ethernet frames
8-24 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing 10-Gigabit Ethernet Using Stratix Stratix Devices
Supports broadcast traffic multi-cast address resolution with 64-entry hash table Compliant with IEEE802.3ae Draft Implements XGMII, allowing interface XAUI through 10-Gigabit commercial SERDES
Conclusion
10-Gigabit Ethernet takes advantage existing Gigabit Ethernet standard. With their rich features, Stratix Stratix devices support components 10-Gigabit Ethernet well XSBI XGMII. Stratix devices also support XAUI. These interfaces easily implemented using core architecture, differential capabilities, superior PLLs Stratix Stratix devices.
Altera Corporation July 2005
8-25 Stratix Device Handbook, Volume
Characteristics XSBI, XGMII XAUI
8-26 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing SFI-4 Stratix Stratix Devices
S52011-2.0
Introduction
growth Internet created huge bandwidth demands voice, video, data push limits existing wide area network (WAN) backbones. facilitate this bandwidth growth, speeds OC-192 higher being deployed backbones (see Figure 9-1). Today's carrier backbone networks supported SONET/SDH transmission technology. SONET/SDH transmission technology transporting optical signals speeds ranging from megabits second (Mbps) gigabits second (Gbps). SONET/SDH rings make majority existing backbone infrastructure Internet public switched telephone network (PSTN). Optical Internetworking Forum (OIF) standard SFI-4 16-bit LVDS interface used OC-192 SONET system link framer serializer/deserializer (SERDES). Stratix® Stratix devices support required data rates 622.08 Mbps along with one-to-one relationship required between clock frequency data rate. fast phase-locked loop (PLL) designed support high clock frequencies one-to-one relationship (between clock data rate) needed interfaces such XSBI SFI-4. Support SFI-4 extends reach high-density programmable logic from backplane physical layer (PHY) devices. This chapter focuses implementation interface between SERDES framer.
Figure 9-1. Backbone
DWDM SONET OC-48 SONET OC-192
STM-64
SONET/SDH transmission network composed several pieces equipment, including terminal multiplexers, add-drop multiplexers, repeater digital cross-connect systems. SONET standard used North America standard used outside North America.
Altera Corporation July 2005
Introduction
SONET/SDH specification outlines frame format, multiplexing method, synchronization method, optical interface between equipment, well specific optical interface. SONET/SDH continues play role next generation networks many carriers. core network, carriers offer services such telephone, dedicated leased lines, Internet protocol (IP) data, which continuously transmitted. individual data channels transmitted separate lines; instead, they multiplexed into higher speeds transmitted SONET/SDH networks corresponding transmission speed. Figure shows typical SONET/SDH line card. system operates follows: SONET/SDH line card first takes high-speed serial optical signal converts into high-speed serial electrical signal. devices called physical media dependent (PMD) devices. system then recovers clock from electrical data using clock data recovery (CDR) unit. SERDES parallelizes data that manipulated easily lower clock rates. interface between SERDES framer called SERDES framer interface. interface requirements defined OIF. framer identifies beginning SONET/SDH frames monitors performance system. mapper following framer maps asynchronous transfer mode (ATM) cells, packets, carrier signals into SONET frame. PHY-link layer interface provides interface packet/cell processors other link-layer devices.
Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing SFI-4 Stratix Stratix Devices
Figure 9-2. SONET/SDH Line Card
Optical Signal
Module
SERDES
SONET/SDH Framer
SONET/SDH Mapper/Protocol Processor
Packet Processor Switch Fabric
Optical-Electrical Conversion
SERDES Framer Interface
Link Layer Interface
defined electrical interface (SFI) between SONET/SDH framer high-speed SERDES devices. keep with evolving transmission speeds technology enhancements, different versions electrical interfaces defined. SFI-4 version that acts interface between OC-192 SERDES SONET framer, shown Figure 9-2. aggregate 9953.28 Mbps transferred each direction. With their differential capabilities, Stratix Stratix devices ideally suited support framer side SFI-4 interface. Support SFI-4 extends reach high-density programmable logic from backplane devices.
System Topology
SFI-4 interface uses channels source-synchronous LVDS interface between SONET framer OC-192 SERDES. Figure shows SFI-4 interface.
Altera Corporation July 2005
Stratix Device Handbook, Volume
Introduction
Figure 9-3. SFI-4 Interface Signals
REFCLK SONET Framer Transmitter TXDATA[15.0] OC-192 SERDES Transmitter
TXCLK
TXCLK_SRC SONET Framer Receiver Recovered Clock Receiver
RXDATA[15.0]
RXCLK
framer transmits outbound data TXDATA[15.0] received SERDES using TXCLK. TXCLK derived from TXCLK_SRC, which provided OC-192 SERDES. framer receives incoming data RXDATA[15.0] from OC-192 SERDES. data received latched rising edge RXCLK. Table provides data rates clock frequencies specified SFI-4. modes TXCLK specified SFI-4 standard. required mode (622 clock mode mode), TXCLK should 622.08 MHz. optional mode (311 clock mode mode), TXCLK should 311.04 MHz.
Table 9-1. SFI-4 Interface Data Rates Clock Frequencies Signal
TXDATA[15.0] TXCLK TXCLK_SRC RXDATA[15.0] RXCLK REFCLK
Performance
622.08 Mbps 622.08 311.04 622.08 622.08 Mbps 622.08 622.08
Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing SFI-4 Stratix Stratix Devices
Interface Implementation Stratix Stratix Devices
16-bit full-duplex LVDS implementation framer part SFI-4 interface shown Figure 9-4. Stratix devices support sourcesynchronous interfacing LVDS differential signaling Mbps. Stratix devices have embedded SERDES circuitry serial parallel data conversion. source-synchronous implemented Stratix devices optionally includes dynamic phase alignment (DPA). automatically continuously tracks fluctuations caused system variations self-adjusts eliminate phase skew between multiplied clock serial data, allowing data rates Gbps. mode behaves similarly that Stratix I/O. This document assumes that disabled. However, simple implement same system with enabled take advantage features. more information DPA, Stratix Transceivers chapter Stratix Device Handbook, Volume fast enables 622.08 Mbps data transmission transmitting receiving differential clock rates MHz. clocks required SERDES parallel serial data conversion configured from received RXCLK (divided down), TXCLK_SRC (divided down), asynchronous core clock. Figure 9-4.
Altera Corporation July 2005
Stratix Device Handbook, Volume
Introduction
Figure 9-4. Implementation SFI-4 Interface Using Stratix Stratix Devices
REFCLK OC-192 SERDES Data Transmitter SERDES TXDATA[15.0]
Stratix Framer PLL1 Stratix Stratix Logic Array
TXCLK
TXCLK_SRC Transmitter Transmitter Receiver PLL2 Phase Shift 180° RXCLK
Data
Receiver SERDES
RXDATA[15.0]
Receiver
details differential buffers, SERDES, clock dividers using PLLs, High-Speed Differential Interfaces Stratix Devices chapter Stratix Device Handbook Stratix Device Handbook. Figure shows transmitter block (from Figure 9-4) SFI-4 framer interface implemented Stratix Stratix devices. data starts logic array goes into Stratix Stratix SERDES block. transmitter SERDES framer converts parallel data serial data TXDATA channels (TXDATA[15.0]). fast used generate TXCLK from TXCLK_SRC. fast keeps TXDATA TXCLK edge-aligned. divided down (÷8) clock generated from TXCLK_SRC used convert parallel data serial transmitter SERDES. divided down clock also clocks some logic logic array.
Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing SFI-4 Stratix Stratix Devices
Figure 9-5. Framer Transmitter Interface Stratix Stratix Devices
Stratix Stratix SFI-4 Transmitter
Stratix Stratix SERDES
Stratix Stratix Logic Array
Parallel Register
Parallel-to-Serial Register
TXDATA[0] Mbps
OC-192 SERDES TXDATA[15] TXCLK 622MHz Fast TXCLK_SRC
CH15
Figure shows receiver block (from Figure 9-4) SFI-4 framer interface implemented Stratix Stratix devices. RXDATA[15.0] received from OC-192 SERDES differential pins Stratix Stratix device. receiver SERDES converts high-speed serial data parallel. generate clocks required SERDES parallel serial data conversion from received RXCLK. RXCLK inverted (phase-shifted 180° capture received data. While normal operation guarantees that data captured, does guarantee parallelization boundary, which randomly determined based power both communicating devices. SERDES embedded data realignment capability, which used save logic elements (LEs).
Altera Corporation July 2005
Stratix Device Handbook, Volume
Introduction
Figure 9-6. Framer Receiver Interface Stratix Stratix Devices
Stratix Stratix SFI-4 Receiver
Stratix Stratix SERDES
Stratix Stratix Logic Array
Parallel Register
Serial-to-Parallel Register
RXDATA[0]
OC-192 SERDES RXDATA[15] Mbps
CH15
Fast
RXCLK
Note Figure 9-6:
figure shows Stratix disabled.
more information byte-alignment feature Stratix Stratix devices, High-Speed Differential Interfaces Stratix Devices chapter Stratix Device Handbook Stratix Device Handbook.
Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing SFI-4 Stratix Stratix Devices
Tables list number SFI-4 cores that implemented Stratix Stratix devices. High-Speed Differential Interfaces Stratix Devices chapter Stratix Device Handbook Stratix Device Handbook package type maximum number channels supported each package.
Table 9-2. Stratix SFI-4 Core Support Number LVDS Channels Stratix Device (Receiver/Transmitter)
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Note Table 9-2:
LVDS channels Mbps Gbps using Stratix devices). This number includes both high speed speed channels. high speed LVDS channels Mbps. speed LVDS channels Mbps. High-Speed Differential Support chapters Stratix Device Handbook, Volume Stratix Device Handbook, Volume device pin-outs (www.altera.com) specify which channels high speed.
Number PLLs
Number SFI-4 Interfaces (Maximum)
44/44 66/66 78/78 82/82 90/90 116/116 152/156
Table 9-3. Stratix SFI-4 Core Support Stratix Device
EP1SGX10 EP1SGX25 EP1SGX40 Note Table 9-3:
LVDS channels Mbps, Gbps using DPA. This number includes both high speed speed channels. high speed LVDS channels Mbps. speed LVDS channels Mbps. High-Speed Differential Support chapter Stratix Device Handbook, Volume Stratix Device Handbook, Volume device pin-outs (www.altera.com) specify which channels high speed.
Number LVDS Channels (Receiver/Transmitter)
22/22 39/39 45/45
Number PLLs
Number SFI-4 Interfaces (Maximum)
Altera Corporation July 2005
Stratix Device Handbook, Volume
Introduction
Timing Specifications
Figures through Tables through illustrate timing characteristics SFI-4 framer. Stratix Stratix devices support timing requirements needed support transmitter receiver functions SFI-4 framer; only framer-related timing specifications applicable.
details timing specifications LVDS standards Stratix Stratix devices, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Differential Interfaces Stratix Devices chapter Stratix Device Family Data Sheet section Stratix Device Handbook, Volume HighSpeed Differential Interfaces Stratix Devices chapter Figure shows timing diagram Stratix Stratix framer transmitter (622 clock) mode. Figure 9-7. Framer Transmitter (622 Clock) Mode Timing Diagram
Tperiod
TX_DATA[15.0] Tcq_pre
Valid Data Tcq_post Tsetup Thold
Table lists timing specifications SFI-4 framer transmitter (622 clock) mode. Table 9-4. SFI-4 Framer Transmitter (622 Clock) Mode Timing Specifications Value Parameter
TX_CLK (Tperiod)
Data invalid window before rising edge (Tcq_pre) Data invalid window after rising edge (Tcq_post)
Unit
1,608
TX_CLK duty cycle
Framer transmitter channel-to-channel skew
9-10 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing SFI-4 Stratix Stratix Devices
Figure shows timing diagram SFI-4 framer transmitter (311 clock) mode Figure 9-8. Framer Transmitter (311 Clock) Mode Timing Diagram
Tperiod/2 TX_CLK(P)
TX_DATA[15.0] Tcq_pre
Valid Data Tcq_post
Valid Data
Table lists timing specifications SFI-4 framer transmitter (311 clock) mode. Table 9-5. SFI-4 Framer Transmitter (311 Clock) Mode Timing Specifications Value Parameter
TX_CLK (Tperiod)
Data invalid window before rising edge (Tcq_pre) Data invalid window after rising edge (Tcq_post)
Unit
3,215
TX_CLK duty cycle
Framer transmitter channel-to-channel skew
Figure shows timing diagram SFI-4 framer receiver. Figure 9-9. Framer Receiver Timing Diagram
Tperiod RX_CLK(P) RX_CLK(P) Tperiod
RX_DATA[15.0] Tcq_pre
Valid Data Tcq_post
RX_DATA[15.0] Tsetup Thold Transmitter Channel-to-Channel Skew/2
RSKM Sampling Window
RSKM Transmitter Channel-to-Channel Skew/2
Altera Corporation July 2005
9-11 Stratix Device Handbook, Volume
Introduction
Table lists timing specifications SFI-4 framer receiver.
Table 9-6. Framer Receiver Timing Specifications Value Parameter
RX_CLK (Tperiod)
Data invalid window before rising edge (Tcq_pre) Data invalid window after rising edge (Tcq_post)
Unit
1,608
RX_CLK duty cycle
Data set-up time (Tsetup) Data hold time (Thold) Framer sampling window Receiver skew margin (RSKM)
Electrical Specifications
SFI-4 uses LVDS high-speed data transfer mechanism implement SFI-4 interface. Table lists electrical characteristics interface, which based IEEE Std. 1596.3-1996 specification. more information voltage specification LVDS standards Stratix Stratix devices, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Differential Interfaces Stratix Devices chapter Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Differential Interfaces Stratix Devices chapter.
9-12 Stratix Device Handbook, Volume
Altera Corporation July 2005
Implementing SFI-4 Stratix Stratix Devices
Table 9-7. Framer LVDS Specifications Value Parameter
Output differential voltage (VOD) Output offset voltage (VOS) Output Impedance, single ended Change between Change between Input voltage range (VI) Differential impedance Input differential voltage (VID) Receiver differential input impedance Ground potential difference (between PMA) Rise fall times (20% 80%) Note Table 9-7:
IEEE standard requires larger swing encouraged, required.
Unit
1,375 2,400 1,125
Software Implementation
SFI-4 interface uses 16-bit LVDS interface. Altera® Quartus® software version supports Stratix Stratix devices, allowing implement LVDS buffers through Quartus Assignment Organizer.
information Quartus Assignment Organizer, Quartus Software Help.
Conclusion
SFI-4 standard interface between SONET framers optical SERDES OC-192 interfaces. With embedded SERDES fast PLLs, Stratix Stratix devices easily support SFI-4 framer interface, enabling 10-Gbps (OC-192) data transfer rates. Stratix Stratix supports required data rates 622.08 Mbps. Stratix Stratix fast PLLs designed support high clock frequencies one-to-one relationship needed interfaces such XSBI SFI-4. Stratix Stratix devices support multiple SFI-4 functions device.
Altera Corporation July 2005
9-13 Stratix Device Handbook, Volume
Introduction
9-14 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
S52012-3.0
Introduction
Stratix® Stratix devices Altera's next-generation, system-ona-programmable-chip (SOPC) solution. Stratix Stratix devices simplify block-based design methodology bridge between system bandwidth requirements programmable logic performance. This chapter highlights features Stratix Stratix devices provides assistance when transitioning designs from APEXII APEX devices Stratix Stratix architecture. should familiar with APEX APEX architecture available device features before using this chapter. this chapter conjunction with Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume
General Architecture
Stratix Stratix devices offer many features architectural enhancements. Enhanced logic elements (LEs) MultiTrackinterconnect structure offer reduced resource utilization considerable design performance improvement. MultiTrack interconnect uses DirectDrivetechnology ensure availability deterministic routing resources design block, regardless placement within device. architectural changes between Stratix Stratix APEX APEX devices described this section require design changes. However, must resynthesize your design recompile Quartus® software target Stratix Stratix devices.
Altera Corporation July 2005
10-1
General Architecture
Logic Elements
Stratix Stratix device include several new, advanced features that improve design performance reduce logic resource consumption (see Table 10-1). Quartus software automatically uses these features improve device utilization.
Table 10-1. Stratix Stratix Features Feature Function Benefit
Conserves resources Register chain interconnects Direct path between register output Provides fast shift register register input adjacent within same logic array implementation Saves local interconnect routing block (LAB) resources within Look-up table (LUT) chain interconnects Direct path between combinatorial Allows LUTs within same output fast input cascade together high-speed wide adjacent within same fan-in functions, such wide operations Bypasses local interconnect faster performance Allows register output feed back into same such that register packed with fanout Uses implementing both adder subtractor Enhanced register packing mode Uses resources more efficiently
Register-to-LUT feedback path
Dynamic arithmetic mode
Improves performance functions that switch between addition subtraction frequently, such correlators
Carry-select chain
Calculates outputs possible carryGives immediate access result parallel both carry-in Increases speed carry functions high-speed operations, such counters, adders, comparators Supports direct asynchronous clear preset functions Conserves resources Does require additional logic resources implement NOT-gate push-back
Asynchronous clear asynchronous preset function
addition features described Table 10-1, there enhancements chains that connect together. Carry chains implemented vertically Stratix Stratix devices, instead horizontally APEX APEX devices, continue across rows, instead across columns, shown Figure 10-1. Also note that Stratix Stratix architectures support cascade primitive. Therefore, Quartus Compiler automatically converts
10-2 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
cascade primitives APEX APEX designs wire primitive when compiled Stratix Stratix devices. These architectural changes transparent user require design changes. Figure 10-1. Carry Chain Implementation APEX APEX Devices Stratix Stratix Devices
APEX APEX Devices Carry Chains Stratix Devices
Carry-Select Chains
LABs (with Each)
MultiTrack Interconnect
Stratix Stratix devices MultiTrack interconnect structure provide high-speed connection between logic resources using performance-optimized routing channels different lengths. This feature maximizes overall design performance placing critical paths routing lines with greater speed, resulting minimal propagation delay.
Altera Corporation July 2005
10-3 Stratix Device Handbook, Volume
General Architecture
Stratix Stratix device MultiTrack interconnect resources described Table 10-2.
Table 10-2. Stratix Stratix Device MultiTrack Interconnect Resources Routing Type
Column Column Column
Interconnect
Direct link
Span
Adjacent LABs and/or blocks Four units horizontally Eight units horizontally Horizontal routing across width device Four units vertically Eight units vertically Vertical routing across length device
Direct link routing saves routing resources while providing fast communication paths between resource blocks. Direct link interconnects allow LAB, digital signal processing (DSP) block, TriMatrixmemory block drive data into local interconnect left right neighbors. LABs, blocks, TriMatrix memory blocks also direct link interconnects drive data back into themselves feedback. Quartus software automatically uses these routing resources enhance design performance.
more information about architecture MultiTrack interconnect structure Stratix Stratix devices, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume
DirectDrive Technology
When using APEX devices, must place critical paths same MegaLABcolumn improve performance. Additionally, should place critical paths same MegaLAB structure optimal performance. However, this restriction does exist Stratix Stratix devices because they contain MegaLAB structures. With DirectDrivetechnology Stratix Stratix devices, actual distance between source destination path most important criteria meeting timing performance. DirectDrive technology ensures that same routing resources available each design block, regardless location device.
10-4 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
Architectural Element Names
architectural element naming system within Stratix Stratix devices differs from row-column coordinate system (for example, LC1_A2, LAB_B1) used previous Altera device families. Stratix Stratix devices uses naming system based coordinate system, number designates location within block where logic resides, such within LAB. Because Stratix Stratix architectures column-based, this naming simplifies location assignments. Stratix Stratix architectural blocks include:
LAB: logic array block DSP: digital signal processing block DSPOUT: adder/subtractor/accumulator summation block block M512: 512-bit memory block M4K: 4-Kbit memory block M-RAM: 512-Kbit memory block
Elements within architectural blocks include:
logic element IOC: element PLL: phase-locked loop DSPMULT: block multiplier SERDESTX: transmitter serializer/deserializer SERDESRX: receiver serializer/deserializer
Altera Corporation July 2005
10-5 Stratix Device Handbook, Volume
General Architecture
Table 10-3 highlights location syntax used Stratix Stratix devices.
Table 10-3. Stratix Stratix Location Assignment Syntax Architectural Elements
Blocks
Example Location Syntax Element Name Location Syntax Location
LAB, DSP, <element_name>_X<number> LAB_X1_Y1 DSPOUT, M512, _Y<number> M4K, M-RAM IOC, PLL, DSPMULT, SERDESTX, SERDESRX
pins <element_name>_X<number> LC_X1_Y1_N0 _Y<number>_N<number>
Description
Designates column Designates first located column
Logic
Pins
pin_<pin_label>
pin_5
Note Table 10-3:
make assignments pads using
following guidelines with naming system:
anchor point, origin, Stratix Stratix devices bottom-left corner, instead top-left corner APEX APEX devices. anchor point, origin, large block element (e.g., M-RAM block) also bottom-left corner. numbers zero-based, meaning origin bottom-left device pins constitute first last rows columns coordinates. Therefore, bottom pins resides X<number>, first left column pins resides Y<number>. sub-location elements, numbering begins top. Therefore, still numbered from bottom, start zero.
Figure 10-2 show Stratix Stratix architectural element numbering convention. Figure 10-3 displays floorplan view Quartus software.
10-6 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
Figure 10-2. Stratix Stratix Architectural Elements Note
Blocks Units Wide Unit High
(1,18)
(11,18)
M512 (12,18)
(13,18)
(14,18)
(16,18)
Block (17,1) Units Wide Eight Units High
(1,17)
(11,17)
M512 (12,17)
(13,17)
(14,17)
(16,17)
(1,16)
(11,16)
M512 (12,16)
(13,16)
(14,16)
(16,16)
DSPMULT (17,7,0) (17,7,1)
(1,15)
(11,15)
M512 (12,15)
(13,15)
(14,15)
(16,15)
(14,14)
(16,14)
DSPMULT (17,5,0) (17,5,1)
(14,13) Mega Block Units Wide Units High
(16,13)
DSPOUT (18,1,0) (18,1,7)
Mega (1,2)
DSPMULT (17,3,0) (17,3,1)
Pins
(14,2)
(16,2) DSPMULT (17,1,0) (17,1,1)
(0,1,0)
(1,1)
(11,1)
M512 (12,1)
(13,1)
(14,1)
(16,1)
Origin
Notes Figure 10-2:
Figure 10-2 shows part Stratix Stratix device. Large block elements their lower-left corner coordinate location. Stratix architectural elements include transceiver blocks right side device.
Altera Corporation July 2005
10-7 Stratix Device Handbook, Volume
TriMatrix Memory
Figure 10-3. Numbering Shown Quartus Software
TriMatrix Memory
TriMatrix memory three different sizes memory blocks, each optimized different purpose application. M512 blocks consist bits plus parity (576 bits), blocks consist bits plus parity (4,608 bits), M-RAM blocks consist 512K bits plus parity (589,824 bits). This structure differs from APEX APEX devices, which feature uniformly sized embedded system blocks (ESBs) either Kbits (APEX devices) Kbits (APEX devices) large. Stratix Stratix TriMatrix memory blocks give advanced control each memory block, with features such byte enables, parity storage, shift-register mode, well mixed-port width support true dual-port mode operation.
10-8 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
Table 10-4 compares TriMatrix memory with ESBs.
Table 10-4. Stratix Stratix TriMatrix Memory Blocks APEX APEX ESBs Stratix Stratix Features M512
Size (bits) Parity bits Byte enable True dual-port mode Embedded shift register Dedicated contentaddressable memory (CAM) support Pre-loadable initialization with .mif Packed mode Feed-through behavior Output power-up condition
APEX
4,608
APEX
2,048
M-RAM
589,824 4,096
Includes support Includes support Includes support mixed width mixed width mixed width
Rising edge Powers cleared even using .mif
Rising edge Powers cleared even using .mif
Rising edge Powers with unknown state
Falling edge Powers cleared initialized value, using .mif
Falling edge Powers cleared initialized value, using .mif
Notes Table 10-4:
.mif: Memory Initialization File. Packed mode refers combining single-port blocks into single block that placed into true dual-port mode.
Stratix Stratix TriMatrix memory blocks only support pipelined mode, while APEX APEX ESBs support both pipelined flow-through modes. Since TriMatrix memory blocks pipelined, input data address lines registered, while outputs either registered combinatorial. Stratix Stratix memory block registers implement input output registers without utilizing additional resources. compile designs containing pipelined memory blocks (inputs registered) Stratix Stratix devices without modifications. However, APEX
Altera Corporation July 2005
10-9 Stratix Device Handbook, Volume
TriMatrix Memory
APEX design contains flow-through memory, must modify memory modules target Stratix Stratix architectures (see "Memory Megafunctions" page 10-12 more information).
more information about TriMatrix memory converting flowthrough memory modules pipelined, TriMatrix Embedded Memory Blocks Stratix Stratix Devices chapter Stratix Device Handbook 210: Converting Memory from Asynchronous Synchronous Stratix Stratix Designs.
Same-Port Read-During-Write Mode
same-port read-during-write mode, block singleport, simple dual-port, true dual-port mode. port from block both reads writes same address location using same clock. When APEX APEX devices perform same-port readduring-write operation, data available falling edge clock cycle which written, shown Figure 10-4. When Stratix Stratix devices perform same-port read-during-write operation, data available rising edge same clock cycle which written, shown Figure 10-5. This holds true TriMatrix memory blocks. Figure 10-4. Falling Edge Feed-Through Behavior (APEX APEX Devices) Note
inclock data_in
wren
data_out
Note Figure 10-4:
Figures 10-4 10-5 assume that address stays constant throughout that outputs registered.
10-10 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
Figure 10-5. Rising Edge Feed-Through Behavior (Stratix Stratix Devices) Note
inclock data_in
wren
data_out
Note Figure 10-5:
Figures 10-4 10-5 assume that address stays constant throughout that outputs registered.
Mixed-Port Read-During-Write Mode
Mixed-port read-during-write mode occurs when block simple true dual-port mode port reading other port writing same address location using same clock. APEX APEX designs, outputs data first half clock cycle data second half clock cycle, indicated Figure 10-6. Figure 10-6. Mixed-Port Feed-Through Behavior (APEX APEX Devices) Note
inclock Port data_in Port wren Port wren Port data_out
Note Figure 10-6:
Figure 10-6 assumes that outputs registered.
Stratix Stratix device outputs data rising edge clock cycle immediately after data written. When Stratix Stratix M512 blocks, choose whether output data targeted address output don't care value during clock cycle when data written. M-RAM blocks
Altera Corporation July 2005
10-11 Stratix Device Handbook, Volume
TriMatrix Memory
always output don't care value. Figures 10-7 10-8 show feedthrough behavior mixed-port mode. altsyncram megafunction output behavior during mixed-port read-duringwrite mode. Figure 10-7. Mixed-Port Feed-Through Behavior (OLD_DATA) Note
inclock addressA addressB Port data_in Port wren Port wren Port data_out Address
Note Figure 10-7:
Figures 10-7 10-8 assume that address stays constant throughout that outputs registered.
Figure 10-8. Mixed-Port Feed-Through Behavior (DONT_CARE) Note
inclock addressA addressB Port data_in Port wren Port wren Port data_out Unknown Address
Note Figure 10-8:
Figures 10-7 10-8 assume that address stays constant throughout that outputs registered.
Memory Megafunctions
convert originally targeting APEX APEX architecture Stratix Stratix memory, specify Stratix Stratix target family MegaWizard Plug-In Manager. software
10-12 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
updates memory module Stratix Stratix architecture instantiates synchronous memory megafunction, altsyncram, which supports both blocks Stratix Stratix architectures.
FIFO Conditions
First-in first-out (FIFO) functionality slightly different Stratix Stratix devices compared APEX APEX devices. Stratix Stratix devices support simultaneous reads writes from empty FIFO buffer. Also, Stratix Stratix devices support lpm_showahead parameter when targeting FIFO buffer because TriMatrix memory blocks synchronous. lpm_showahead parameter APEX APEX devices puts FIFO buffer "read-acknowledge" mode first data written into FIFO buffer immediately flows through output. Other than these differences, APEX APEX FIFO functions fully compatible with Stratix Stratix architectures.
Design Migration Mode Quartus Software
Quartus software features migration mode simplifying process converting APEX APEX memory functions Stratix Stratix architecture. design Stratix Stratix altsyncram megafunction replacement previous APEX APEX memory function while maintaining functionally similar behavior, Quartus software automatically converts memory. software produces warning message during compilation reminding verify that design migrated correctly. memory blocks with inputs registered, existing megafunction converted altsyncram megafunction. software generates warning when altsyncram megafunction incompatible. example, block with inputs registered except read enable compiles with warning message indicating that read-enable port registered. suppress warning messages entire project individual memory blocks setting parameter "on" global parameter selecting Assignment Organizer (Tools menu). Assignment Organizer window, click Parameters Assignment Categories box. Type Assignment Name type Assignment Setting box. suppress these warning messages per-memory-instance basis, parameter Assignment Organizer "on" memory instance.
Altera Corporation July 2005
10-13 Stratix Device Handbook, Volume
TriMatrix Memory
functionality APEX APEX memory megafunction differs from altsyncram functionality least clock feeds memory megafunction, Quartus software converts APEX APEX memory megafunction Stratix Stratix altsyncram megafunction. This conversion useful initial evaluation design might perform Stratix Stratix devices should only used evaluation purposes. During this process, Quartus software generates warning that conversion functionally incorrect timing results accurate. Since functionality incorrect compilation only intended comparative purposes, Quartus software does generate programming file. functionally correct conversion requires manually instantiating altsyncram megafunction require additional design changes. previous memory function does have clock (fully asynchronous), fitting-evaluation conversion results error message during compilation does successfully convert design.
210: Converting Memory from Asynchronous Synchronous Stratix Stratix Designs more information. Table 10-5 summarizes possible scenarios when using design migration mode resulting behavior Quartus software. most common cases where design-migration mode have difficulty converting existing design when:
port reading from address that being written another port (mixed-port read-during-write mode). both ports using same clock, read port Stratix Stratix devices data until next clock cycle, after data written.
10-14 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
There differences power-up behavior between APEX APEX 20K, Stratix Stratix devices. should manually account these differences maintain desired operation system.
Table 10-5. Migration Mode Summary Memory Configuration
Single-port
Conditions
Possible Instantiated Megafunctions
altrom lpm_ram_dq lpm_ram_io lpm_rom
Quartus Warning Message(s)
Power-up differences.
Programming File Generated
inputs registered. altram
inputs registered. altdpram Multi-port (two-, three-, four-port lpm_ram_dp functions) altqpram
Power-up differences. Mixed-port read- duringwrite. Power-up differences. Mixed-port read- duringwrite. Read enable will registered.
alt3pram
Dual-port Read-enable ports unregistered. Other inputs registered.
altdpram lpm_ram_dp altqpram alt3pram altdpram lpm_ram_dp altqpram alt3pram altram lpm_ram_dq lpm_ram_io altram altrom altdpram altqpram alt3pram altdpram lpm_ram_dq lpm_ram_io lpm_rom lpm_ram_dp lpm_ram_dp
Dual-port
other unregistered port except read-enable ports. Clock available. least registered input. Clock available. clock.
Compile fitting- evaluation purposes.
Single-port
Compile fitting- evaluation purposes. Error conversion possible.
clock
Note Table 10-5:
parameter turned Quartus software does issue these warnings.
Altera Corporation July 2005
10-15 Stratix Device Handbook, Volume
Block
Block
Stratix Stratix device blocks outperform LE-based implementations common functions. Each block contains several multipliers that configured widths bits. Depending mode operation, these multipliers optionally feed adder/subtractor/accumulator summation unit. configure block's input registers efficiently implement shift registers serial input sharing, eliminating need external shift registers LEs. pipeline registers block accelerated operation. Registers available input output multiplier, output adder/subtractor/accumulator summation block. blocks have four modes operation:
Simple multiplier mode Multiply-accumulator mode Two-multipliers adder mode Four-multipliers adder mode
Associated megafunctions available Quartus software implement each mode block.
Block Megafunctions
lpm_mult megafunction configure block simple multiplier mode. lpm_mult Multiplier Implementation option MegaWizard Plug-In Manager either default implementation, ESBs, blocks. select Default option, compiler first attempts place multiplier blocks. However, under certain conditions, compiler implement multiplier LEs. placement depends factors such block resource consumption, width multiplier, whether operand constant, other options chosen megafunction. Stratix Stratix devices support ESBs option. select this option, Quartus software tries place multiplier unused blocks. recompile APEX APEX designs using lpm_mult megafunction Stratix Stratix devices Quartus software without changing megafunction. This makes converting lpm_mult megafunction designs Stratix Stratix devices straightforward.
10-16 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
APEX APEX designs pipeline stages improve registered performance LE-based multipliers expense latency. However, need pipeline stages when targeting Stratix Stratix high-speed blocks. blocks offer three sets dedicated pipeline registers. Therefore, Altera recommends that reduce number pipeline stages three fewer implement them blocks. Additional pipeline stages implemented LEs, which latency without providing performance benefit. example, configure block 36-bit multiplication using lpm_mult megafunction. specify pipeline stages, software uses block input pipeline registers. specify three pipeline stages, software places third pipeline stage block output registers. This design yields same performance with three pipeline stages because critical path 36-bit operation within multiplier. With four more pipeline stages, device inefficiently uses resources additional pipeline stages. Therefore, multiplier modules APEX APEX designs converted Stratix Stratix designs require same number pipeline stages, surrounding circuitry must modified preserve original functionality design. design with multipliers feeding accumulator altmult_accum (MAC) megafunction block multiplyaccumulator mode. APEX APEX design already uses LEbased multipliers feeding accumulator, Quartus software does automatically instantiate altmult_accum (MAC) megafunction. Therefore, should MegaWizard Plug-In Manager instantiate altmult_accum (MAC) megafunction. also LeonardoSpectrumor Synplify synthesis tools, which have block inference support, instantiate megafunction. Designs that multipliers feeding into adders instantiate altmult_add megafunction configure blocks twomultipliers adder four-multipliers adder mode. also altmult_add megafunction stand-alone multipliers take advantage blocks features such dynamic sign control inputs input shift register connections. These features accessible through lpm_mult megafunction. your APEX APEX designs already multipliers feeding adder/subtractor, Quartus software does automatically infer altmult_add megafunction. Therefore, should step through MegaWizard Plug-In Manager instantiate altmult_add megafunction LeonardoSpectrum Synplify synthesis tools, which have block inference support.
Altera Corporation July 2005
10-17 Stratix Device Handbook, Volume
PLLs Clock Networks
Furthermore, altmult_add altmult_accum (MAC) megafunctions only available Stratix Stratix devices because these megafunctions target Stratix Stratix blocks, which available other device families. attempt these megafunctions designs that target other Altera device families, Quartus software reports error message. lpm_mult lpm_add_sub altaccumulate megafunction similar functionality other device families. third-party synthesis tool, able avoid megafunction conversion process. LeonardoSpectrum Synplify provide inference support lpm_mult, altmult_add, altmult_accum (MAC) blocks. your design does require implement multipliers blocks, must manually global parameter parameter each instance force tool implement lpm_mult megafunction LEs. Depending synthesis tools, inference blocks handled differently.
more information about using blocks Stratix Stratix devices, Blocks Stratix Stratix Devices chapter Stratix Device Handbook. Stratix Stratix devices provide exceptional clock management with hierarchical clock network four enhanced phase-locked loops (PLLs) eight fast PLLs versus four general-purpose PLLs four True-LVDSPLLs APEX devices. providing superior clock interfacing, numerous advanced clocking features, significant enhancements over APEX APEX PLLs, Stratix Stratix device PLLs increase system performance bandwidth.
PLLs Clock Networks
Clock Networks
There global clock networks available throughout each Stratix Stratix device well fast regional four regional clock networks device quadrant, resulting unique clock networks device. increased number dedicated clock resources available Stratix Stratix devices eliminate need general-purpose pins clock inputs. Stratix EP1S25 smaller devices have dedicated clock pins EP1S30 larger devices have four additional clock pins feed various clocking networks. comparison, APEX devices have eight dedicated clock pins APEX 20KE APEX 20KC devices have four dedicated clock pins.
10-18 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
dedicated clock pins Stratix Stratix devices feed clock inputs, global clock networks, regional clock networks. outputs internally-generated signals also drive global clock network. These global clocks available throughout entire device clock device resources. Stratix Stratix devices divided into four quadrants, each equipped with four regional clock networks. regional clock network either dedicated clock pins outputs within device quadrant. regional clock network only feed device resources within particular device quadrant. Each Stratix Stratix device provides eight dedicated fast clock pins FCLK[7.0] versus four dedicated fast pins APEX APEX devices. fast regional clock network these dedicated FCLK[7.0] pins interconnect. interconnect allows internal logic drive fast regional clock network. fast regional clock network available generalpurpose clocking well high fan-out control signals such clear, preset, enable, TRDY IRDY applications, bidirectional output pins. EP1S25 smaller devices have eight fast regional clock networks, device quadrant. quadrants EP1S30 larger devices divided half, each half-quadrant clocked eight fast regional networks. Additionally, each fast regional clock network drive neighboring half-quadrant (within same device quadrant).
PLLs
Table 10-6 highlights Stratix Stratix enhancements existing APEX APEX 20KE APEX 20KC features.
Table 10-6. Stratix Stratix APEX APEX 20KE APEX 20KC Features (Part Stratix Stratix Feature Enhanced PLLs
Number PLLs (EP1S30 smaller devices); four (EP1S40 larger devices)
APEX PLLs Fast PLLs
Four (EP1S25 Four generalpurpose PLLs smaller devices); four LVDS PLLs eight (EP1S30 larger devices) (10)
APEX 20KE APEX 20KC PLLs
four generalpurpose PLLs. LVDS PLLs.
Minimum input frequency Maximum input frequency
644.5 (11)
Altera Corporation July 2005
10-19 Stratix Device Handbook, Volume
PLLs Clock Networks
Table 10-6. Stratix Stratix APEX APEX 20KE APEX 20KC Features (Part Stratix Stratix Feature Enhanced PLLs
Internal clock outputs External clock outputs Four differential/eight singled-ended single-ended Down 160-ps increments
APEX PLLs Fast PLLs
APEX 20KE APEX 20KC PLLs
Phase Shift Time shift counter values counter values clock input sharing T1/E1 rate conversion Notes Table 10-6:
Down 125-ps increments
500-ps 1-ns resolution
0.4- 1-ns resolution
250-ps increments
EP20K200E smaller devices only have general-purpose PLLs. EP20K400E larger devices have LVDS PLLs four general-purpose PLLs. more information, 115: Using ClockLock ClockBoost Features APEX Devices. maximum input frequency Stratix Stratix enhanced PLLs depends standard used with that input clock pin. more information, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Fast PLLs have three internal clock output ports PLL. Fast PLLs have internal clock output ports PLL. Every Stratix device enhanced PLLs with eight single-ended four differential outputs each. additional enhanced PLLs EP1S80, EP1S60, EP1S40 devices each have single-ended output. driven fast global regional outputs external clock output pin. smallest phase shift unit determined voltage-controlled oscillator (VCO) period divided There maximum between clock outputs. clock frequency 1.544 clock frequency 2.048 MHz, which violates minimum clock input frequency requirement Stratix PLL. Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX40 contains four. (10) Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX40 contains four. (11) Stratix supports clock rates Gbps using DPA.
Enhanced PLLs
Stratix Stratix devices provide four enhanced PLLs with advanced features. addition feature changes mentioned Table 10-6, Stratix Stratix device PLLs include many new,
10-20 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
advanced features improve system timing management performance. Table 10-7 shows some features available Stratix Stratix enhanced PLLs.
Table 10-7. Stratix Stratix Enhanced Features Feature
clock outputs feed logic array locked output feed logic array Multiplication allowed zero-delay buffer mode external feedback mode Programmable phase shift allowed zero-delay buffer mode external feedback mode Phase frequency detector (PFD) disable Clock output disable Programmable lock detect gated lock Dynamic clock switchover reconfiguration Programmable bandwidth Spread spectrum Notes Table 10-7:
These features also available fast PLLs. addition delay chains each counter, specify programmable phase shift each output fine coarse levels. Each clock output associated clock enable signal. used external feedback mode, will need relock.
Description
Allows clock outputs feed data ports registers combinatorial logic. Allows locked port feed data ports registers combinatorial logic. clock outputs multiplied divided down ratio input clock. clock outputs phase shifted. phase shift relative clock output.
Programmable duty cycle Allows variable duty cycle each clock output.
Allows operate last control voltage frequency with some long term drift. maintains lock with output clocks disabled. Holds lock signal programmable number input clock cycles. Enables switch between reference input clocks, either clock redundancy dual-clock domain applications. Allows counters delay elements within reconfigured realtime without reloading programmer object file (.pof). Provides advanced control bandwidth using programmable control loop characteristics. Modulates target frequency over frequency range reduce electromagnetic interference (EMI) emissions.
Fast PLLs
Stratix Stratix fast PLLs similar APEX True-LVDS PLLs that setting, which governs relationship between clock input data rate, setting, which controls width
Altera Corporation July 2005
10-21 Stratix Device Handbook, Volume
PLLs Clock Networks
high-speed differential data bus, have equal. Additionally, Stratix Stratix fast PLLs offer three clock outputs, multiplied high-speed clocks drive serializer/deserializer (SERDES) block and/or external pin, low-speed clock drive logic array. fast PLLs both high-speed interfacing general-purpose applications. Table 10-8 shows differences between Stratix Stratix fast PLLs APEX APEX True-LVDS PLLs.
Table 10-8. Stratix Stratix Fast APEX APEX True-LVDS Feature
Number fast PLLs TrueLVDS PLLs
Stratix Stratix
Four (EP1S25 smaller devices) fast PLLs Eight (EP1S30 larger devices) fast PLLs
APEX
Four True-LVDS PLLs
APEX 20KE APEX 20KC
True-LVDS PLLs
Number channels transmitter/receiver block frequency Minimum input frequency Minimum input frequency Notes Table 10-8:
1GHz
also Stratix Stratix device fast PLLs general-purpose applications. EP20K400E larger devices have True-LVDS PLLs. APEX 20KE APEX 20KC devices, Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX10 contains four. Stratix supports frequency range 300-1000 (using DPA).
Stratix Stratix fast frequency range MHz, APEX True-LVDS frequency range GHz. Therefore, must update designs that data rate less than megabits second (Mbps) enhanced PLLs M512 blocks SERDES bypass mode. Additionally, must update designs that data rate faster than Mbps.
altpll Megafunction
Altera recommends that replace instances altclklock megafunction with altpll megafunction take advantage Stratix Stratix features. Although most cases retarget your APEX APEX design Stratix Stratix
10-22 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
device with altclklock megafunction, there specific cases where must altpll megafunction, explained this section. MegaWizard Plug-In Manager, select altpll megafunction directory from Available Megafunctions (see Figure 10-9). altclklock megafunction also available from Quartus software backward compatibility, instantiates altpll megafunction when targeting Stratix Stratix devices. Quartus Compiler automatically selects whether altpll module uses either enhanced fast based design's needs feature requirements each PLL. Figure 10-9. altpll Megafunction Selection MegaWizard Plug-In Manager
compile APEX APEX 20KE, APEX 20KC designs using altclklock megafunction normal mode Stratix Stratix devices without updating megafunction. However, should replace altclklock megafunction with altpll megafunction. Quartus software cannot implement requested clock multiplication division PLL, compiler reports error message with appropriate reason stated.
Altera Corporation July 2005
10-23 Stratix Device Handbook, Volume
PLLs Clock Networks
APEX APEX 20KE, APEX 20KC devices have only external clock output available PLL. Therefore, when retargeting APEX APEX 20KE, APEX 20KC design that uses PLLs zero delay buffer mode external feedback mode Stratix Stratix device, should replace instances altclklock megafunction. APEX APEX 20KE, APEX 20KC altclklock module only uses clock output (internal external) compiled target Stratix Stratix device, design compiles successfully with warning that design uses Stratix Stratix external clock output, extclk0. However, APEX APEX 20KE, APEX 20KC more than clock output, must replace instances altclklock megafunction with altpll megafunction because Quartus Compiler does know which clock output external output back Stratix Stratix device fbin pin. example, APEX APEX 20KE, APEX 20KC design with altclklock megafunction uses clock0 output port feed external clock output clock1 output port feed internal logic array, Quartus software generates error during compilation must MegaWizard Plug-In Manager instantiate altpll megafunction. using altpll megafunction, choose which four external clock outputs take advantage Stratix Stratix features available zero delay buffer mode external feedback mode.
Timing Analysis
When Quartus software performs timing analysis APEX APEX 20KE, APEX 20KC designs, clock settings override project clock settings. However, during timing analysis Stratix Stratix designs using PLLs, project clock settings override input clock frequency duty cycle settings. MegaWizard Plug-In Manager does project clock settings determine altpll parameters. This saves time with designs that features such clock switchover reconfiguration because Quartus software perform timing analysis without recompiling design. important note following:
warning during compilation reports that project clock settings overrides clock settings. project clock setting overrides clock settings timingdriven compilation. compiler will check lock frequency range PLL. frequency specified project clock settings outside lock frequency range, clock settings will overridden. Performing timing analysis without recompiling your design does change programming files. must recompile your design update programming files.
10-24 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
Default Required fMAX setting does override clock settings. Only individual clock settings override clock settings.
Therefore, enter different project clock settings corresponding settings accelerate timing analysis eliminating full compilation cycle.
more information about using Stratix Stratix PLLs, General-Purpose PLLs Stratix Stratix Devices chapter. Stratix Stratix element (IOE) architecture similar APEX architecture, with total registers latch each IOE. registers organized three sets: output registers drive single double-data rate (DDR) output path, input registers latch support single input path, output enable registers enhance clock-to-output enable timing SDRAM interfacing. synchronous reset signal available each three sets registers preset clear, neither. addition advanced architecture, Stratix Stratix features dedicated circuitry external interfacing, standards, differential on-chip termination, high-speed differential standard support.
Structure
External Interfacing
advanced Stratix Stratix architecture includes dedicated circuitry interface with external RAM. This circuitry provides enhanced support external high-speed memory devices such SDRAM FCRAM. SDRAM interface uses bidirectional signal, DQS, clock data, both transmitting receiving device. Stratix Stratix devices transmit signal with data signals minimize clock data skew. Stratix Stratix devices include groups programmable pins, bottom banks device. Each group consists that supports fixed number pins. number pins depends mode. When using external interfacing circuitry, drives dedicated clock network that feeds pins residing that bank. Stratix Stratix programmable delay chains that phase shift signal ensure data sampled appropriate point time. Therefore, Stratix Stratix devices make full IOEs, remove need build input data path logic array. make these assignments Quartus Assignment Organizer.
Altera Corporation July 2005
10-25 Stratix Device Handbook, Volume
Structure
more information external interfacing, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet Stratix Device Family Handbook, Volume
Standard Support
Stratix Stratix devices support standards that APEX APEX devices support, including high-speed differential standards such LVDS, LVPECL, PCML, HyperTransporttechnology, differential HSTL input output clocks, differential SSTL output clocks. Stratix Stratix devices also introduce support SSTL-18 Class Similar APEX devices, Stratix Stratix devices only support certain standards designated banks. addition, vref pins dedicated pins Stratix Stratix devices support input pins.
more information about standard support Stratix Stratix devices, Selectable Standards Stratix Stratix Devices chapter.
High-Speed Differential Standards
Stratix Stratix devices support high-speed differential interfaces speeds Mbps using high-speed PLLs that drive dedicated clock network SERDES. Each fast drive highspeed channels. Stratix Stratix devices enhanced PLLs M512 blocks provide Mbps performance SERDES bypass clock interfacing. There restriction number channels that clocked using this scenario. Stratix Stratix devices have different number differential channels than APEX devices. Tables 10-9 10-10 highlight number differential channels supported Stratix Stratix devices.
Table 10-9. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1S10
Count
Number Receiver Channels
Number Transmitter Channels
10-26 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
Table 10-9. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1S20
Count
Number Receiver Channels
Number Transmitter Channels
EP1S25
1,020
EP1S30
1,020
EP1S40
1,020
1,508
EP1S60
1,020
1,508
EP1S80
1,508
Note Table 10-9:
information channel speeds, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Differential Interfaces chapter Stratix Device Handbook, Volume
Altera Corporation July 2005
10-27 Stratix Device Handbook, Volume
Structure
Table 10-10. Number Dedicated DIfferential Channels Stratix Devices Note Device
EP1SGX10 EP1SGX10 EP1SGX25 EP1SGX25 EP1SGX25 EP1SGX40 EP1SGX40 Note Table 10-10:
information channel speeds, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Source-Synchronous Differential Interfaces Stratix Devices chapter Stratix Device Handbook, Volume
Count
672/1,020 1,020 1,020 1,020
Number Transceivers
Number SourceSynchronous Channels
differential within Stratix also provides dynamic phase alignment (DPA). enables differential operate Gbps channel. automatically continuously tracks fluctuations caused system variations self-adjusts eliminate phase skew between multiplied clock serial data. block contains dynamic phase selector phase detection selection, SERDES, synchronizer, data realigner circuit. bypass dynamic phase aligner without affecting basic source-synchronous operation channel using separate deserializer. compile APEX LVDS design that uses clock-data synchronization (CDS) Stratix Stratix device, Quartus software issues warning during compilation that Stratix Stratix devices support CDS. Stratix Stratix devices offer flexible solution using byte realignment circuitry correct byte misalignment shifting, slipping, data bits. Stratix Stratix devices activate byte realignment circuitry when external (rx_data_align) internal custom-made state machine asserts SYNC node high. APEX APEX 20KE, APEX 20KCdevices have dedicated transmitter clock output (LVDSTXOUTCLK). Stratix Stratix devices, transmitter dataout channel with LVDS clock (fast clock) generates transmitter clock output. Therefore, drive
10-28 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
channel output clock pin, just dedicated clock output pins. This solution offers better versatility address various applications that require more complex clocking schemes.
more information differential support, data realignment, transmitter clock output Stratix Stratix devices, High-Speed Differential Interfaces Stratix Devices chapter.
altlvds Megafunction
take full advantage high-speed differential standards available Stratix Stratix devices, should update each instance altlvds megafunction APEX APEX 20KE, APEX 20KC designs. MegaWizard Plug-In Manager, choose altlvds megafunction, select Stratix Stratix target device family, update megafunction, recompile your design. altlvds megafunction supports Stratix Stratix parameters that available APEX APEX 20KE, APEX 20KC devices. Tables 10-11 10-12 describe parameters LVDS receiver LVDS transmitter, respectively.
Table 10-11. altlvds Parameters Stratix LVDS Receiver Note Parameter
input_data_rate inclock_data_alignment rx_data_align
Function
Specifies data rate Mbps. This parameter replaces multiplication factor Indicates alignment rx_inclk rx_in data. Drives data alignment port fast enables byte realignment circuitry.
registered_data_align_input Registers rx_data_align input port clocked rx_outclock. common_rx_tx_pll
Indicates fast shared between receiver transmitter applications.
Table 10-12. altlvds Parameters Stratix LVDS Transmitter (Part Note Parameter
output_data_rate inclock_data_alignment outclock_alignment
Function
Specifies data rate Mbps. This parameter replaces multiplication factor Indicates alignment tx_inclk tx_in data. Specifies alignment tx_outclock tx_out data.
Altera Corporation July 2005
10-29 Stratix Device Handbook, Volume
Configuration
Table 10-12. altlvds Parameters Stratix LVDS Transmitter (Part Note Parameter
registered_input
Function
Specifies clock source input synchronization registers, which either tx_inclock tx_coreclock. Used only when Registered Inputs option selected. Indicates fast shared between receiver transmitter applications.
common_rx_tx_pll
Notes Tables 10-11 10-12:
specify these parameters MegaWizard Plug-In Manager. must specify data rate MegaWizard Plug-In Manager instead factor. same fast used clock both receiver transmitter only both running same frequency.
Above standard offered APEX APEX 20K, Stratix devices, Stratix devices provide 3.175 Gbps transceivers. transceivers provide high-speed serial links chip-to-chip, backplane, line-side connectivity support number emerging high-speed protocols. find more information Stratix Family Data Sheet Stratix Family Handbook, Volume
Configuration
Stratix Stratix devices supports current configuration schemes, including enhanced configuration devices, passive serial (PS), passive parallel asynchronous (PPA), fast passive parallel (FPP), JTAG. Stratix Stratix devices also provide number configuration enhancements that take advantage when migrating APEX APEX designs Stratix Stratix devices.
Configuration Speed Schemes
configure Stratix Stratix devices maximum clock speed MHz, which faster than 66-MHz 33-MHz maximum configuration speeds APEX APEX devices, respectively. Similar APEX devices, 8-bit parallel data configure Stratix Stratix devices (the target device receive byte-wide configuration data each clock cycle) significantly speeding configuration times. select configuration scheme based MSEL pins driven. Stratix Stratix devices have three MSEL pins (APEX APEX devices have MSEL pins) determining configuration scheme.
10-30 Stratix Device Handbook, Volume
Altera Corporation July 2005
Transitioning APEX Designs Stratix Stratix Devices
more information about Stratix Stratix configuration schemes, Configuring Stratix Stratix Devices chapter.
Remote Update Configuration
APEX device family introduced concept remote update configuration, where could send APEX device configuration files from remote source device would store files flash memory reconfigure itself with configuration data. Stratix Stratix devices enhance support remote update configuration with new, dedicated circuitry handle recover from errors. error occurs either during device configuration user mode, this circuitry reconfigures Stratix Stratix device known state. Additionally, Stratix Stratix devices have user watchdog timer ensure application configuration data executes successfully during user mode. User logic must continually reset this watchdog timer order validate that application configuration data functioning properly.
more information about remote local update modes, Remote System Configuration with Stratix Stratix Devices chapter.
JTAG Instruction Support
Stratix Stratix devices support JTAG instructions, PULSE_NCONFIG CONFIG_IO. PULSE_NCONFIG instruction emulates pulsing nCONFIG signal trigger reconfiguration, while actual nCONFIG device unaffected. CONFIG_IO instruction allows JTAG chain configure standards pins. Because this instruction interrupts device configuration, should reconfigure Stratix Stratix device after finish JTAG testing ensure proper device operation. Table 10-13 compares JTAG instruction support Stratix Stratix devices versus APEX APEX devices. further information about supported JTAG instructions, appropriate device family data sheet.
Table 10-13. JTAG Instruction Support (Part JTAG Instruction
SAMPLE/PRELOAD EXTEST BYPASS USERCODE
Stratix
APEX
APEX
Altera Corporation July 2005
10-31 Stratix Device Handbook, Volume
Conclusion
Table 10-13. JTAG Instruction Support (Part JTAG Instruction
IDCODE Instructions SignalTapII Instructions HIGHZ CLAMP PULSE_NCONFIG CONFIG_IO
Stratix
APEX
APEX
Conclusion
Stratix Stratix devices extend advanced features available APEX APEX device families deliver complete system-on-a-programmable-chip (SOPC) solution. following these guidelines, easily transition current APEX APEX designs take advantage features available Stratix Stratix devices.
10-32 Stratix Device Handbook, Volume
Altera Corporation July 2005
Other recent searches
QV400D - QV400D QV400D Datasheet
QS32X384 - QS32X384 QS32X384 Datasheet
QS32X2384 - QS32X2384 QS32X2384 Datasheet
MC100E155 - MC100E155 MC100E155 Datasheet
LV-550T2S1-LDE - LV-550T2S1-LDE LV-550T2S1-LDE Datasheet
LM4911 - LM4911 LM4911 Datasheet
ISO422 - ISO422 ISO422 Datasheet
GVT7364A16 - GVT7364A16 GVT7364A16 Datasheet
FMA04A - FMA04A FMA04A Datasheet
CY7C1470BV25 - CY7C1470BV25 CY7C1470BV25 Datasheet
CY7C1472BV25 - CY7C1472BV25 CY7C1472BV25 Datasheet
CY7C1474BV25 - CY7C1474BV25 CY7C1474BV25 Datasheet
AN-917 - AN-917 AN-917 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
