LV8071LP Bi-CMOS Piezoelectric Actuator Driver LV8071LP
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Ordering number ENA0991
LV8071LP
Bi-CMOS
Piezoelectric Actuator Driver
LV8071LP piezoelectric autofocus actuator driver cell phone cameras. internally generates drive waveforms, which reduces load makes possible control piezoelectric actuators simple control signals.
Features
actuator using piezoelectric device driven external input simple control signal. 39MHz (CLK1 input) input divided into quarters internally generate 9.75MHz input. operation time generated using this base ensure output appropriate piezoelectric drive. CLK2 input 9.75MHz input used, base either. start/stop controlled input. Initialization made according built-in sequence startup. actuator drive time determined inputting pulse DRIVE pin. recognize operation/stop actuator, BUSY signal output while performs output.
Specifications
Maximum Ratings 25°C,
Parameter Supply voltage Output current Input signal voltage Allowable loss Operating temperature range Storage temperature Symbol Topr Tstg Mounted specified board* Conditions Ratings -0.5 -0.5 VCC+0.5 +150 Unit
Note Mounted specified board: glass epoxy board
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
D1907 20060124-S00004 No.A0991-1/6
LV8071LP
Allowable Operating Condtions
Parameter Supply voltage Input signal voltage Input CLK1 frequency Input CLK2 frequency DRIVE minimum pulse width DRIVE minimum pulse width Maximum operation cycle frequency Symbol FCLK1 FCLK2 CLK1 CLK2 1clk=1/4CLK1=CLK2 1clk=1/4CLK1=CLK2 cycle 87clk Conditions Ratings 9.75 cycles Unit times
Electrical Characteristics 25°C, 2.8V, GND=0V, unless otherwise specified.
Parameter Current drain standby Current drain during operation level input voltage level input voltage Output block upper-side resistance Output block lower-side resistance Turn-ON time Turn-OFF time Symbol ICC0 ICC1 RonP RonN TPLH TPHL load load Conditions input CLK1=39MHz 2.5V 5.5V 2.5V 5.5V Ratings Unit
Note: time 1090% rise 9010% fall specified.
Package Dimensions
unit (typ) 3318
VIEW SIDE VIEW BOTTOM VIEW (0.125)
(0.13)
(C0.116)
LASER MARKED INDEX (0.55)
SIDE VIEW
(0.035)
0.25
SANYO VCT16(2.6X2.6)
No.A0991-2/6
LV8071LP
Assignment
DRIVE (NC)
Mounted specified board: glass epoxy 4-layer substrate (2S2P)
Allowable Power Dissipation,
OUT1
TEST1
(NC)
LV8071LP
TEST2
0.36
CLK1
CLK2 BUSY OUT2
(NC)
ILV00256
Ambient Temperature,
view
Block Diagram
CLK1 CLK2 DRIVE
Quarterdividing circuit
OUT1
select Actuator drive waveform generated
GATE GATE busy
OUT2
BUSY
TEST1
TEST2
Resistance provided LV8071LP, insertion resistor between pins enables suppression inrush current piezoelectric element. Since resistance value exerts influence actuator operation, determine constant within range while checking operation.
No.A0991-3/6
LV8071LP
Description Operation
CLK1 CLK2 inputs CLK1 incorporates quarter-dividing circuit. input 39MHz directly, input directly CLK1 pin. When dividing circuit provided externally, input 9.75MHz CLK2 pin. Short-circuit unused GND. cycle: cycle (8.923s CLK1=39MHz CLK2=9.75MHz) waveform operation used unit output operation. drive waveform appropriate piezoelectric drive shown below generated (1clk=1/4CLK1=1CLK2)
87clk cycle 23clk
4clk
34clk
input: input causes functions stop suppress current drain standby state. input causes start. After initialization according start sequence, DRIVE ready accept input. Initialization: Internal sequence move actuator initial position start After operation cycles times direction, standby time cycles times secured. Then, cycles times return operation made macro direction. DRIVE input: Operation time setting pin. performs cycles operation pulse pulse input. prevent noise-induced error, input with pulse width 96clk (9.85s when 39MHz) respectively accepted. input: Actuator operation direction setting pin. Actuator macro direction input direction input actuator stops operation changed over even when operating with DRIVE pulse. TEST1/2 Setting inspection. Short-circuit this with during actual use. BUSY output: signal output pin, which outputs "H=VCC voltage while actuator operating when actuator stopped.
No.A0991-4/6
LV8071LP
Timing Chart (For CLK1=39MHz)
direction logic select DRIVE 8.923s GATE GATE Operating direction Operation start DRIVE input cycles 5.00ms BUSY Returns with "EN=L" even during operation Operating macro direction Operation pulses cycles Operation stop with input Macro direction logic select
BUSY output only during operation
Enlarged view gate signal sequence
Operating direction
8.923s 2.359s 2.359s
GATE 410ns GATE 3.487s 3.487s
Operating macro direction 410ns GATE 3.487s GATE 2.359s
8.923s
3.487s
2.359s
Initialization sequence startup
Start with EN=H. Initialization sequence starts. 8.923s GATE GATE Operating direction cycles 212.3ms Standby state cycles 5.00ms Initialization about 220ms Operating macro direction cycles 2.50ms
BUSY during initialization even standby state BUSY output initialization BUSY output during initialization
No.A0991-5/6
LV8071LP
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellectual property rights which resulted from technical information products mentioned above.
This catalog provides information December, 2007. Specifications information herein subject change without notice.
No.A0991-6/6
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