LC87F2H08A CMOS 8K-byte FROM 256-byte integrated 8-bit 1-chi

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LC87F2H08A CMOS 8K-byte FROM 256-byte integrated 8-bit 1-chi

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Ordering number ENA0970
LC87F2H08A
CMOS 8K-byte FROM 256-byte integrated
8-bit 1-chip Microcontroller
SANYO LC87F2H08A 8-bit microcomputer that, centered around running minimum cycle time 83.3ns, integrates single chip number hardware features such 8K-byte flash (On-boardprogrammable), 256-byte RAM, On-chip-debugger, sophisticated 16-bit timers/counters (may divided into 8-bit timers), 16-bit timer/counter (may divided into 8-bit timers/counters 8-bit PWMs), 8-bit timers with prescaler, base timer serving time-of-day clock, high-speed clock counter, synchronous interface, asynchronous/synchronous interface, UART interface (full duplex), 12-bit channels, 12/8-bit 9-channel converter, system clock frequency divider, internal reset 20-source 10-vector interrupt feature.
Features
Flash Capable on-board programming with wide range (2.2 5.5V) voltage source. Block-erasable byte units Writable 2-byte units 8192 bits bits Minimum Cycle 83.3ns (12MHz VDD=2.7V 5.5V) 100ns (10MHz VDD=2.2V 5.5V) 250ns 4MHz VDD=1.8V 5.5V) Note: cycle time here refers read speed.
This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
Ver.0.50
N2807HKIM 20070911-S00007 No.A0970-1/25
LC87F2H08A
Minimum Instruction Cycle Time 250ns (12MHz VDD=2.7V 5.5V) 300ns (10MHz VDD=2.2V 5.5V) 750ns (4MHz VDD=1.8V 5.5V) Ports Normal withstand voltage ports Ports whose direction designated 1-bit units (Pin, P20, P21, P30, P31,P70 P73) Ports whose direction designated 4-bit units (P0n) Dedicated oscillator ports/input ports (CF1/XT1, CF2/XT2) Reset (RES) Power pins (VSS1, VSS2, VDD1) Timers Timer 16-bit timer/counter with capture register. Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture register) channels Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture register) 8-bit counter (with 8-bit capture register) Mode 16-bit timer with 8-bit programmable prescaler (with 16-bit capture register) Mode 16-bit counter (with 16-bit capture register) Timer 16-bit timer/counter that supports PWM/toggle outputs Mode 8-bit timer with 8-bit prescaler (with toggle outputs) 8-bit timer/ counter with 8-bit prescaler (with toggle outputs) Mode 8-bit with 8-bit prescaler channels Mode 16-bit timer/counter with 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order bits) Mode 16-bit timer with 8-bit prescaler (with toggle outputs) (The lower-order bits used PWM) Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Base timer clock selectable from subclock (32.768kHz crystal oscillation), system clock, timer prescaler output. Interrupts programmable different time schemes High-Speed Clock Counter count clocks with maximum clock rate 20MHz main clock 10MHz). generate output real time. SIO0: 8-bit Synchronous serial interface first/MSB first mode selectable Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC) SIO1: 8-bit asynchronous/synchronous serial interface Mode Synchronous 8-bit serial 3-wire configuration, tCYC transfer clocks) Mode Asynchronous serial (half-duplex, data bits, stop bit, 2048 tCYC baudrates) Mode mode (start bit, data bits, tCYC transfer clocks) Mode mode (start detect, data bits, stop detect) UART Full Duplex 7/8/9 data bits selectable Stop bits continuous data transmission) Built-in baudrate generator Converter: bits/8 bits channels 12/8 bits converter resolution selectable
No.A0970-2/25
LC87F2H08A
PWM: Multifrequency 12-bit channels Remote Control Receiver Circuit (sharing pins with P73, INT3, T0IN) Noise rejection function (noise filter time constant selectable from tCYC/32 tCYC/128 tCYC) Clock Output Function generate clock outputs with frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 source clock selected system clock. generate source clock subclock Watchdog Timer External watchdog timer Interrupt reset signals selectable Interrupts sources, vector addresses Provides three levels (low (L), high (H), highest (X)) multiplex interrupt control. interrupt requests level equal lower than current interrupt accepted. When interrupt requests more vector addresses occur same time, interrupt highest level takes precedence over other interrupts. interrupts same level, interrupt into smallest vector address takes precedence.
Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level INT0 INT1 INT2/T0L/INT4 INT3/INT5/base timer T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit ADC/T6/T7/PWM4, PWM5 Port Interrupt Source
Priority levels interrupts same level, with smallest vector address takes precedence. Subroutine Stack Levels: 128levels (The stack allocated RAM.) High-speed Multiplication/Division Instructions bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) Oscillation Circuits Internal oscillation circuits Low-speed oscillation circuit system clock (100kHz) Medium-speed oscillation circuit system clock (1MHz) Multifrequency oscillation circuit system clock (8MHz) External oscillation circuits Hi-speed oscillation circuit: system clock, with internal speed crystal oscillation circuit: low-speed system clock, with internal crystal oscillation circuits share same pins. active circuit selected under program control. Both crystal oscillator circuits stop operation system reset. When reset released, only oscillation circuit resumes operation.
No.A0970-3/25
LC87F2H08A
System Clock Divider Function current. minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s main clock rate 10MHz). Internal reset function Power-on reset (POR) function reset generated only power-on time. release level selected from levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, 4.35V) through option configuration. Low-voltage detection reset (LVD) function functions combined generate resets when power turned when power voltage falls below certain level. use/disuse function voltage threshold level levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V). Standby Function HALT mode: Halts instruction execution while allowing peripheral circuits continue operation. Oscillation halted automatically. Canceled system reset occurrence interrupt. HOLD mode: Suspends instruction execution operation peripheral circuits. crystal oscillators automatically stop operation. There three ways resetting HOLD mode. Setting reset lower level. Setting least INT0, INT1, INT2, INT4, INT5 pins specified level Having interrupt source established port X'tal HOLD mode: Suspends instruction execution operation peripheral circuits except base timer. oscillator automatically stop operation. state crystal oscillation established when X'tal HOLD mode entered retained. There four ways resetting X'tal HOLD mode. Setting reset level Setting least INT0, INT1, INT2, INT4, INT5 pins specified level Having interrupt source established port Having interrupt source established base timer circuit Note: Available only when X'tal oscillation selected. Onchip Debugger Supports software debugging with mounted target board. channels on-chip debugger pins available compatible with small count devices. DBGP0 (P0), DBGP1 (P1) Data Security Function (flash versions only) Protects program data stored flash memory from unauthorized read copy. Note: This data security function does necessarily provide absolute data security. Package Form Lead-free type Development Tools On-chip debugger: TCB87 type LC87F2H08A Programming Boards
Package Programming boards W87F24Q
No.A0970-4/25
LC87F2H08A
Flash Programmer
Maker Single Flash Support Group, Inc. Gang Model AF9708/AF9709/AF9709B (including product Ando Electric Co.,Ltd) AF9723 (Main body) (including product Ando Electric Co.,Ltd) AF9833 (Unit) (including product Ando Electric Co.,Ltd) SKK/SKK TypeB SANYO /SKK-DBG TypeB (SANYO FWS) Supported version (Note) Revision After 02.72 Application Version After 1.04 Chip Data Version After 2.10 LC87F2H08A Device LC87F2H08A
Package Dimensions
unit (typ) 3162C
0.65 (0.9)
1.7max
0.15
(1.5)
SANYO QFP36(7X7)
No.A0970-5/25
LC87F2H08A
Assignment
P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 N.C. P31/PWM5/INT5/T1IN P30/PWM4/INT5/T1IN P21/URX/INT4/T1IN P04/AN4 P05/AN5/CKO/DBGP00 P06/AN6/T6O/DBGP01 P07/T7O/DBGP02 N.C. N.C. P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
LC87F2H08A
P20/UTX/INT4/T1IN P17/T1PWMH/BUZ P16/T1PWML N.C. N.C. P15/SCK1/DGBP10 P14/SI1/SB1/DBGP11 P13/SO1/DBGP12 P12/SCK0
P73/INT3/T0IN I.C. VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO0 P11/SI0/SB0
view
SANYO: "Lead-free Type"
QFP36 NAME P73/INT3/T0IN I.C. VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1/DBGP12 P14/SI1/SB1/DBGP11 P15/SCK1/DBGP10 N.C. N.C. P16/T1PWML P17/T1PWMH/BUZ P20/UTX/INT4/T1IN QFP36 NAME P21/URX/INT4/T1IN P30/PWM4/INT5/T1IN P31/PWM5/INT5/T1IN N.C. VSS2 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5/CKO/DBGP00 P06/AN6/T6O/DBGP01 P07/T7O/DBGP02 N.C. N.C. P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
Note I.C. N.C. pins must held open (disconnected).
No.A0970-6/25
LC87F2H08A
System Block Diagram
Interrupt control
Standby control
Flash
X'tal Reset control Clock generator
Reset circuit (LVD/POR)
register
register
SIO0
interface
SIO1
Port
Timer
Port
Timer
Port
Timer
Port
Timer
Port
Stack pointer
Base timer
On-chip debugger
PWM4
INT0 INT3 (Noise filter)
PWM5
Port INT4
UART1
Port INT5
No.A0970-7/25
LC87F2H08A
Description
Name VSS1,VSS2 VDD1 Port power supply pins power supply 8-bit port specifiable 4-bit units Pull-up resistors turned 4-bit units. HOLD reset input Port interrupt input functions P05: System clock output P06: Timer toggle output P07: Timer toggle output P00(AN0) P06(AN6):AD converter input P05(DBGP00) P07(DBGP02):On-chip debugger port Port 8-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P10: SIO0 data output P11: SIO0 data input/bus P12: SIO0 clock P13: SIO1 data output Port 2-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P20: UART transmit P21: UART receive P21: INT4 input/HOLD reset input/timer event input/timer capture input/ timer capture input Interrupt acknowledge types Rising INT4 2-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P30: PWM4 output P31: PWM5 output P31: INT5 input/HOLD reset input/timer event input/timer capture input/ timer capture input Interrupt acknowledge types Rising INT5 enable Falling enable Rising Falling enable level disable level disable enable Falling enable Rising Falling enable level disable level disable P14: SIO1 data input/bus P15: SIO1 clock P16: Timer PWML output P17: Timer PWMH output/beeper output Description Option
P15(DBGP10) P13(DBGP12):On-chip debugger port
Port
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No.A0970-8/25
LC87F2H08A
Continued from preceding page.
Name Port 4-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P70: INT0 input/HOLD reset input/timer capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer capture input P72: INT2 input/HOLD reset input/timer event input/timer capture input P73: INT3 input (input with noise filter)/timer event input/timer capture input P70(AN8),P71(AN9) converter input Interrupt acknowledge types Rising INT0 INT1 INT2 INT3 CF1/XT1 enable enable enable enable Falling enable enable enable enable Rising Falling disable disable enable enable level enable enable disable disable level enable enable disable disable Description Option
External reset Input/internal reset output Ceramic resonator 32.768kHz crystal oscillator input function General-purpose input port Must configured general-purpose port connected VSS1 used. Ceramic resonator 32.768kHz crystal oscillator output function General-purpose input port Must configured general-purpose port connected VSS1 used.
CF2/XT2
Port Output Types
table below lists types port outputs presence/absence pull-up resistor. Data read into input port even output mode.
Port Name Option selected units Option type CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Output type Pull-up resistor Programmable (Note Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable
Note control presence absence programmable pull-up resistors port switching between low-and high-impedance pull-up connection exercised nibble (4-bit) units (P00 07). Note sure electrically short-circuit between VSS1 VSS2 pins.
On-chip Debugger connection requirements
treatment on-chip debugger pins, refer separately available documents entitled "RD87 On-chip Debugger Installation Manual" "LC872000 Series On-chip debugger connection requirements"
No.A0970-9/25
LC87F2H08A
Absolute Maximum Ratings 25°C, VSS1 VSS2
Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current High level output current IOPH(2) Mean output current (Note 1-1) Total output current IOMH(2) IOAH(1) IOAH(2) IOAH(3) IOAH(4) Peak output current IOPL(2) level output current IOPL(3) Mean output current (Note 1-1) IOML(2) IOML(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) Power Dissipation max(2) max(1) IOML(1) IOPL(1) Ports Ports Ports P00, Port Ports P00, Port Port Port Ports Ports applicable applicable Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Ta=-40 +85°C Package only Ta=-40 +85°C Package with thermal resistance board (Note 1-2) Operating ambient Temperature Storage ambient temperature Tstg Topr +125 applicable applicable applicable Total applicable pins applicable IOMH(1) Ports IOPH(1) CF1, Ports Port Ports CMOS output select applicable applicable CMOS output select applicable applicable Total applicable pins Total applicable pins Total applicable pins Symbol Pin/Remarks VDD1 Conditions VDD[V] -0.3 -0.3 -0.3 -7.5 Specification +6.5 VDD+0.3 VDD+0.3 unit
Note 1-1: mean output current mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: glass epoxy) used.
No.A0970-10/25
LC87F2H08A
Allowable Operating Conditions -40°C +85°C, VSS1 VSS2
Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports port input/ interrupt side VIH(2) VIH(3) VIH(4) level input voltage VIL(1) Ports Port watchdog timer side CF1, Ports port input/ interrupt side VIL(2) Ports VIL(3) VIL(4) Instruction cycle time (Note 2-1) External system clock frequency FEXCF open System clock frequency division ratio=1/1 External system clock duty=50±5% open System clock frequency division ratio=1/2 External system clock duty=50±5% Oscillation frequency range (Note 2-3) FmCF(3) CF1, FmCF(2) CF1, FmCF(1) CF1, 12MHz ceramic oscillation Fig. 10MHz ceramic oscillation Fig. 4MHz ceramic oscillation. oscillation normal amplifier size selected. Fig. (CFLAMP=0) 4MHz ceramic oscillation. oscillation amplifier size selected. (CFLAMP=1) Fig. FmMRC Frequency variable oscillation. frequency division ration.(RCCTD=0) (Note 2-4) FmRC FmSRC FsX'tal XT1, Internal Medium-speed oscillation Internal Low-speed oscillation 32.768kHz crystal oscillation Fig. 32.768 7.44 8.56 24.4 tCYC (Note 2-2) Port watchdog timer side CF1, 0.245 0.294 0.735 0.15VDD+0.4 0.2VDD 0.8VDD-1.0 0.25VDD 0.2VDD 0.3VDD+0.7 0.9VDD 0.75VDD 0.1VDD+0.4 0.3VDD+0.7 Symbol VDD(1) VDD(2) VDD(3) VDD1 Pin/Remarks VDD1 Conditions VDD[V] 0.245s tCYC 200s 0.294s tCYC 200s 0.735s tCYC 200s register contents sustained HOLD mode. Specification unit
Note 2-1: must held greater than equal 2.2V flash onboard programming mode. Note 2-2: Relationship between tCYC oscillation frequency 3/FmCF division ratio 6/FmCF division ratio 1/2. Note 2-3: Tables oscillation constants. Note 2-4: When switching system clock, allow oscillation stabilization time 100s longer after multifrequency oscillator circuit transmits from "oscillation stopped" "oscillation enabled" state.
No.A0970-11/25
LC87F2H08A
Electrical Characteristics -40°C +85°C, VSS1 VSS2
Parameter High level input current Symbol IIH(1) Pin/Remarks Ports Port Conditions VDD[V] Output disabled Pull-up resistor VIN=VDD (Including output Tr's leakage current) IIH(2) level input current IIL(1) Ports Port VIN=VDD Output disabled Pull-up resistor VIN=VSS (Including output Tr's leakage current) IIL(2) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Rpu(3) Ports Port Port P00, Port Ports Port Ports VIN=VSS IOH=-1mA IOH=-0.35mA IOH=-0.15mA IOH=-6mA IOH=-1.4mA IOH=-0.8mA IOL=10mA IOL=1.4mA IOL=0.8mA IOL=1.4mA IOL=0.8mA IOL=25mA IOL=4mA IOL=2mA VOH=0.9VDD When Port selected low-impedance pull-up. VOH=0.9VDD When Port selected High-impedance pull-up. Hysteresis voltage VHYS(1) VHYS(2) capacitance Ports pins pins other than that under test: VIN=VSS f=1MHz Ta=25°C 0.1VDD 0.07VDD VDD-1 VDD-0.4 VDD-0.4 VDD-1 VDD-0.4 VDD-0.4 Specification unit
No.A0970-12/25
LC87F2H08A
Serial Characteristics -40°C +85°C, VSS1 VSS2
SIO0 Serial Characteristics (Note 4-1-1)
Parameter Frequency Input clock level pulse width High level pulse width Output clock Frequency level pulse width High level pulse width Serial input Data setup time tsDI(1) SB0(P11), SI0(P11) Data hold time Output delay Input clock time tdD0(2) tdD0(3) thDI(1) tdD0(1) SO0(P10), SB0(P11) Must specified with respect rising edge SIOCLK. Fig. Continuous data transmission/reception mode (Note 4-1-2) Synchronous 8-bit mode (Note 4-1-2) Output clock (Note 4-1-2) 0.05 (1/3)tCYC +0.08 1tCYC +0.08 0.05 tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) CMOS output selected Fig. tSCK tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/Remar SCK0(P12) Conditions VDD[V] Fig. tCYC Specification unit
Serial output
Serial clock
(1/3)tCYC +0.08
Note 4-1-1: These specifications theoretical values. margin depending use. Note 4-1-2: Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. SIO1 Serial Characteristics (Note 4-2-1)
Parameter Frequency Input clock level pulse width High level pulse width Frequency Output clock level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) Must specified with respect rising edge SIOCLK. Fig. 0.05 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.08 0.05 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) CMOS output selected Fig. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) Fig. Conditions VDD[V] tCYC tSCK Specification unit
Note 4-2-1: These specifications theoretical values. margin depending use.
No.A0970-13/25
Serial clock
LC87F2H08A
Pulse Input Conditions -40°C +85°C, VSS1 VSS2
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 P21), INT5(P30 P31) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant INT3(P73) when noise filter time constant 1/32 INT3(P73) when noise filter time constant 1/128 Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer nabled. Interrupt source flag set. Event inputs timer enabled. Resetting enabled. tCYC Conditions VDD[V] Interrupt source flag set. Event inputs timer enabled. Specification unit
No.A0970-14/25
LC87F2H08A
Converter Characteristics VSS1 VSS2 <12bits Converter Mode/Ta=-40 +85°C>
Parameter Resolution Absolute accuracy Symbol Pin/Remarks AN0(P00) AN6(P06), AN8(P70), AN9(P71) Conversion time TCAD (Note 6-1) (Note 6-1) Ta=-10 +50°C Conversion time calculation formulas. (Note 6-2) Conversion time calculation formulas. (Note 6-2) Ta=-10 +50°C Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN Conditions VDD[V] Specification unit
<8bits Converter Mode/Ta=-40 +85°C
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol Pin/Remarks AN0(P00) AN6(P06) AN8(P70) AN9(P71) Conversion time calculation formulas. (Note 6-2) Conversion time calculation formulas. (Note 6-2) Ta=-10 +50°C Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (Note 6-1) Conditions VDD[V] Specification ±1.5 unit
Conversion time calculation formulas: 12bits Converter Mode TCAD(Conversion time) ((52/(AD division 8bits Converter Mode TCAD(Conversion time) ((32/(AD division
External oscillation (FmCF) CF-12MHz Operating supply voltage range (VDD) 4.0V 5.5V 3.0V 5.5V CF-10MHz 4.0V 5.5V 3.0V 5.5V CF-4MHz 3.0V 5.5V 2.4V 3.6V System division ratio (SYSDIV) Cycle time (tCYC) 250ns 250ns 300ns 300ns 750ns 750ns division ratio (ADDIV) 1/16 1/16 1/32 12bit 34.8s 69.5s 41.8s 83.4s 104.5s 416.5s conversion time (TCAD) 8bit 21.5s 42.8s 25.8s 51.4s 64.5s 256.5s
Note 6-1: quantization error (±1/2LSB) must excluded from absolute accuracy. absolute accuracy must measured microcontroller's state which operations occur pins adjacent analog input channel. Note 6-2: conversion time refers period from time instruction starting conversion process till time conversion results register(s) loaded with complete digital conversion value corresponding analog input value. conversion time times normal-time conversion time when: first conversion performed 12-bit conversion mode after system reset. first conversion performed after conversion mode switched from 8-bit 12-bit conversion mode.
No.A0970-15/25
LC87F2H08A
Power-on Reset (POR) Characteristics Ta=-40 +85°C, VSS1=VSS2=0V
Specification Parameter release voltage Symbol PORRL Pin/Remarks Conditions Select from option. (Note 7-1) Option selected voltage 1.67V 1.97V 2.07V 2.37V 2.57V 2.87V 3.86V 4.35V Detection voltage unknown state Power supply rise time PORIS Power supply rise time from 1.6V. POUKS Fig. (Note 7-2) 0.95 1.55 1.85 1.95 2.25 2.45 2.75 3.73 4.21 1.67 1.97 2.07 2.37 2.57 2.87 3.86 4.35 1.79 2.09 2.19 2.49 2.69 2.99 3.99 4.49 unit
Note7-1: release level selected levels only when reset function disabled. Note7-2: unknown state before transistors start operation.
voltage detection reset (LVD) Characteristics Ta=-40 +85°C, VSS1=0V
Specification Parameter reset Voltage (Note 8-2) Symbol LVDET Pin/Remarks Conditions Select from option. (Note 8-1) (Note 8-3) Fig. Option selected voltage 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V hysteresys width LVHYS 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V Detection voltage unknown state voltage detection minimum Width (Reply sensitivity) TLVDW LVUKS Fig. (Note 8-4) LVDET-0.5V Fig. 0.95 1.81 1.91 2.21 2.41 2.71 3.69 4.18 1.91 2.01 2.31 2.51 2.81 3.79 4.28 2.01 2.11 2.41 2.61 2.91 3.89 4.38 unit
Note8-1: reset level selected levels only when reset function enabled. Note8-2: reset voltage specification values include hysteresis voltage. Note8-3: reset voltage exceed specification values when port output state changes and/or when large current flows through port. Note8-4: unknown state before transistors start operation.
No.A0970-16/25
LC87F2H08A
Consumption Current Characteristics -40°C +85°C, VSS1 VSS2
Parameter Normal mode consumption current (Note 9-1) Symbol IDDOP(1) Pin/ Remarks VDD1 Conditions VDD[V] FmCF=12MHz ceramic oscillation mode System clock 12MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(2) CF1=24MHz external clock System clock side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(3) FmCF=10MHz ceramic oscillation mode System clock 10MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(4) FmCF=4MHz ceramic oscillation mode System clock 4MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(5) oscillation amplifier size selected. (CFLAMP=1) FmCF=4MHz ceramic oscillation mode System clock 4MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(6) FsX'tal=32.768kHz crystal oscillation mode Internal speed oscillation stopped. System clock internal medium speed oscillation. Frequency variable oscillation stopped. frequency division ratio IDDOP(7) FsX'tal=32.768kHz crystal oscillation mode Internal speed medium speed oscillation stopped. System clock 8MHz with frequency variable oscillation frequency division ratio IDDOP(8) External FsX'tal FmCF oscillation stopped. System clock internal speed oscillation. Internal medium speed oscillation sopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(9) External FsX'tal FmCF oscillation stopped. System clock internal speed oscillation. Internal medium speed oscillation sopped. Frequency variable oscillation stopped. frequency division ratio Ta=-10 +50°C 11.9 16.2 13.0 Specification unit
Note9-1: Values consumption current include current that flows into output transistors internal pull-up resistors.
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No.A0970-17/25
LC87F2H08A
Continued from preceding page.
Parameter Normal mode consumption current (Note 9-1) Symbol IDDOP(10) Pin/ Remarks VDD1 Conditions VDD[V] FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(11) FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio Ta=-10 +50°C HALT mode consumption current (Note 9-1) IDDHALT(1) VDD1 HALT mode FmCF=12MHz ceramic oscillation mode System clock 12MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(2) HALT mode CF1=24MHz external clock System clock side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(3) HALT mode FmCF=10MHz ceramic oscillation mode System clock 10MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(4) HALT mode FmCF=4MHz ceramic oscillation mode System clock 4MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(5) HALT mode oscillation amplifier size selected. (CFLAMP=1) FmCF=4MHz ceramic oscillation mode System clock 4MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(6) HALT mode FsX'tal=32.768kHz crystal oscillation mode Internal speed oscillation stopped. System clock internal medium speed oscillation Frequency variable oscillation stopped. frequency division ratio Specification unit
Note9-1: Values consumption current include current that flows into output transistors internal pull-up resistors.
Continued next page.
No.A0970-18/25
LC87F2H08A
Continued from preceding page.
Parameter HALT mode consumption current (Note 9-1) Symbol IDDHALT(7) Pin/ remarks VDD1 HALT mode FsX'tal=32.768kHz crystal oscillation mode Internal speed medium speed oscillation stopped. System clock 8MHz with Frequency variable oscillation frequency division ratio IDDHALT(8) HALT mode External FsX'tal FmCF oscillation stopped. System clock internal speed oscillation. Internal medium speed oscillation sopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(9) HALT mode External FsX'tal FmCF oscillation stopped. System clock internal speed oscillation. Internal medium speed oscillation sopped. Frequency variable oscillation stopped. frequency division ratio Ta=-10 +50°C IDDHALT(10) HALT mode FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(11) HALT mode FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio Ta=-10 +50°C HOLD mode consumption current (Note 9-1) IDDHOLD(2) IDDHOLD(1) VDD1 HOLD mode CF1=VDD open (External clock mode) HOLD mode CF1=VDD open (External clock mode) Ta=-10 +50°C IDDHOLD(3) HOLD mode CF1=VDD open (External clock mode) option selected IDDHOLD(4) HOLD mode CF1=VDD open (External clock mode) Ta=-10 +50°C option selected Timer HOLD mode consumption current (Note 9-1) IDDHOLD(6) IDDHOLD(5) VDD1 Timer HOLD mode FsX'tal=32.768 crystal oscillation mode Timer HOLD mode FsX'tal=32.768kHz crystal oscillation mode Ta=-10 +50°C 0.04 0.02 0.04 0.02 0.017 Conditions VDD[V] Specification unit
Note9-1: Values consumption current include current that flows into output transistors internal pull-up resistors. Note9-2: consumption current values include operational current function specified.
No.A0970-19/25
LC87F2H08A
F-ROM Programming Characteristics Ta=+10 +55°C, VSS1 VSS2
Parameter Onboard programming current Programming time tFW(1) tFW(2) Erasing time Programming time Symbol IDDFW(1) Pin/Remarks VDD1 Conditions VDD[V] Only current Flash block. Specification unit
UART (Full Duplex) Operating Conditions Ta=-40 +85°C, VSS1 VSS2
Parameter Transfer rate Symbol Pin/Remarks UTX(P20) URX(P21) Conditions VDD[V] 16/3 Specification 8192/3 unit tCYC
Data length: Stop bits Parity bits:
7/8/9 bits (LSB first) (2-bit continuous data transmission) None Example Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start Stop Transmit data (LSB first) transmission
Start transmission
Example Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start Start reception Receive data (LSB first)
Stop reception
Characteristics Sample Main System Clock Oscillation Circuit
Given below characteristics sample main system clock oscillation circuit that measured using SANYO-designated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Main System Clock Oscillator Circuit with Ceramic Oscillator oscillation normal amplifier size selected (CFLAMP=0)
Nominal Frequency Vendor Name Circuit Constant Oscillator Name [pF] 12MHz CSTCE12M0G52-R0 CSTCE12M0G52-B0 10MHz MURATA CSTCE10M0G52-R0 CSTCE10M0G52-B0 4MHz CSTCR4M00G53-R0 CSTCR4M00G53-B0 (10) (10) (10) (10) (15) (15) [pF] (10) (10) (10) (10) (15) (15) Open Open Open Open Open Open 1.5k 1.5k Operating Voltage Range Oscillation Stabilization Time [ms] [ms] Internal C1,C2 (SMD type) Remarks
No.A0970-20/25
LC87F2H08A
oscillation amplifier size selected (CFLAMP=1)
Nominal Frequency Vendor Name Circuit Constant Oscillator Name [pF] CSTCR4M00G53-R0 4MHz MURATA CSTCR4M00G53-B0 CSTCR4M00G53095-R0 CSTCR4M00G53095-B0 (15) (15) (15) (15) [pF] (15) (15) (15) (15) Open Open Open Open 1.0k 1.0k 1.0k 1.0k Operating Voltage Range Oscillation Stabilization Time [ms] [ms] Internal C1,C2 (SMD type) Remarks
oscillation stabilization time refers time interval that required oscillation stabilized after goes above operating voltage lower limit (see Figure
Characteristics Sample Subsystem Clock Oscillator Circuit
Given below characteristics sample subsystem clock oscillation circuit that measured using SANYOdesignated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Subsystem Clock Oscillator Circuit with Crystal Oscillator
Nominal Frequency Vendor Name EPSON TOYOCOM Circuit Constant Oscillator Name [pF] 32.768kHz MC-306 [pF] OPEN 330k Operating Voltage Range Oscillation Stabilization Time Applicable value=7.0pF Remarks
oscillation stabilization time refers time interval that required oscillation stabilized after instruction starting subclock oscillation circuit executed time interval that required oscillation stabilized after HOLD mode reset (see Figure Note: components that involved oscillation should placed close another possible because they vulnerable influences circuit pattern.
CF1/XT1
CF2/XT2
CF/X'tal
Figure Oscillator Circuit
0.5VDD
Figure Timing Measurement Point
No.A0970-21/25
LC87F2H08A
Power supply Reset time
Operating lower limit
Internal medium speed oscillation
tmsCF/tmsX'tal
CF1,
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal absent
HOLD reset signal valid
Internal medium speed oscillation speed oscillation tmsCF/tmsX'tal CF1, (Note)
HOLD
HALT
HOLD Reset Signal Oscillation Stabilization Time Note: External oscillation circuit selected. Figure Oscillation Stabilization Times
No.A0970-22/25
LC87F2H08A
RRES
CRES
Note: External circuits reset vary depending usage LVD. Please refer user's manual more information.
Figure Reset Circuit
SIOCLK:
DATAIN:
DATAOUT:
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH
Figure Serial Output Waveforms
tPIL
tPIH
Figure Pulse Input Timing Signal Waveform
No.A0970-23/25
LC87F2H08A
release voltage (PORRL)
Reset period Unknown-state (POUKS)
100s longer
Reset period
Figure Waveform observed when only used (LVD used) (RESET pin: Pull-up resistor RRES only) function generates reset only when power turned starting level. stable reset will generated power turned again when power level does down level shown (a). such case anticipated, function together with function implement external reset circuit. reset generated only when power level goes down level shown power turned again after this condition continues 100s longer.
hysteresis width (LVHYS) release voltage (LVDET+LVHYS)
reset voltage (LVDET) Reset period Unknown-state (LVUKS) Reset period Reset period
Figure Waveform observed when both functions used (RESET pin: Pull-up resistor RRES only) Resets generated both when power turned when power level lowers. hysteresis width (LVHYS) provided prevent repetitions reset release entry cycles near detection level.
No.A0970-24/25
LC87F2H08A
release voltage
reset voltage
TLVDW
LVDET-0.5V
Figure voltage detection minimum width (Example momentary power loss/Voltage variation waveform)
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellectual property rights which resulted from technical information products mentioned above.
This catalog provides information September, 2007. Specifications information herein subject change without notice.
No.A0970-25/25

LC87F2H08A CMOS 8K-byte FROM 256-byte integrated 8-bit 1-chi

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