Publication 44109 Revision: 3.00 Issue Date: November 2007 2007 A

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Publication 44109 Revision: 3.00 Issue Date: November 2007 2007 A

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Family PhenomProcessor Product Data Sheet
Publication 44109 Revision: 3.00 Issue Date: November 2007
2007 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. information contained herein preliminary advance nature subject change without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, Arrow logo, Phenom combinations thereof, CoolCore 3DNow! trademarks Advanced Micro Devices, Inc. HyperTransport licensed trademark HyperTransport Technology Consortium. trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
PID:44109 Rev:3.00 November 2007
Family PhenomProcessor Product Data Sheet
Revision History
Date
November 2007
Revision
3.00
Description
Initial Public Release
Revision History
PID:44109 Rev:3.00 November 2007
Family PhenomProcessor Product Data Sheet
Family PhenomProcessor Features
following list features capabilities Family Phenomprocessor.
Compatible with Existing 32-Bit Code Base Including support SSE, SSE2, SSE3, SSE4a, ABM, MMXTM, 3DNow!technology legacy instructions Runs existing operating systems drivers Local APIC chip AMD64 Technology AMD64 technology instruction extensions 64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses Sixteen 64-bit integer registers Sixteen 128-bit SSE/SSE2/SSE3 registers Multi-Core Architecture Triple-core quad-core options Balanced Smart Cache Discrete cache structures each core Shared cache structure Machine Check Architecture Includes hardware scrubbing major protected arrays Cache Structures 64-Kbyte 2-Way Associative ECC-Protected Data Cache 64-bit operations cycle, 3-cycle latency 64-Kbyte 2-Way Associative Parity-Protected Instruction Cache With advanced branch prediction 512-Kbyte 16-Way Associative ECC-Protected Cache Exclusive cache architecture storage addition caches 2048-Kbyte (2-Mbyte) Maximum 32-way Associative ECC-Protected Cache Shared cache architecture storage addition exclusive caches Floating-Point Unit Wide Floating-Point Accelerator Floating-Point Unit (FPU) Virtualization Features disable lock Nested paging Rapid Virtualization Indexing Power Management Multiple low-power states Independent Dynamic Core Technology CoolCoreTechnology Dual Dynamic Power Management System Management Mode (SMM) ACPI-compliant, including support processor performance states Supported power states: C1E, Electrical Interfaces DDR2 SDRAM: SSTL_1.8 JEDEC specification DDR2 SDRAM-like electrical specifications also used clock, reset test signals
Family PhenomProcessor Features
PID:44109 Rev:3.00 November 2007
Family PhenomProcessor Product Data Sheet
Refer Family Processor Electrical Data Sheet, order# 40014, electrical details Family processors. HyperTransportTechnology Devices HyperTransport HyperTransport technology supported link, 16-bits each direction, supporting 2000 MT/s GB/s each direction HyperTransport Generation mode 3600 MT/s GB/s each direction HyperTransport Generation mode. Integrated Memory Controller Memory Optimizer Technology Low-latency, high-bandwidth checking with double-bit detect single-bit correct 144-bit DDR2 SDRAM controller operating frequencies Supports four unbuffered DIMMs Available Packages Compliant with RoHS Directive 2002/95/EC) with lead used only small amounts specifically exempted applications Package AM2r2 Refer AM2r2 Processor Functional Data Sheet, order# 41697, functional mechanical details AM2r2 package processor. 940-pin lidded micro 1.27-mm pitch array Organic attach
Family PhenomProcessor Features
PID:44109 Rev:3.00 November 2007
Family PhenomProcessor Product Data Sheet
Compatible Socket Infrastructures
Refer Infrastructure Roadmap, order# 41842 information platform feature implications package socket infrastructure combinations. Family Phenomprocessors support following socket infrastrucutres:
Socket Socket Infrastructure Compatible with AM2r2 package processors Refer Socket Processor Functional Data Sheet, order# 31117, functional mechanical details socket. Socket AM2r2 Socket Infrastructure Compatible with AM2r2 package processors Refer AM2r2 Processor Functional Data Sheet, order# 41697, functional mechanical details AM2r2 socket.
Compatible Socket Infrastructures

Publication 44109 Revision: 3.00 Issue Date: November 2007 2007 A

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