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Four Channel Programmable DC-DC Power Manager
Windows Users Guide Configuration Register Descriptions
information contained Application Note details Configuration Register settings SMB113A four-channel DC-DC power manager. SMB113A Windows Graphical User Interface (GUI) also shown with associated registers functions highlighted. additional explanation device functionality related configuration registers, refer SMB113A Data Sheet. Note: This application note also applies SMB113B SMB117, four-channel programmable DC-DC power managers.
memory (Figure This space subdivided into blocks: general-purpose memory block (0xA0-0xBF) general-purpose memory block (0xC0-0xFF). memory written byte mode page mode bytes). sequential read within general-purpose memory space will cycle through entire array contiguously.
Array-Based Configuration Registers:
non-volatile configuration register content stored array. Upon initial power-up, those locations from array read into volatile registers chip. output these registers determines configuration device. When data written into configuration space, that data written directly into memory array. conclusion internal write cycle, another readout will occur that information transferred from array into volatile register location.
Register Formats Functions
SMB113A internally maps into register fields that divide into four different categories: bytes general-purpose EEPROM memory, bytes nonvolatile configuration registers, bytes non-volatile reserved registers, bytes software enabled volatile registers. memory locations accessed interface, which responds programmable slave address (SA[3:0]=C_17[3:0]) programmable address (BA[2:0]=C17[6:4]).
Volatile Registers:
register space between 0x8F 0x9F consists volatile registers. These registers used commence sequencing, enable disable channels read status individual channels.
General Purpose EEPROM:
register space between 0xA0 0xFF (inclusive) consists bytes general-purpose EEPROM
0xFF
Memory Block
0xBF
Memory Block
Volatile Configuration Configuration Reserved Configuration Configuration Reserved Configuration
0x9F 0x8F 0x5F 0x4F 0x2F 0x00
Figure Memory SMB113A displaying volatile/non-volatile configuration registers general-purpose memory
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Options pull down menus Standard Configuration Registers Settings
Graphical Toolbar with `Mouse-Over'
Window Tabs
Selection Check Boxes
Configuration register content Hexadecimal
Figure SMB113A
Device/Hex File Checksum enable, Input voltage monitoring dynamic voltage control capabilities SMB113A.
SMB113A Windows Graphical User Interface
SMB113A Windows (Figure used with SMX3200 programming `Dongle'. easy Graphical Interface that compatible with Windows 2000 operating systems. consists pull-down menus, check boxes, up/down buttons, etc. generates checksum that compare programmed device configuration register values versus contents. Help Help menu used view SMB113A Datasheet this note while prototyping with Windows GUI. `About' selection will show version number, which also displayed upper left hand corner GUI. advised that user periodically visit Summit site (www.summitmicro.com) check most current data sheet software. Demo help familiarize user with SMB113A systematic tutorial will guide user through extensive feature set. Demo demonstrates power on/off sequencing, independent channel
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Memory SMB113A equipped with bytes user
programmable non-volatile EEPROM memory. From Memory options, pull down menu memory accessed modified several modes. When selection chosen from memory pull down menu memory will automatically selected GUI. user view memory contents either graphical tabular form. contents memory read memory dump read. memory written either single byte page bytes). memory separated into separate byte sections each which independently locked protect memory content. Configuration: configuration pull down menu used read from write configuration registers SMB113A. addition, configuration menu used check acknowledge from addressed device over create detailed description registers their contents. When performing
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read Write operation necessary power applied before command issued. File file menu used open file, save file, modify system settings, exit program. When file saved contents configuration registers saved hexadecimal format, likewise when file opened configuration registers loaded with contents file. After opening file necessary user perform write operation store contents into configuration registers. Additional options file menu allow parameters accessed modified. Features that modified include automatic read after write option, read write speed direct register access mode.
Load settings from hexadecimal file
Write settings Part
Create text file containing register contents description
Write settings Part
Save Settings hexadecimal file format
Interface option selects parallel port
Read settings Part Read settings Part
Figure SMB113A Graphical toolbar pull down menu.
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UV/OV Sequencing:
DESCRIPTION REGISTER Trip Level R[20:23] Glitch Filter. R[20:23] Healthy.R[1C:1F] Power .R[1C:1F] Force SD.R[1C:1F] Trip Level R[20:23] Glitch Filter. R[20:23] Healthy.R[1C:1F] Power Off.R[1C:1F] Force SD.R[1C:1F] Sequence Position.R[C:F] Sequence Mode.R[11] Power Enable.R[13] Power Delay.R[C:F] Power Delay.R[C:F] Last Sequence Position Used. Sequence Termination Timer Reset Timer Slew Rate Control Reset Triggers Healthy .R2D Wait Power Command. Power On/Off Command Clear Power Latched Trip Point. Force Shut Down Power Healthy.R2D Latched. Power Latched
Interfacing:
Programmable Slave Address Programmable Address. Configuration Registers Lock.
Voltages:
Nominal R[4:7] Margin .R[5C:5F] Margin R[54:57] Divider R[30:31]
Margin/Status:
Power Enable Status Register R[98:99] Margin Command R[9C:9D]
Miscellaneous Settings:
Trip Point. Force Shut Down Power Healthy.R2D Latched
Memory Array:
Lock Memory Block Lock Memory Block
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Registers 0x00 through 0x04 control non-overlap delay (dead time) n-channel p-channel MOSFETS. dead times described below refer HSRDV LSDRV states. Registers 0x00 0x04 correspond channels through three respectively.In default mode, contents registers 0x04 through 0x07 hidden from user unless expert mode selected. desired output voltage user enters desired output voltage Output Voltage box, double clicking typing value pressing enter. Once desired output voltage been entered, reference voltage automatically calculated loaded into corresponding register. write operation must then performed change output voltage.
Registers (HIDDEN REGISTER) Actions Minimum falling edge dead time Maximum falling edge dead time Minimum rising edge dead time Maximum rising edge dead time Table Dead time control registers. This register displayed GUI.
Press enter Expert Mode
Figure default settings allow user enter output voltage settings without specifying reference voltage When expert mode selected, Registers 0x04 through 0x07 modified from GUI. These registers output voltage COMP1_ChX
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feedback SMB113A. Voltage range programmable from -1.0V increments channels 0-3. corresponds Channel 3062 8/28/2007
corresponds channel allows user increment decrement value stored registers bit, corresponding change, Registers enter value directly. output voltage each channel calculated according formula displayed GUI.
Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.004 volts Channel Nominal Point 1.000 volts
Table Programmable reference point values.
Figure Channel through reference points Registers Actions These registers unused, modify. Table Unused registers Registers 0C-0F correspond sequence position sequence positions skipped last sequence power-on/off delay settings channels through position entered into appropriate register (R14). respectively. channels will only sequence intermediate used supply other channels when channel manual mode. channel then this channel must enabled prior occupy sequence position, long channels supplying. There stipulation
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number channels that occupy same sequence position. Each channel power-on delay, which 1.5, 12.5, Each channel will enabled power delay after sequence position been entered. Similarly, each channel will disabled power delay after sequence position been entered during power sequence. When SEQUENCING selected, power delay included sequence termination timeout period, should taken into account accordingly.
Figure expert settings allow user manually adjust reference voltages used determine output voltages. Registers Actions Channel sequence position Channel sequence position Channel sequence position Channel sequence position Channel used (Null) *All other combinations disallowed Channel power-on delay Channel power-on delay 12.5 Channel power-on delay Channel power-on delay Channel power-off delay Channel power-off delay 12.5 Channel power-off delay Channel power-off delay Table Programmable sequence position options.
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Figure Registers 0x0Cto 0x0F determine sequence position power on/off delay channels.
Register Actions This register unused Table Unused registers manual mode selected during which, Register controls sequencing option sequencing disabled channels channels. Each channel sequence controlled enable signal. When sequencing three modes: Normal Sequencing, Sequencing with Enable, sequencing with channel bypass, mode selected, sequencing initiated either power command PWREN complete description sequencing modes please refer Figure register addition, depending programmed settings.
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Register Actions Disallowed. use. Channel Sequence Disallowed. use. Channel Manual Control Disallowed. use. Channel Sequence Disallowed. use. Channel Manual Control Disallowed. use. Channel Sequence Disallowed. use. Channel Manual Control Disallowed. use. Channel Sequence Disallowed. use. Channel Manual Control Table Programmable sequence mode options.
Figure Register controls sequencing option channels. Register controls mode which SMB113A individually. When enable signal receives enable signal. There three ways assigned volatile configuration register (R90), channel receive enable signal: from volatile register must initialized upon receipt system configuration that initialized power. initialized then power command (Default Default Off), from general will begin sequencing that channel; when purpose enable input. When channel initialized off, active enable must supplied normal sequencing mode, enable input will before power command will commence disengaged. enable mode each channel sequencing.
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Register Actions This register unused
Table Unused registers Register Actions Channel Defaulted Channel Default Channel PWREN Disallowed. use. Channel Defaulted Channel Default Channel PWREN Disallowed. use. Channel Defaulted Channel Default Channel PWREN Disallowed. use. Channel Defaulted Channel Default Channel PWREN Disallowed. use. Table Programmable enable signal source SMB113A.
Figure Register controls enable options channels.
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supplied SMB113A, provided channels Register controls settings input voltage enabled. monitoring power sequencing control. sequencing control mechanism selected, power sequencing operation initiated sequencing will commence once sequencing writing volatile register, asserting mechanism provided. general-purpose enable input pin, PWREN. Input voltage monitoring thresholds allow user Sequencing initiated PWREN select whether violation UV/OV thresholds ways, asserting PWREN high, result termination supplies. available programming enable input active push options allow supplies sequenced button enable were PWREN momentarily opposite order they where sequenced (powerasserted low. off) immediately terminate supplies (force sequencing control mechanism selected, shutdown). sequencing will commence soon power Register Actions Register initiates sequencing. Labeled Wait Power command Register does initiate sequencing. Labeled Wait Power command PWREN does initiate sequencing PWREN initiates sequencing does trigger Power-Off triggers Power-Off does trigger Power-Off triggers Power-Off Power-Off latched Power-Off latched Trigger does trigger Force Shutdown triggers Force Shutdown does trigger Force Shutdown triggers Force Shutdown Force Shutdown latched Force Shutdown latched Trigger Table Programmable under voltage options SMB113A.
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Figure Register determines settings input voltage monitor functions. SMB113A equipped with global slew rate SROUT SRREF +R1/R2) limiting soft start feature. soft start allows output possible slew rates displayed Table voltages gradually ramped rate that function global slew rate reference proportional final output voltage global resistor divider settings. slew rate setting. selectable global slew rate soft start control also disabled when values vary from 400V/s V/s. actual slew necessary; however, soft start function should rate each channel then computed from disabled boost channels. equation Global Slew Rate Resistor Divider 90K/10K 80K/20K 70K/30K 60K/40K 50K/50K 40K/60K 30K/70K 400V/sec Voltage Range 3.33V 2.5V 2.0V 1.67V 1.43V Voltage Step Size 12mV 11mV 10mV 200V/sec 100V/sec 50V/sec 50V/sec 33V/sec 25V/sec 20V/sec
Output Slew Rate (V/sec) 4000 2000 1333 1000 2000 1000 1000
Table Voltage slew rates function internal resistor divider global slew rate setting.
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Register Actions Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate
Table Programmable global slew rate options SMB113A.
Figure Register sets global slew rate. Register controls locking configuration registers locked avoid unintentional writes these registers. This option, however, allowed when using GUI, irreversible. memory that separated into continuous independently lockable sections also locked.
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Registers Register locks Actions Configuration registers unlocked Configuration registers locked Memory Block unlocked Memory Block locked Memory Block unlocked Memory Block locked Table Programmable register locking options volatile non-volatile memory.
Figure Register controls configuration memory locking mechanism.
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Register contains Slave address from which registers accessed. slave address possible addresses. SMB113A always slave, never master. After address been changed using will necessary address next read write command. address search also performed which address first device sent acknowledge returned.
Registers Slave Address Actions Seven level Dynamic voltage control disabled Seven level Dynamic voltage control enabled Slave address 0000000 Slave address 0000001 Slave address 1111111 Table Programmable slave address options.
Figure Register sets slave address, seven level dynamic voltage control SMB113A. Register Actions This register unused Table Unused registers Registers through correspond over over voltage under voltage cause power voltage under voltage settings channels force shutdown. addition, triggering power off, through respectively. Similar battery HEALTHY status also asserted when monitoring registers, registers 1C-1F control whether over voltage under voltage occur.
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Registers Over Voltage Under Voltage triggers Actions Channel does trigger Force Shutdown Channel triggers Force Shutdown Channel does trigger Power-On/Off Channel triggers Power-On/Off Channel does trigger Healthy Channel triggers Power- Healthy Channel does trigger Power- nRESET Channel triggers Power- nRESET Channel does trigger Force Shutdown Channel triggers Force Shutdown Channel does trigger Power-On/Off Channel triggers Power-On/Off Channel does trigger Healthy Channel triggers Power- Healthy This READ-only. Attempt change will cause part malfunction Table Programmable under voltage over voltage options.
Figure Registers through control over voltage under voltage fault responses channels through Registers bits control allows output equal input voltage limits output voltage range each channel. minimum voltage controller sustain. options allow channel output approach while limiting upper output limit. 100% limit
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Register Channel duty cycle options Table Channel duty cycle options. Actions 100% duty cycle, minimum duty cycle enabled duty cycle, minimum duty cycle disabled
Register Channels duty cycle options Actions Must Table Channel duty cycle options. Register Actions Channel 100% duty cycle, minimum duty cycle enabled Channel duty cycle, minimum duty cycle disabled Channel 100% duty cycle, minimum duty cycle enabled Channel duty cycle, minimum duty cycle disabled Table Channel duty cycle options. Register Channel duty cycle options Table Channel duty cycle options. Actions Channel 100% duty cycle, minimum duty cycle enabled Channel duty cycle, minimum duty cycle disabled
Figure Duty cycle options Tab. correct settings chosen based user provided input voltage setting. points programmed separately each Registers through bits control four outputs, available settings include glitch filters trip points percent above (OV) nominal output channels through respectively. trip voltage, percent below (UV) Summit Microelectronics, 3062 8/28/2007
nominal output voltages settings. order condition occur output voltage must exceed trip point minimum period corresponding value glitch filter register. glitch filter times selectable
Registers Over Voltage Under Voltage glitch filter trip levels Actions Channel glitch filter Channel glitch filter Channel glitch filter Channel glitch filter Channel trip level Channel trip level Channel trip level Channel trip level Channel trip level Channel trip level Channel trip level Channel trip level Table Under voltage over voltage trip point options.
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Register Actions This register unused Table Unused registers Register controls trip point levels. should always exceed trip point. This programmable threshold values range from 2.55V requirement stems from fact that latched 3.6V increments. trip point that will reset unless trip point passed then exceeded.
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Register programmable threshold levels Actions SMB113A SMB117 trip level 2.55 trip level trip level trip level 2.55 trip level trip level Table Programmable battery monitoring options.
Figure Register controls input voltage monitoring trip point levels. Register Table Channel interleaving options.
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Actions Single phase, channels switch phase Half channels switch degrees phase
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Register contains settings sequence termination timer. When three sequencing modes selected, sequence termination timer used. This function prevents stalled power power sequencing operation from occurring. event that sequence termination timer expires before channel passes setting, supplies will immediately terminated with force shutdown operation. allowable sequence termination timer timeout periods 100, advised that sequence termination timer should used with sequencing with enable; unless enable signal valid time power-on sequencing operation begins.
Register Actions PWREN acts active push-button initiate sequencing PWREN active High input initiate sequencing PWREN debounce time PWREN debounce time PWREN debounce time PWREN debounce time Sequence termination timeout period Sequence termination timeout period Sequence termination timeout period Sequence termination timeout period Reset timeout period Reset timeout period Reset timeout period 100ms Reset timeout period Table Programmable sequence termination options.
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Figure Register controls Sequence Termination Timer setting. Register contains settings capable disabling When enabled, outputs will slew rate soft start feature. When soft start disabled, dependent programmed output voltage outputs will slew fixed rate dependent global slew rate reference. maximum slew rate capabilities output drivers. Register Disable soft start Actions Channel soft start disabled Channel soft start enabled Channel soft start disabled Channel soft start enabled Channel soft start disabled Channel soft start enabled Channel soft start disabled Channel soft start enabled These bits READ-only. Attempt change will cause part malfunction
Table Programmable soft start settings.
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Figure Register enables disabled soft Start function SMB113A. Register contains data pertinent sequencing functionality SMB113A. When three sequencing modes selected, necessary store last sequence position used. sequence positions must begin sequence position incrementally increase. necessary store last sequence position plus this register that proper operating mode transitioned default, SMB113A automatically updates last sequence position used according necessary guidelines.
Register Last sequence position used (HIDDEN REGISTER) Actions Last Sequence position used Last Sequence position used Last Sequence position used Last Sequence position used *All other combinations disallowed will cause part malfunction Table Programmable last sequence position used options.
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Figure Register sets last sequence position used during sequencing. Register allows healthy output asserted when voltage VBATT falls below settings. Register HEALTHY triggers Actions Multiplexed Healthy/nRESET acts Healthy output Multiplexed Healthy/nRESET acts Reset output Reset Triggers Healthy Battery Fault Triggers Healthy Power Fail Triggers Healthy Battery Fault Triggers Reset Power Fail Triggers Reset Table Programmable options under voltage VBATT supply trip healthy pin.
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Figure Register controls HEALTHY triggers. Register controls setting internal automatically selects value resistor divider resistor dividers channels. based desired output voltage. upper lower resistors Register Internal resistor divider settings Step Down outputs Actions Must Channel 20k, Channel 30k, Channel 90k, Channel 20k, Channel 30k, Channel 90k, Table Programmable resistor divider selection options.
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Register Internal resistor divider settings Actions Channel 20k, Channel 30k, Channel 90k, Channel 20k, Channel 30k, Channel 90k, Table Programmable resistor divider selection options.
Figure Register internal resistor dividers.
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Figure Registers through control reference voltage margin settings. Registers through control reference voltages margin high settings. Register through Actions These registers unused, modify. Table Unused registers. Registers through contain margin stored margin high register. available settings channels respectively Registers settings this range from 0-1.0V channels through contain margin high settings NOTE: When write read operation channels respectively. outputs performed, SMB113A must margining. adjusted writing volatile margin command Subsequently when write read operation register. When non-volatile write operation carried selected, will automatically adjust voltage COMP1 adjusted from outputs their nominal points. nominal setting setting corresponding that Registers Channel Margin settings (Channel Register etc.) Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.004 volts Channel Nominal Point 1.000 volts Table Programmable margin point.
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Register through Table Unused registers. Actions These registers unused, modify.
Registers Channel Margin high settings (Channel Register etc.) Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.004 volts Channel Nominal Point 1.000 volts Table Programmable margin high point. Register through Table Unused registers.
Actions These registers unused, modify. controlled initialized initialized then register will enable disable channel. setting this register depends current state register which determines initialized off.
Register volatile configuration register used enable disable outputs channels 0-3. When SMB113A normal sequencing mode outputs enabled disabled their respective enable signals. When enable signal
Registers Volatile Power Enable Actions Power (h13[7:6]=00) Enabled (h13[7:6]=01) Disabled Power (h13[7:6]=01) Enabled (h13[7:6]=00) Disabled Power (h13[5:4]=00) Enabled (h13[5:4]=01) Disabled Power (h13[5:4]=01) Enabled (h13[5:4]=00) Disabled Power (h13[3:2]=00) Enabled (h13[3:2]=01) Disabled Power (h13[3:2]=01) Enabled (h13[3:2]=00) Disabled Power (h13[1:0]=00) Enabled (h13[1:0]=01) Disabled Power (h13[1:0]=01) Enabled (h13[1:0]=00) Disabled Table Programmable sequence mode options.
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Figure Register volatile register used enable disable output voltages when enable selected. Normal-sequencing mode, Enable disabled. Figure: Register initiates power on/off sequencing clears latched state internal register. When SMB113A three power sequencing modes, sequenced write command this registers. When voltage Register Power control Actions Power-ON Power-OFF Clear Table Programmable Power control. VBATT dips below trip point register will become latched. latched condition automatically cleared dipping below trip point, register cleared writing volatile register.
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Figure Register volatile register used commence Power sequencing operation, also contains setting used clear latched condition volatile register. Register non-volatile read only registers When supplies off, they will show under that contain information about current state voltage condition because they below outputs. These registers read time programmable threshold. When supplies they will tell user whether condition within programmed range, present monitored output voltages. settings will detected. Register volatile 2-byte read Actions First byte ignored Table Programmable sequence mode options.
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Register volatile 2-byte write Actions Channel Channel Channel Channel Channel Channel Channel Channel Table Channel status register.
Figure Registers volatile read only registers that contain current state outputs. Register volatile margin control register. When margin high margin operation selected, voltage COMP1 (channels 0-3) will changed reflect value stored margin high threshold register.
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Register Channel[0:3] Margin Control Register Actions Channel Margin High with 9D[7:6] Channel Margin with 9D[7:6] Channel Margin High with 9D[7:6] Channel Margin with 9D[7:6] Channel Margin High with 9D[7:6] Channel Margin with 9D[7:6] Table Margin register.
Register Channel[0:3] Margin Control Register Actions Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal Table Output voltage control register used switch between different outputs.
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Figure Register volatile registers used margin output voltages margin high margin voltage settings.
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NOTICE
SUMMIT Microelectronics, Inc. reserves right make changes products contained this publication order improve design, performance reliability. SUMMIT Microelectronics, Inc. assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained herein reflect representative operating parameters, vary depending upon user's specific application. While information this publication been carefully checked, SUMMIT Microelectronics, Inc. shall liable damages arising result error omission. SUMMIT Microelectronics, Inc. does recommend products life support aviation applications where failure malfunction product reasonably expected cause failure either system significantly affect their safety effectiveness. Products authorized such applications unless SUMMIT Microelectronics, Inc. receives written assurances, satisfaction, that: risk injury damage been minimized; user assumes such risks; potential liability SUMMIT Microelectronics, Inc. adequately protected under circumstances.
Revision This document supersedes previous versions. Please check Summit Microelectronics Inc. site http://www.summitmicro.com data sheet updates. Copyright 2007 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE POWER GREEN PLANET
ADOC
registered trademarks Summit Microelectronics Inc., trademark Philips Corporation.
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