Windows Users Guide Configuration Register Descriptions informati
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Nine-Channel Digitally Programmable DC/DC converter with integrated Power Management
Windows Users Guide Configuration Register Descriptions
information contained Application Note details Configuration Register settings SMB120 nine-channel DC-DC converter, monitor, marginer sequencer. SMB120 Windows Graphical User Interface (GUI) also shown with associated registers functions highlighted. additional explanation device functionality related configuration registers, refer SMB120 Data Sheet.
memory (Figure This space subdivided into blocks: general-purpose memory block (0xA0 0xBF) general-purpose memory block (0xC0 0xFF). memory written byte mode page mode bytes). sequential read within general-purpose memory space will cycle through entire array contiguously.
Array-Based Configuration Registers:
non-volatile configuration register content stored array. Upon initial power-up, those locations from array read into volatile registers chip. output these registers that determine configuration device. When information written into configuration space, that data written directly into array. conclusion internal write cycle, another readout will occur that information transferred from array into volatile register location.
Register Formats Functions
SMB120 internally maps into register fields that divide into four different categories: bytes general-purpose EEPROM memory, bytes nonvolatile configuration registers, bytes non-volatile reserved registers, bytes software enabled volatile registers. memory locations accessed interface, which responds programmable slave address (SA[3:0] C_17[3:0]) programmable address (BA[2:0] C17[6:4]).
Volatile Registers:
register space between 0x8F 0x9F consists volatile registers. These registers used commence sequencing, enable disable channels read status individual channels.
General Purpose EEPROM:
register space between 0xA0 0xFF (inclusive) consists bytes general-purpose EEPROM
0xFF
Memory Block
0xBF
Memory Block
Volatile Configuration Configuration Reserved Configuration Configuration Reserved Configuration
0x9F 0x8F 0x5F 0x4F 0x2F 0x00
Figure Memory SMB120 displaying volatile non-volatile configuration registers generalpurpose memory
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Options pull down menus Standard Configuration Registers Settings
Graphical Toolbar with `Mouse-Over'
Window Tabs
Selection Check Boxes
Configuration register content Hexadecimal
Figure SMB120
Device/Hex File Checksum enable, battery monitoring dynamic voltage control capabilities SMB120.
SMB120 Windows Graphical User Interface
SMB120 Windows (Figure used with SMX3200 programming `Dongle'. easy Graphical Interface that compatible with Windows 2000 operating systems. consists pull-down menus, check boxes, up/down buttons, etc. generates checksum that compare programmed device configuration register values versus contents. Help Help menu used view SMB120 Datasheet this note while prototyping with Windows GUI. `About' selection will show version number, which also displayed upper left hand corner GUI. advised that user periodically visit Summit site (www.summitmicro.com) check most current data sheet software. Demo help familiarize user with SMB120 systematic tutorial will guide user through extensive feature set. Demo demonstrates power on/off sequencing, independent channel
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Memory SMB120 equipped with bytes user
programmable non-volatile EEPROM memory. From Memory options, pull down menu memory accessed modified several modes. When selection chosen from memory pull down menu memory will automatically selected GUI. user view memory contents either graphical tabular form. contents memory read memory dump read. memory written either single byte page bytes). memory separated into separate byte sections each which independently locked protect memory content. Configuration: configuration pull down menu used read from write configuration registers SMB120. addition, configuration menu used check acknowledge from addressed device over create detailed description registers their contents. When performing
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read Write operation necessary power applied before command issued. File file menu used open file, save file, modify system settings, exit program. When file saved contents configuration registers saved hexadecimal format, likewise when file opened configuration registers loaded with contents file. After opening file necessary user perform write operation store contents into configuration registers. Additional options file menu allow parameters accessed modified. Features that modified include automatic read after write option, read write speed direct register access mode.
Write settings Part Load settings from hexadecimal file
Create text file containing register contents description
Write settings Part
Save Settings hexadecimal file format
Interface option selects parallel port
Read settings Part Read settings Part
Figure SMB120 Graphical toolbar pull down menu.
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UV/OV:
DESCRIPTION REGISTER Trip Level R[20:27] Glitch Filter. R[20:27] Reset. R[18:1F] Healthy. R[18:1F] Power R[18:1F] Force R[18:1F] Trip Level R[20:27] Glitch Filter. R[20:27] Reset R[18:1F] Healthy. R[18:1F] Power Off. R[18:1F] Force R[18:1F] Battery Fault Battery Fault Healthy .R2D Battery Fault Reset .R2D Battery Fault Latched Battery Fault Latched.
Miscellaneous Settings:
Phase/PLL options.2E duty cycle .R20, R21, duty cycle .R30, R35, R36, R37, R38, Last Used Termination Timer .R2A Dock Trip Point Reset Timer .R2A Slew Rate Control Reset Triggers Healthy .R2D Wait Power Command PWR_EN1 used power Debounce.R2A Power On/Off Command Clear Power Fail
Sequencing:
Sequence Position. R[8:F] Sequence Mode. R[10:11] Power Enable. R[12:13] Power Delay. R[8:F] Power Delay. R[8:F]
Voltages:
Nominal R[0:7] Margin R[58:5F] Margin R[50:57]
Interfacing:
Programmable Slave Address Programmable Address. Configuration Registers Lock.
Battery Monitoring:
Power Fail Trip Point Power Fail Force ShutDn. Power Fail Off. Power Fail Healthy.R2D Power Fail Reset .R2D Power Fail Latched Power Fail Latched Battery Fault Trip Point Battery Fault Force ShutDn
Margin/Status:
Power Enable. Status Register R[98:99] Margin Command R[9C:9D]
Memory Array:
Lock Memory Block Lock Memory Block
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default mode, contents registers 0x00 through 0x07 hidden from user unless expert mode selected. desired output voltage user enters desired output voltage Output Voltage box, double clicking typing value pressing enter. Once desired output voltage been entered, reference voltage automatically calculated loaded into corresponding register. write operation must then performed change output voltage.
Press enter Expert Mode
Figure default settings allow user enter output voltage settings without specifying reference voltage. When expert mode selected, Registers through modified from GUI. These registers output voltage COMP1_ChX feedback SMB120. Voltage range programmable from -1.0V increments channels 1-7, fixed channel channel output voltage modifying voltage VREF pin; voltage this programmable from Register 2.0V increments. corresponds Channel corresponds channel allows user increment decrement value stored registers bit, corresponding change, enter value directly. output voltage each channel calculated according formula displayed GUI.
Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.008 volts Channel Nominal Point 2.000 volts
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Registers Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.004 volts Channel Nominal Point 1.000 volts
Figure expert settings allow user manually adjust reference voltages used determine output voltages. Registers 08-0F correspond sequence position power-on/off delay settings channels through respectively. channels will only sequence when channel manual mode. channel occupy sequence position, long sequence positions skipped last sequence position entered into appropriate register (R14). intermediate used supply other channels then this channel must enabled prior channels supplying. There stipulation number channels that occupy same sequence position. Each channel power-on delay, which 1.5, 12.5, Each channel will enabled power delay after sequence position been entered. Similarly, each channel will disabled power delay after sequence position been entered during power sequence. When NORMAL SEQUENCING SEQUENCING WITH ENABLE selected, power delay included sequence termination timeout period, should taken into account accordingly.
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Registers Actions Channel sequence position Channel sequence position Channel sequence position Channel used Channel power-on delay Channel power-on delay Channel power-on delay 12.5 Channel power-on delay Channel power-off delay Channel power-off delay Channel power-off delay 12.5 Channel power-off delay
Figure Registers 08-0F determine sequence position power on/off delay channels through respectively
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Registers control sequencing options channels respectively. Each channel sequence three modes: Normal Sequencing, Sequencing with Enable, sequencing with channel bypass, complete description sequencing modes please refer Figure registers addition, manual mode selected during which, sequencing disabled channels controlled enable signal. When sequencing mode selected, sequencing initiated either power command PWR_EN1 depending programmed settings.
Registers (channels (channels Actions Channel Normal Sequencing Channel Sequence with Channel Bypass Channel Sequence with Enable Channel Manual sequencing Channel Normal Sequencing Channel Sequence with Channel Bypass Channel Sequence with Enable Channel Manual sequencing Channel Normal Sequencing Channel Sequence with Channel Bypass Channel Sequence with Enable Channel Manual sequencing Channel Normal Sequencing Channel Sequence with Channel Bypass Channel Sequence with Enable Channel Manual sequencing
Figure Registers control sequencing option channels through 5-through respectively.
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RESTART AFTER FORCESHUTDO COMMAND
SEQUENCE
CURRENT SEQUENCE
NEXT SEQUENCE
ABLE
NORMAL
BYPASS
ELAY
DELAY
DELAY
ENABLE
ENABLE
ABLE
ENABLE
ENABLE
UT<=UV
UT>UV
Figure Flow chart displaying three programmable sequencing modes, Normal Sequencing, Sequencing with enable, Sequencing with channel bypass.
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Registers control mode which SMB120 receives enable signal. There four different ways which channel receive enable signal: from volatile configuration that initialized off, from general purpose enable inputs. When channel normal sequencing mode, enable input will disengaged. enable mode each channel individually. When enable signal assigned volatile configuration register (R90), register must initialized upon receipt system power. initialized then power command will begin sequencing that channel; when initialized off, active enable must supplied before power command will commence sequencing.
Registers (channels (channels Actions Channel defaulted Channel defaulted Channel PWR_EN[0] Channel PWR_EN[1] Channel defaulted Channel defaulted Channel PWR_EN[0] Channel PWR_EN[1] Channel defaulted Channel defaulted Channel PWR_EN[0] Channel PWR_EN[1] Channel defaulted Channel defaulted Channel PWR_EN[0] Channel PWR_EN[1]
Figure Registers control enable options channels through 5-through respectively.
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Register controls settings Battery Fault Power Fail thresholds; addition, power control located here. power sequencing operation initiated either PWR_EN1 configuration register space. When PWR_EN1 been programmed power pin, must driven high initiate sequencing. When power supplied SMB120 automatically commence power sequencing provided channels enabled, wait power sequencing command from volatile power register (R91). addition, register allows user Registers select whether violation battery monitoring thresholds will result termination supplies. available options allow supplies sequenced opposite order they where sequenced (power-off) immediately terminate supplies (force shutdown). When force shutdown power occurs user choose whether terminating condition will latched. When nBATT_FAULT threshold exceeded, output voltage will automatically terminated. latched condition selected outputs will automatically sequenced
Actions Power-On/Off Power-On/Off Power-On/Off signal supplied Power-On/Off signal supplied PWR_EN[1] BATT_FAULT does trigger Power-Off BATT_FAULT triggers Power-Off POWER_FAIL does trigger Power-Off POWER_FAIL triggers Power-Off Power-Off latched Power-Off latched BATT_FAULT POWER_FAIL Trigger BATT_FAULT does trigger Force Shutdown BATT_FAULT triggers Force Shutdown POWER_FAIL does trigger Force Shutdown POWER_FAIL triggers Force Shutdown Force Shutdown latched Force Shutdown latched BATT_FAULT POWER_FAIL Trigger
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Figure Register determines settings battery monitoring functions. SMB120 equipped with global slew rate limiting soft start feature. soft start allows output voltages gradually ramped rate that proportional final output voltage global slew rate setting. selectable global slew rate Registers values vary from 400V/s V/s. soft start control also disabled when necessary; however, soft start function should disabled boost channels.
Actions Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate Global Slew Rate
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Figure Register sets global slew rate. Register controls DOCK_DC trip point configuration memory locking bits. DOCK_DC voltage monitoring input continually monitors voltage input until monitored voltage exceeds programmed threshold value which point delay will begin before DC_IN asserted. DOCK_DC threshold Registers programmable from 3.6-4.8V increments. configuration registers also locked avoid unintentional writes configuration registers, this option, however, allowed when using GUI, irreversible. memory that separated into continuous independently lockable sections also locked.
Docking station trip point register locks Actions DOCK_DC trip level DOCK_DC trip level DOCK_DC trip level Configuration registers unlocked Configuration registers locked Memory Block unlocked Memory Block locked Memory Block unlocked Memory Block locked
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Figure Register controls configuration memory locking mechanism, well DOCK_DC trip point. Register contains Slave address from which registers accessed. slave address possible addresses. SMB120 always slave, never master. Register After address been changed using will necessary address next read write command. address search also performed which address first device sent acknowledge returned.
Address possible addresses) Actions address address address
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Register Register Slave Address possible slave addresses) Actions Slave address 0010 Slave address 1001 Slave address 1011 Slave address 1111 Address used communication (Bit7 used; reserved bit) Actions address 000; Slave address Address 1001000x address 001; Slave address Address 1011001x address 000; Slave address Address 1111111x
combination slave address address used determine which address SMB120 will respond. This address determined combining slave addresses follows: [SA3 depending whether access part read write.
Figure Register sets slave address SMB120. Registers through correspond over voltage under voltage settings channels through respectively. Similar battery monitoring registers, registers 18-1F control whether over voltage under voltage cause power force shutdown. addition, triggering power off, number status pins also asserted when over voltage under voltage occur. status pins include HEALTHY nRESET,
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Registers Over Voltage Under Voltage triggers Actions Channel does trigger Force Shutdown Channel triggers Force Shutdown Channel does trigger Power-On/Off Channel triggers Power-On/Off Channel does trigger Healthy Channel triggers Power- Healthy Channel does trigger Reset Channel triggers Power- Reset Channel does trigger Force Shutdown Channel triggers Force Shutdown Channel does trigger Power-On/Off Channel triggers Power-On/Off Channel does trigger Healthy Channel triggers Power- Healthy Channel does trigger Reset Channel triggers Power- Reset
Figure Registers through control over voltage under voltage fault responses channels through respectively. Registers through pertain glitch filters trip points. trip points programmed separately each outputs, available settings include 5,10,15 percent above (OV) nominal output voltage, 5,10,15 percent below (UV)
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nominal output voltages settings. order condition occur output voltage must exceed trip point minimum period corresponding value glitch filter register. glitch filter times selectable
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Registers Over Voltage Under Voltage Glitch Filter Trip Levels Actions register description page register description page Channel glitch filter Channel glitch filter Channel glitch filter Channel glitch filter Channel trip level Channel trip level Channel trip level Channel trip level Channel trip level Channel trip level Channel trip level Channel trip level
Figure Registers maximum duty cycle buck controllers. shown figure each buck controller SMB120 individually either 100% maximum duty cycle. When operating 100% duty cycle controller operates dropout mode, which lower NFET gate held high,
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PFET gate held subsequently allowing output follow input voltage. When duty cycle option selected, maximum output voltage equal times input voltage.
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Registers Registers Registers Channel Duty Cycle Actions Channel duty cycle 100% Channel duty cycle 100% Channels Duty Cycle Actions Channel duty cycle 100% Channel duty cycle 100% Channel duty cycle 100% Channel duty cycle 100% Channel Duty Cycle Actions Channel duty cycle 100% Channel duty cycle 100%
Figure Registers through control under voltage over voltage fault levels glitch filter times.
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Register controls nBATT_FAULT POWER_FAIL trip point levels. programmable threshold values range from 2.55V 3.6V increments. POWER_FAIL trip point should always exceed nBATT_FAULT trip point. This requirement stems from fact that POWER_FAIL Register latched that will reset unless nBATT_FAULT trip point passed then exceeded. When battery voltage falls below level specified nBATT_FAULT threshold, will turn off.
nBATT_FAULT POWER_FAIL levels Actions nBATT_FAULT trip level 2.55 nBATT_FAULT trip level nBATT_FAULT trip level POWER_FAIL trip level 2.55 POWER_FAIL trip level POWER_FAIL trip level
Figure Register controls battery monitoring trip point levels.
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Register contains settings power debounce time sequence termination timer. When PWR_EN1 programmed power pin, PWR_EN1 debounced programmable period. This allows function push button switch suitable human interaction. programmable settings this When three sequencing modes selected, sequence termination timer used. This function prevents stalled power power sequencing operations from occurring. event that sequence termination timer expires before channel passes setting, supplies will immediately terminated with force shutdown operation. allowable sequence termination timer timeout periods 100, advised that sequence termination timer should used with sequencing with enable; unless enable signals valid time power-on sequencing operation begins. Register contains settings reset timeout period. reset signal also asserted active high HOST_RESET input UV/OV violation channel. RESET output waits reset delay period 100, before reset released
Register
Actions Power-on Debounce time Power-on Debounce time Power-on Debounce time Power-on Debounce time Sequence termination timeout period Sequence termination timeout period Sequence termination timeout period Sequence termination timeout period Reset timeout period Reset timeout period Reset timeout period =100 Reset timeout period =200
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Figure Register controls Power de-bounce period, Reset delay, sequence termination timer. Register contains settings capable disabling soft start feature. When soft start disabled, outputs will slew fixed rate dependent maximum slew rate capabilities output drivers. Registers Disable Soft Start When enabled, outputs will slew rate dependent programmed output voltage global slew rate reference. boost channels should never have slew rate disabled.
Actions Channel soft start disabled Channel soft start enabled Channel soft start disabled Channel soft start enabled Channel soft start disabled Channel soft start enabled Channel soft start disabled Channel soft start enabled modify
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Figure Register enables disabled soft Start function SMB120. Soft Start control should disabled boost channels (channels 0-3). Register contains data pertinent sequencing functionality SMB120. When three Sequencing modes selected, necessary store last sequence position used. sequence positions must begin sequence position incrementally increase. necessary store Registers last sequence position plus this register that proper operating mode transitioned default, SMB120 automatically updates last sequence position used according necessary guidelines.
Last Sequence Position Used Actions Last Sequence position used Last Sequence position used Last Sequence position used Last Sequence position used Last Sequence position used Last Sequence position used Last Sequence position used Last Sequence position used Last Sequence position used
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Figure Register sets last sequence position used during sequencing.
Register allows reset healthy outputs asserted when voltage VBATT falls below POWER_FAIL BATT_FAULT settings. Register
There additional option that allows HEALTHY trigger assertion RESET pin.
HEALTHY RESET Triggers Actions RESET triggers HEALTHY nBATT_FAULT triggers HEALTHY POWER_FAIL triggers HEALTHY nBATT_FAULT triggers RESET nBATT_FAULT triggers RESET
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Figure Register controls RESET HEALTHY triggers. Register controls internal resistor divider step down buck converters. upper lower resistors automatically selects value resistor divider based desired output voltage. Since resistor, divider network external inverting step-up channels value stored internally part. result user must either Register enter actual values used based upon provided equations, "Find values" selected which case user should displayed values values remembered GUI, which stores them file located same directory GUI. Without values loaded into boxes, output voltage cannot displayed.
Internal Resistor Divider Settings Step Down Outputs Actions Channel 20k, Channel 30k, Channel 90k, Channel 20k, Channel 30k, Channel 90k,
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Register Internal Resistor Divider Settings Actions Channel 20k, Channel 30k, Channel 90k, Channel 20k, Channel 30k, Channel 90k,
Figure Register internal resistor divider.
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FACTORY PROGRAMMABLE SETTINGS Registers control minimum maximum allowable duty cycle boost inverting controllers. programmable options allow either option. boost converters must same duty cycle setting while Inverting converter choose either option When duty cycle option selected, boost inverting controllers operate pulse-skipping mode, where LSDRV output switches only when necessary maintain programmed voltage. When option selected, boost inverting controllers operate fixed frequency mode operation. fixed frequency mode minimum load necessary prevent output voltages from exceeding there programmed value, value minimum load found SMB120 datasheet. Register controls channel interleaving options SMB120. channel interleaving options allow each converter switch phase with respect converters. This spreads current demands battery over entire cycle reduces battery droop. channel interleaving option also reduces channel-to-channel interference inductive coupling. minimum duty cycle channel interleaving options located write protected non-volatile registers that only programmed time part ordered. facilitate ordering process specify desired settings hexadecimal text file generated after saving settings. duty cycle converter phase interleaving options select 100% bubble (see figure desired phase Factory Programmable Settings section. After factory programmable settings have been selected, settings will saved file. view selected duty cycle option open newly saved file, selected options should displayed Ordering Information section Duty Cycle/PLL tab.
Channels, Duty Cycle Options (Factory Programmable) Actions Channel Channel Channel Channel Channel Channel other settings allowed Registers Register Actions
Channel Channel
Channel Interleaving Phase Options Actions Single Phase Dual Phase
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Check select duty cycle converter interleaving options. Note this will change current device settings.
current duty cycle converter interleaving settings displayed here after read config command Selected Ordering information will shown here. Will displayed after file saved reopened Figure Using select Factory programmable settings. Factory programmable settinings include minimum duty cycle, converter phase interleaving
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Register contains margin settings nominal setting setting corresponding that channel channel output adjusted stored margin high register. available writing volatile margin command register (R9C settings this range from 0-2.0V 9D), when non-volatile write operation carried increments. voltage VREF adjusted from NOTE: When write read operation performed, SMB120 must margining. will automatically adjust outputs there nominal points when write command issued. Registers Cannel Margin settings Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.008 volts Channel Nominal Point 2.000 volts
Figure Registers through control reference voltage margin settings. Registers through control reference voltages margin high settings. Registers through contain margin settings channels respectively. outputs adjusted writing volatile margin command register, when non-volatile write operation carried voltage COMP1 adjusted from nominal setting setting corresponding that
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stored margin high register. available settings this range from 0-1.0V channels NOTE: When write read operation performed, SMB120 must margining. will automatically adjust outputs there nominal points when write command issued.
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Registers Registers Channel Margin settings Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.004 volts Channel Nominal Point 1.000 volts
Channel Margin high settings Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.008 volts Channel Nominal Point 2.000 volts Channel Margin high settings Actions Channel Nominal Point 0.000 volts Channel Nominal Point 0.004 volts Channel Nominal Point 1.000 volts controlled initialized initialized then register will enable disable channel. setting this register depends current state register which determines initialized off.
Registers
Register volatile configuration register used enable disable outputs channels 0-7. When SMB120 normal sequencing mode outputs enabled disabled their respective enable signals. When enable signal Registers
Volatile Power Enable Actions Power (h13[7:6]=00) Enabled (h13[7:6]=01) Disabled Power (h13[7:6]=01) Enabled (h13[7:6]=00) Disabled Power (h13[5:4]=00) Enabled (h13[5:4]=01) Disabled Power (h13[5:4]=01) Enabled (h13[5:4]=00) Disabled Power (h13[3:2]=00) Enabled (h13[3:2]=01) Disabled Power (h13[3:2]=01) Enabled (h13[3:2]=00) Disabled Power (h13[1:0]=00) Enabled (h13[1:0]=01) Disabled Power (h13[1:0]=01) Enabled (h13[1:0]=00) Disabled Power (h12[7:6]=00) Enabled (h12[7:6]=01) Disabled Power (h12[7:6]=01) Enabled (h12[7:6]=00) Disabled Power (h12[5:4]=00) Enabled (h12[5:4]=01) Disabled Power (h12[5:4]=01) Enabled (h12[5:4]=00) Disabled Power (h12[3:2]=00) Enabled (h12[3:2]=01) Disabled Power (h12[3:2]=01) Enabled (h12[3:2]=00) Disabled Power (h12[1:0]=00) Enabled (h12[1:0]=01) Disabled Power (h12[1:0]=01) Enabled (h12[1:0]=00) Disabled
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Figure Register volatile register used enable disable output voltages when enable selected. Normal-sequencing mode, Enable disabled. Register initiates power on/off sequencing clears latched state POWER_FAIL pin. When SMB120 three power sequencing modes, sequenced write command this registers. When voltage VBATT dips below Register power control POWER_FAIL trip point power fail will become latched. latched condition automatically cleared dipping below nBATT_FAULT trip point surpassing DOCK_DC trip point then latch cleared writing volatile register.
Actions Power-ON Power-OFF Clear power fail
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Figure Register volatile register used commence Power sequencing operation, also contains setting used clear latched condition POWER_FAIL pin. Registers non-volatile read only registers that contain information about current state outputs. These registers read time they will tell user whether condition present monitored output Registers volatile 2-byte write Actions Channel Channel Channel Channel Channel Channel Channel Channel
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voltages. When supplies off, they will show under voltage condition because they below programmable threshold. When supplies within programmed range, settings will detected.
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Registers volatile 2-byte write Actions Channel Channel Channel Channel Channel Channel Channel Channel
Figure Registers volatile read only registers that contain current state outputs. Register volatile margin control register. When margin high margin operation selected, voltage COMP1 (channels 1-7) will changed reflect value stored margin high threshold register. channel voltage VREF will updated adjust output.
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Register Register Channel[4:7] Margin Control Register Actions Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal Channel[4:7] Margin Control Register Actions Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal Channel Margin High Channel Margin Channel Margin Nominal
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Figure Registers volatile registers used margin output voltages margin high margin voltages. NOTICE
SUMMIT Microelectronics, Inc. reserves right make changes products contained this publication order improve design, performance reliability. SUMMIT Microelectronics, Inc. assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained herein reflect representative operating parameters, vary depending upon user's specific application. While information this publication been carefully checked, SUMMIT Microelectronics, Inc. shall liable damages arising result error omission. SUMMIT Microelectronics, Inc. does recommend products life support aviation applications where failure malfunction product reasonably expected cause failure either system significantly affect their safety effectiveness. Products authorized such applications unless SUMMIT Microelectronics, Inc. receives written assurances, satisfaction, that: risk injury damage been minimized; user assumes such risks; potential liability SUMMIT Microelectronics, Inc. adequately protected under circumstances.
Revision This document supersedes previous versions. Please check Summit Microelectronics Inc. site http://www.summitmicro.com data sheet updates. Copyright 2006 SUMMIT MICROELECTRONICS, Inc. ADOC
PROGRAMMABLE POWER DIGITAL WORLD
registered trademarks Summit Microelectronics Inc., trademark Philips Corporation.
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