Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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AthlonX2 Dual-Core Processor Product Data Sheet
Compatible with Existing 32-Bit Code Base Including support SSE, SSE2, SSE3, MMXTM, 3DNow!technology legacy instructions Runs existing operating systems drivers Local APIC on-chip Power Management Multiple low-power states including System Management Mode (SMM) ACPI-compliant, including support processor performance states
AMD64 Technology AMD64 technology instruction extensions 64-bit integer registers, 48-bit virtual addresses, Socket Specific Features 40-bit physical addresses Eight additional 64-bit integer registers total) Eight additional 128-bit SSE/SSE2/SSE3 registers Refer Socket Processor Functional Data Sheet, order# 31117, functional total) mechanical details socket processors. Dual-Core Architecture Refer Family Processor Discrete cache structures each core Electrical Data Sheet, order# 31119, HyperTransportTechnology Devices electrical details socket processors. 16-bit link supporting speeds (2000 Electrical Interfaces MT/s) Gigabytes/s each direction HyperTransporttechnology: LVDS-like 64-Kbyte 2-Way Associative ECC-Protected differential, unidirectional Data Caches DDR2 SDRAM: SSTL_1.8 JEDEC 64-bit operations cycle, 3-cycle latency specification Clock, reset, test signals also DDR2 64-Kbyte 2-Way Associative Parity-Protected SDRAM-like electrical specifications Instruction Caches With advanced branch prediction 16-Way Associative ECC-Protected Caches Exclusive cache architecture-storage addition caches Mbyte cache Machine Check Architecture Includes hardware scrubbing major ECC-protected arrays Packaging Lidded micro grid array 1.27-mm pitch Compliant with RoHS Directive 2002/95/EC) with lead used only small amounts specifically exempted applications Integrated Memory Controller Low-latency, high-bandwidth 144-bit DDR2 SDRAM controller operating Supports four unbuffered DIMMs checking with double-bit detect single-bit correct
Publication Issue Date:
43042 2007
Revision:
3.00
Advanced Micro Devices
AthlonX2 Dual-Core Product Data Sheet
43042
Rev. 3.00
2007
Revision History
Date
2007
Revision
3.00
Description
Initial public release.
2007 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. information contained herein preliminary advance nature subject change without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, Arrow logo, Athlon combinations thereof, 3DNow! trademarks Advanced Micro Devices, Inc. HyperTransport licensed trademark HyperTransport Technology Consortium. trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.

Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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