Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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Athlon64 Dual-Core Processor Notebooks Product Data Sheet
Compatible with Existing 32-Bit Code Base Including support SSE, SSE2, SSE3, MMXTM, S1g1 Processor Specific Features 3DNow!technology, legacy instructions Runs existing operating systems drivers Refer S1g1 Processor Functional Data Local APIC chip Sheet, order# 31731, functional mechanical details S1g1 processors. Refer AMD64 Technology Family Processor AMD64 technology instruction extensions Electrical Data Sheet, order# 31119, 64-bit integer registers, 48-bit virtual addresses, electrical details S1g1 processors. 40-bit physical addresses Eight additional 64-bit integer registers total) Packaging 638-pin lidless micro package Eight additional 128-bit registers total) 1.27-mm pitch Dual-Core Architecture grid array Discrete cache structures each core organic substrate Enhanced Virus Protection Compliant with RoHS Directive 2002/95/EC) Execute (NX) page-translation tables with lead used only small amounts specifically specifies whether code executed from exempted applications page Integrated Memory Controller HyperTransportTechnology Devices Low-latency, high-bandwidth 16-bit link supporting speeds 128-bit DDR2 SDRAM controller operating (1600 MT/s) Gbytes/s each direction Supports unbuffered SO-DIMMs 64-Kbyte 2-Way Associative ECC-Protected Data Cache 64-bit operations cycle, 3-cycle latency 64-Kbyte 2-Way Associative Parity-Protected Instruction Cache With advanced branch prediction 16-Way Associative ECC-Protected Cache Exclusive cache architecture-storage addition caches Mbyte cache Mbyte 512-Kbyte options Machine Check Architecture Includes hardware scrubbing major ECC-protected arrays Electrical Interfaces HyperTransporttechnology: LVDS-like differential, unidirectional DDR2 SDRAM: SSTL_1.8 JEDEC specification Clock, reset, test signals also DDR2 SDRAM-like electrical specifications. Power Management Multiple low-power states including System Management Mode (SMM) ACPI compliant, including support processor performance states PowerNow!technology designed dynamically switch between multiple low-power states based application performance requirements.
Publication Issue Date:
42989 August 2007
Revision:
3.01
Advanced Micro Devices
Athlon64 Dual-Core Processor Notebooks Product Data Sheet
42989
Rev. 3.01 August 2007
Revision History
Date
August 2007
Revision
3.01
Description
Initial public release.
2007 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. information contained herein preliminary advance nature subject change without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, Arrow logo, Athlon combinations thereof, 3DNow!, PowerNow! trademarks Advanced Micro Devices, Inc. HyperTransport licensed trademark HyperTransport Technology Consortium. trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.

Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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