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This section provides information design transition, board design guidelines, Stratix device path delay issues. This section includes following chapter:
Chapter Transitioning APEX Designs Stratix Stratix Devices Chapter Stratix Board Design Guidelines Chapter Quartus Software Fitter Warnings
table below shows revision history Chapters through Chapter(s) Date Version
February 2005 v3.0
Changes Made
Added chapter Stratix Device Handbook.
February 2005 Added chapter Stratix Device Handbook. v1.0 March 2005 v1.0 Added chapter Stratix Device Handbook.
Altera Corporation
Section II-1 Preliminary
Design Guidelines
Stratix Device Handbook, Volume
Section II-2 Preliminary
Altera Corporation
Transitioning APEX Designs Stratix Stratix Devices
S52012-3.0
Introduction
Stratix® Stratix devices Altera's next-generation, system-ona-programmable-chip (SOPC) solution. Stratix Stratix devices simplify block-based design methodology bridge between system bandwidth requirements programmable logic performance. This chapter highlights features Stratix Stratix devices provides assistance when transitioning designs from APEXII APEX devices Stratix Stratix architecture. Designers using this chapter should familiar with APEX APEX architecture available device features. this chapter conjunction with Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume
General Architecture
Stratix Stratix devices offer many features architectural enhancements. Enhanced logic elements (LEs) MultiTrackinterconnect structure offer reduced resource utilization considerable design performance improvement. MultiTrack interconnect uses DirectDrivetechnology ensure availability deterministic routing resources design block, regardless placement within device. architectural changes between Stratix Stratix APEX APEX devices described this section require design changes. However, must resynthesize your design recompile Quartus® software target Stratix Stratix devices.
Altera Corporation February 2005
General Architecture
Logic Elements
Stratix Stratix device include several new, advanced features that improve design performance reduce logic resource consumption (see Table 3-1). Quartus software automatically uses these features improve device utilization.
Table 3-1. Stratix Stratix Features Feature Function Benefit
Conserves resources Register chain interconnects Direct path between register output Provides fast shift register register input adjacent within same logic array implementation Saves local interconnect routing block (LAB) resources within Look-up table (LUT) chain interconnects Direct path between combinatorial Allows LUTs within same output fast input cascade together high-speed wide adjacent within same fan-in functions, such wide operations Bypasses local interconnect faster performance Allows register output feed back into same such that register packed with fanout Uses implementing both adder subtractor Enhanced register packing mode Uses resources more efficiently
Register-to-LUT feedback path
Dynamic arithmetic mode
Improves performance functions that switch between addition subtraction frequently, such correlators
Carry-select chain
Calculates outputs possible carryGives immediate access result parallel both carry-in Increases speed carry functions high-speed operations, such counters, adders, comparators Supports direct asynchronous clear preset functions Conserves resources Does require additional logic resources implement NOT-gate push-back
Asynchronous clear asynchronous preset function
addition features described Table 3-1, there enhancements chains that connect together. Carry chains implemented vertically Stratix Stratix devices, instead horizontally APEX APEX devices, continue across rows, instead across columns, shown Figure 3-1. Also note that Stratix Stratix architectures support cascade primitive. Therefore, Quartus Compiler automatically converts
Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
cascade primitives APEX APEX designs wire primitive when compiled Stratix Stratix devices. These architectural changes transparent user require design changes. Figure 3-1. Carry Chain Implementation APEX APEX Devices Stratix Stratix Devices
APEX APEX Devices Stratix Devices
Carry Chains
Carry-Select Chains
LABs (with Each)
MultiTrack Interconnect
Stratix Stratix devices MultiTrack interconnect structure provide high-speed connection between logic resources using performance-optimized routing channels different lengths. This feature maximizes overall design performance placing critical paths routing lines with greater speed, resulting minimal propagation delay.
Altera Corporation February 2005
Stratix Device Handbook, Volume
General Architecture
Stratix Stratix device MultiTrack interconnect resources described Table 3-2.
Table 3-2. Stratix Stratix Device MultiTrack Interconnect Resources Routing Type
Column Column Column
Interconnect
Direct link
Span
Adjacent LABs and/or blocks Four units horizontally Eight units horizontally Horizontal routing across width device Four units vertically Eight units vertically Vertical routing across length device
Direct link routing saves routing resources while providing fast communication paths between resource blocks. Direct link interconnects allow LAB, digital signal processing (DSP) block, TriMatrixmemory block drive data into local interconnect left right neighbors. LABs, blocks, TriMatrix memory blocks also direct link interconnects drive data back into themselves feedback. Quartus software automatically uses these routing resources enhance design performance.
more information about architecture MultiTrack interconnect structure Stratix Stratix devices, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume
DirectDrive Technology
When using APEX devices, must place critical paths same MegaLABcolumn improve performance. Additionally, should place critical paths same MegaLAB structure optimal performance. However, this restriction does exist Stratix Stratix devices because they contain MegaLAB structures. With DirectDrivetechnology Stratix Stratix devices, actual distance between source destination path most important criteria meeting timing performance. DirectDrive technology ensures that same routing resources available each design block, regardless location device.
Stratix Device Handbook, Volume
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Transitioning APEX Designs Stratix Stratix Devices
Architectural Element Names
architectural element naming system within Stratix Stratix devices differs from row-column coordinate system (for example, LC1_A2, LAB_B1) used previous Altera device families. Stratix Stratix devices uses naming system based coordinate system, number designates location within block where logic resides, such within LAB. Because Stratix Stratix architectures column-based, this naming simplifies location assignments. Stratix Stratix architectural blocks include:
LAB: logic array block DSP: digital signal processing block DSPOUT: adder/subtractor/accumulator summation block block M512: 512-bit memory block M4K: 4-Kbit memory block M-RAM: 512-Kbit memory block
Elements within architectural blocks include:
logic element IOC: element PLL: phase-locked loop DSPMULT: block multiplier SERDESTX: transmitter serializer/deserializer SERDESRX: receiver serializer/deserializer
Altera Corporation February 2005
Stratix Device Handbook, Volume
General Architecture
Table highlights location syntax used Stratix Stratix devices.
Table 3-3. Stratix Stratix Location Assignment Syntax Architectural Elements
Blocks
Example Location Syntax Element Name Location Syntax Location
LAB, DSP, <element_name>_X<number> LAB_X1_Y1 DSPOUT, M512, _Y<number> M4K, M-RAM IOC, PLL, DSPMULT, SERDESTX, SERDESRX
pins <element_name>_X<number> LC_X1_Y1_N0 _Y<number>_N<number>
Description
Designates column Designates first located column
Logic
Pins
pin_<pin_label>
pin_5
Note Table 3-3:
make assignments pads using
following guidelines with naming system:
anchor point, origin, Stratix Stratix devices bottom-left corner, instead top-left corner APEX APEX devices. anchor point, origin, large block element (e.g., M-RAM block) also bottom-left corner. numbers zero-based, meaning origin bottom-left device pins constitute first last rows columns coordinates. Therefore, bottom pins resides X<number>, first left column pins resides Y<number>. sub-location elements, numbering begins top. Therefore, still numbered from bottom, start zero.
Figure show Stratix Stratix architectural element numbering convention. Figure displays floorplan view Quartus software.
Stratix Device Handbook, Volume
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Transitioning APEX Designs Stratix Stratix Devices
Figure 3-2. Stratix Stratix Architectural Elements Note
Blocks Units Wide Unit High
(1,18)
(11,18)
M512 (12,18)
(13,18)
(14,18)
(16,18)
Block (17,1) Units Wide Eight Units High
(1,17)
(11,17)
M512 (12,17)
(13,17)
(14,17)
(16,17)
(1,16)
(11,16)
M512 (12,16)
(13,16)
(14,16)
(16,16)
DSPMULT (17,7,0) (17,7,1)
(1,15)
(11,15)
M512 (12,15)
(13,15)
(14,15)
(16,15)
(14,14)
(16,14)
DSPMULT (17,5,0) (17,5,1)
(14,13) Mega Block Units Wide Units High
(16,13)
DSPOUT (18,1,0) (18,1,7)
Mega (1,2)
DSPMULT (17,3,0) (17,3,1)
Pins
(14,2)
(16,2) DSPMULT (17,1,0) (17,1,1)
(0,1,0)
(1,1)
(11,1)
M512 (12,1)
(13,1)
(14,1)
(16,1)
Origin
Notes Figure 3-2:
Figure shows part Stratix Stratix device. Large block elements their lower-left corner coordinate location. Stratix architectural elements include transceiver blocks right side device.
Altera Corporation February 2005
Stratix Device Handbook, Volume
TriMatrix Memory
Figure 3-3. Numbering Shown Quartus Software
TriMatrix Memory
TriMatrix memory three different sizes memory blocks, each optimized different purpose application. M512 blocks consist bits plus parity (576 bits), blocks consist bits plus parity (4,608 bits), M-RAM blocks consist 512K bits plus parity (589,824 bits). This structure differs from APEX APEX devices, which feature uniformly sized embedded system blocks (ESBs) either Kbits (APEX devices) Kbits (APEX devices) large. Stratix Stratix TriMatrix memory blocks give advanced control each memory block, with features such byte enables, parity storage, shift-register mode, well mixed-port width support true dual-port mode operation.
Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
Table compares TriMatrix memory with ESBs.
Table 3-4. Stratix Stratix TriMatrix Memory Blocks APEX APEX ESBs Stratix Stratix Features M512
Size (bits) Parity bits Byte enable True dual-port mode Embedded shift register Dedicated contentaddressable memory (CAM) support Pre-loadable initialization with .mif Packed mode Feed-through behavior Output power-up condition
APEX
4,608
APEX
2,048
M-RAM
589,824 4,096
Includes support Includes support Includes support mixed width mixed width mixed width
Rising edge Powers cleared even using .mif
Rising edge Powers cleared even using .mif
Rising edge Powers with unknown state
Falling edge Powers cleared initialized value, using .mif
Falling edge Powers cleared initialized value, using .mif
Notes Table 3-4:
.mif: Memory Initialization File. Packed mode refers combining single-port blocks into single block that placed into true dual-port mode.
Stratix Stratix TriMatrix memory blocks only support pipelined mode, while APEX APEX ESBs support both pipelined flow-through modes. Since TriMatrix memory blocks pipelined, input data address lines registered, while outputs either registered combinatorial. Stratix Stratix memory block registers implement input output registers without utilizing additional resources. compile designs containing pipelined memory blocks (inputs registered) Stratix Stratix devices without modifications. However, APEX
Altera Corporation February 2005
Stratix Device Handbook, Volume
TriMatrix Memory
APEX design contains flow-through memory, must modify memory modules target Stratix Stratix architectures (see "Memory Megafunctions" page 3-12 more information).
more information about TriMatrix memory converting flowthrough memory modules pipelined, TriMatrix Embedded Memory Blocks Stratix Stratix Devices chapter Stratix Device Handbook 210: Converting Memory from Asynchronous Synchronous Stratix Stratix Designs.
Same-Port Read-During-Write Mode
same-port read-during-write mode, block singleport, simple dual-port, true dual-port mode. port from block both reads writes same address location using same clock. When APEX APEX devices perform same-port readduring-write operation, data available falling edge clock cycle which written, shown Figure 3-4. When Stratix Stratix devices perform same-port read-during-write operation, data available rising edge same clock cycle which written, shown Figure 3-5. This holds true TriMatrix memory blocks. Figure 3-4. Falling Edge Feed-Through Behavior (APEX APEX Devices) Note
inclock data_in
wren
data_out
Note Figure 3-4:
Figures assume that address stays constant throughout that outputs registered.
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Transitioning APEX Designs Stratix Stratix Devices
Figure 3-5. Rising Edge Feed-Through Behavior (Stratix Stratix Devices) Note
inclock data_in
wren
data_out
Note Figure 3-5:
Figures assume that address stays constant throughout that outputs registered.
Mixed-Port Read-During-Write Mode
Mixed-port read-during-write mode occurs when block simple true dual-port mode port reading other port writing same address location using same clock. APEX APEX designs, outputs data first half clock cycle data second half clock cycle, indicated Figure 3-6. Figure 3-6. Mixed-Port Feed-Through Behavior (APEX APEX Devices) Note
inclock Port data_in Port wren Port wren Port data_out
Note Figure 3-6:
Figure assumes that outputs registered.
Stratix Stratix device outputs data rising edge clock cycle immediately after data written. When Stratix Stratix M512 blocks, choose whether output data targeted address output don't care value during clock cycle when data written. M-RAM blocks
Altera Corporation February 2005
3-11 Stratix Device Handbook, Volume
TriMatrix Memory
always output don't care value. Figures show feedthrough behavior mixed-port mode. altsyncram megafunction output behavior during mixed-port read-duringwrite mode. Figure 3-7. Mixed-Port Feed-Through Behavior (OLD_DATA) Note
inclock addressA addressB Port data_in Port wren Port wren Port data_out Address
Note Figure 3-7:
Figures assume that address stays constant throughout that outputs registered.
Figure 3-8. Mixed-Port Feed-Through Behavior (DONT_CARE) Note
inclock addressA addressB Port data_in Port wren Port wren Port data_out Unknown Address
Note Figure 3-8:
Figures assume that address stays constant throughout that outputs registered.
Memory Megafunctions
convert originally targeting APEX APEX architecture Stratix Stratix memory, specify Stratix Stratix target family MegaWizard Plug-In Manager. software
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updates memory module Stratix Stratix architecture instantiates synchronous memory megafunction, altsyncram, which supports both blocks Stratix Stratix architectures.
FIFO Conditions
First-in first-out (FIFO) functionality slightly different Stratix Stratix devices compared APEX APEX devices. Stratix Stratix devices support simultaneous reads writes from empty FIFO buffer. Also, Stratix Stratix devices support lpm_showahead parameter when targeting FIFO buffer because TriMatrix memory blocks synchronous. lpm_showahead parameter APEX APEX devices puts FIFO buffer "read-acknowledge" mode first data written into FIFO buffer immediately flows through output. Other than these differences, APEX APEX FIFO functions fully compatible with Stratix Stratix architectures.
Design Migration Mode Quartus Software
Quartus software features migration mode simplifying process converting APEX APEX memory functions Stratix Stratix architecture. design Stratix Stratix altsyncram megafunction replacement previous APEX APEX memory function while maintaining functionally similar behavior, Quartus software automatically converts memory. software produces warning message during compilation reminding verify that design migrated correctly. memory blocks with inputs registered, existing megafunction converted altsyncram megafunction. software generates warning when altsyncram megafunction incompatible. example, block with inputs registered except read enable compiles with warning message indicating that read-enable port registered. suppress warning messages entire project individual memory blocks setting parameter "on" global parameter selecting Assignment Organizer (Tools menu). Assignment Organizer window, click Parameters Assignment Categories box. Type Assignment Name type Assignment Setting box. suppress these warning messages per-memory-instance basis, parameter Assignment Organizer "on" memory instance.
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3-13 Stratix Device Handbook, Volume
TriMatrix Memory
functionality APEX APEX memory megafunction differs from altsyncram functionality least clock feeds memory megafunction, Quartus software converts APEX APEX memory megafunction Stratix Stratix altsyncram megafunction. This conversion useful initial evaluation design might perform Stratix Stratix devices should only used evaluation purposes. During this process, Quartus software generates warning that conversion functionally incorrect timing results accurate. Since functionality incorrect compilation only intended comparative purposes, Quartus software does generate programming file. functionally correct conversion requires manually instantiating altsyncram megafunction require additional design changes. previous memory function does have clock (fully asynchronous), fitting-evaluation conversion results error message during compilation does successfully convert design.
210: Converting Memory from Asynchronous Synchronous Stratix Stratix Designs more information. Table summarizes possible scenarios when using design migration mode resulting behavior Quartus software. most common cases where design-migration mode have difficulty converting existing design when:
port reading from address that being written another port (mixed-port read-during-write mode). both ports using same clock, read port Stratix Stratix devices data until next clock cycle, after data written.
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There differences power-up behavior between APEX APEX 20K, Stratix Stratix devices. should manually account these differences maintain desired operation system.
Table 3-5. Migration Mode Summary Memory Configuration
Single-port
Conditions
Possible Instantiated Megafunctions
altrom lpm_ram_dq lpm_ram_io lpm_rom
Quartus Warning Message(s)
Power-up differences.
Programming File Generated
inputs registered. altram
inputs registered. altdpram Multi-port (two-, three-, four-port lpm_ram_dp functions) altqpram
Power-up differences. Mixed-port read- duringwrite. Power-up differences. Mixed-port read- duringwrite. Read enable will registered.
alt3pram
Dual-port Read-enable ports unregistered. Other inputs registered.
altdpram lpm_ram_dp altqpram alt3pram altdpram lpm_ram_dp altqpram alt3pram altram lpm_ram_dq lpm_ram_io altram altrom altdpram altqpram alt3pram altdpram lpm_ram_dq lpm_ram_io lpm_rom lpm_ram_dp lpm_ram_dp
Dual-port
other unregistered port except read-enable ports. Clock available. least registered input. Clock available. clock.
Compile fitting- evaluation purposes.
Single-port
Compile fitting- evaluation purposes. Error conversion possible.
clock
Note Table 3-5:
parameter turned Quartus software does issue these warnings.
Altera Corporation February 2005
3-15 Stratix Device Handbook, Volume
Block
Block
Stratix Stratix device blocks outperform LE-based implementations common functions. Each block contains several multipliers that configured widths bits. Depending mode operation, these multipliers optionally feed adder/subtractor/accumulator summation unit. configure block's input registers efficiently implement shift registers serial input sharing, eliminating need external shift registers LEs. pipeline registers block accelerated operation. Registers available input output multiplier, output adder/subtractor/accumulator summation block. blocks have four modes operation:
Simple multiplier mode Multiply-accumulator mode Two-multipliers adder mode Four-multipliers adder mode
Associated megafunctions available Quartus software implement each mode block.
Block Megafunctions
lpm_mult megafunction configure block simple multiplier mode. lpm_mult Multiplier Implementation option MegaWizard Plug-In Manager either default implementation, ESBs, blocks. select Default option, compiler first attempts place multiplier blocks. However, under certain conditions, compiler implement multiplier LEs. placement depends factors such block resource consumption, width multiplier, whether operand constant, other options chosen megafunction. Stratix Stratix devices support ESBs option. select this option, Quartus software tries place multiplier unused blocks. recompile APEX APEX designs using lpm_mult megafunction Stratix Stratix devices Quartus software without changing megafunction. This makes converting lpm_mult megafunction designs Stratix Stratix devices straightforward.
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APEX APEX designs pipeline stages improve registered performance LE-based multipliers expense latency. However, need pipeline stages when targeting Stratix Stratix high-speed blocks. blocks offer three sets dedicated pipeline registers. Therefore, Altera recommends that reduce number pipeline stages three fewer implement them blocks. Additional pipeline stages implemented LEs, which latency without providing performance benefit. example, configure block 36-bit multiplication using lpm_mult megafunction. specify pipeline stages, software uses block input pipeline registers. specify three pipeline stages, software places third pipeline stage block output registers. This design yields same performance with three pipeline stages because critical path 36-bit operation within multiplier. With four more pipeline stages, device inefficiently uses resources additional pipeline stages. Therefore, multiplier modules APEX APEX designs converted Stratix Stratix designs require same number pipeline stages, surrounding circuitry must modified preserve original functionality design. design with multipliers feeding accumulator altmult_accum (MAC) megafunction block multiplyaccumulator mode. APEX APEX design already uses LEbased multipliers feeding accumulator, Quartus software does automatically instantiate altmult_accum (MAC) megafunction. Therefore, should MegaWizard Plug-In Manager instantiate altmult_accum (MAC) megafunction. also LeonardoSpectrumor Synplify synthesis tools, which have block inference support, instantiate megafunction. Designs that multipliers feeding into adders instantiate altmult_add megafunction configure blocks twomultipliers adder four-multipliers adder mode. also altmult_add megafunction stand-alone multipliers take advantage blocks features such dynamic sign control inputs input shift register connections. These features accessible through lpm_mult megafunction. your APEX APEX designs already multipliers feeding adder/subtractor, Quartus software does automatically infer altmult_add megafunction. Therefore, should step through MegaWizard Plug-In Manager instantiate altmult_add megafunction LeonardoSpectrum Synplify synthesis tools, which have block inference support.
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PLLs Clock Networks
Furthermore, altmult_add altmult_accum (MAC) megafunctions only available Stratix Stratix devices because these megafunctions target Stratix Stratix blocks, which available other device families. attempt these megafunctions designs that target other Altera device families, Quartus software reports error message. lpm_mult lpm_add_sub altaccumulate megafunction similar functionality other device families. third-party synthesis tool, able avoid megafunction conversion process. LeonardoSpectrum Synplify provide inference support lpm_mult, altmult_add, altmult_accum (MAC) blocks. your design does require implement multipliers blocks, must manually global parameter parameter each instance force tool implement lpm_mult megafunction LEs. Depending synthesis tools, inference blocks handled differently.
more information about using blocks Stratix Stratix devices, Blocks Stratix Stratix Devices chapter Stratix Device Handbook. Stratix Stratix devices provide exceptional clock management with hierarchical clock network four enhanced phase-locked loops (PLLs) eight fast PLLs versus four general-purpose PLLs four True-LVDSPLLs APEX devices. providing superior clock interfacing, numerous advanced clocking features, significant enhancements over APEX APEX PLLs, Stratix Stratix device PLLs increase system performance bandwidth.
PLLs Clock Networks
Clock Networks
There global clock networks available throughout each Stratix Stratix device well fast regional four regional clock networks device quadrant, resulting unique clock networks device. increased number dedicated clock resources available Stratix Stratix devices eliminate need general-purpose pins clock inputs. Stratix EP1S25 smaller devices have dedicated clock pins EP1S30 larger devices have four additional clock pins feed various clocking networks. comparison, APEX devices have eight dedicated clock pins APEX 20KE APEX 20KC devices have four dedicated clock pins.
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Transitioning APEX Designs Stratix Stratix Devices
dedicated clock pins Stratix Stratix devices feed clock inputs, global clock networks, regional clock networks. outputs internally-generated signals also drive global clock network. These global clocks available throughout entire device clock device resources. Stratix Stratix devices divided into four quadrants, each equipped with four regional clock networks. regional clock network either dedicated clock pins outputs within device quadrant. regional clock network only feed device resources within particular device quadrant. Each Stratix Stratix device provides eight dedicated fast clock pins FCLK[7.0] versus four dedicated fast pins APEX APEX devices. fast regional clock network these dedicated FCLK[7.0] pins interconnect. interconnect allows internal logic drive fast regional clock network. fast regional clock network available generalpurpose clocking well high fan-out control signals such clear, preset, enable, TRDY IRDY applications, bidirectional output pins. EP1S25 smaller devices have eight fast regional clock networks, device quadrant. quadrants EP1S30 larger devices divided half, each half-quadrant clocked eight fast regional networks. Additionally, each fast regional clock network drive neighboring half-quadrant (within same device quadrant).
PLLs
Table highlights Stratix Stratix enhancements existing APEX APEX 20KE APEX 20KC features.
Table 3-6. Stratix Stratix APEX APEX 20KE APEX 20KC Features (Part Stratix Stratix Feature Enhanced PLLs
Number PLLs (EP1S30 smaller devices); four (EP1S40 larger devices)
APEX PLLs Fast PLLs
Four (EP1S25 Four generalpurpose PLLs smaller devices); four LVDS PLLs eight (EP1S30 larger devices) (10)
APEX 20KE APEX 20KC PLLs
four generalpurpose PLLs. LVDS PLLs.
Minimum input frequency Maximum input frequency
644.5 (11)
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PLLs Clock Networks
Table 3-6. Stratix Stratix APEX APEX 20KE APEX 20KC Features (Part Stratix Stratix Feature Enhanced PLLs
Internal clock outputs External clock outputs Four differential/eight singled-ended single-ended Down 160-ps increments
APEX PLLs Fast PLLs
APEX 20KE APEX 20KC PLLs
Phase Shift Time shift counter values counter values clock input sharing T1/E1 rate conversion Notes Table 3-6:
Down 125-ps increments
500-ps 1-ns resolution
0.4- 1-ns resolution
250-ps increments
EP20K200E smaller devices only have general-purpose PLLs. EP20K400E larger devices have LVDS PLLs four general-purpose PLLs. more information, 115: Using ClockLock ClockBoost Features APEX Devices. maximum input frequency Stratix Stratix enhanced PLLs depends standard used with that input clock pin. more information, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook. Fast PLLs have three internal clock output ports PLL. Fast PLLs have internal clock output ports PLL. Every Stratix device enhanced PLLs with eight single-ended four differential outputs each. additional enhanced PLLs EP1S80, EP1S60, EP1S40 devices each have single-ended output. driven fast global regional outputs external clock output pin. smallest phase shift unit determined voltage-controlled oscillator (VCO) period divided There maximum between clock outputs. clock frequency 1.544 clock frequency 2.048 MHz, which violates minimum clock input frequency requirement Stratix PLL. Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX40 contains four. (10) Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX40 contains four. (11) Stratix supports clock rates Gbps using DPA.
Enhanced PLLs
Stratix Stratix devices provide four enhanced PLLs with advanced features. addition feature changes mentioned Table 3-6, Stratix Stratix device PLLs include many new,
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advanced features improve system timing management performance. Table shows some features available Stratix Stratix enhanced PLLs.
Table 3-7. Stratix Stratix Enhanced Features Feature
clock outputs feed logic array locked output feed logic array Multiplication allowed zero-delay buffer mode external feedback mode Programmable phase shift allowed zero-delay buffer mode external feedback mode Phase frequency detector (PFD) disable Clock output disable Programmable lock detect gated lock Dynamic clock switchover reconfiguration Programmable bandwidth Spread spectrum Notes Table 3-7:
These features also available fast PLLs. addition delay chains each counter, specify programmable phase shift each output fine coarse levels. Each clock output associated clock enable signal. used external feedback mode, will need relock.
Description
Allows clock outputs feed data ports registers combinatorial logic. Allows locked port feed data ports registers combinatorial logic. clock outputs multiplied divided down ratio input clock. clock outputs phase shifted. phase shift relative clock output.
Programmable duty cycle Allows variable duty cycle each clock output.
Allows operate last control voltage frequency with some long term drift. maintains lock with output clocks disabled. Holds lock signal programmable number input clock cycles. Enables switch between reference input clocks, either clock redundancy dual-clock domain applications. Allows counters delay elements within reconfigured realtime without reloading programmer object file (.pof). Provides advanced control bandwidth using programmable control loop characteristics. Modulates target frequency over frequency range reduce electromagnetic interference (EMI) emissions.
Fast PLLs
Stratix Stratix fast PLLs similar APEX True-LVDS PLLs that setting, which governs relationship between clock input data rate, setting, which controls width
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PLLs Clock Networks
high-speed differential data bus, have equal. Additionally, Stratix Stratix fast PLLs offer three clock outputs, multiplied high-speed clocks drive serializer/deserializer (SERDES) block and/or external pin, low-speed clock drive logic array. fast PLLs both high-speed interfacing general-purpose applications. Table shows differences between Stratix Stratix fast PLLs APEX APEX True-LVDS PLLs.
Table 3-8. Stratix Stratix Fast APEX APEX True-LVDS Feature
Number fast PLLs TrueLVDS PLLs
Stratix Stratix
Four (EP1S25 smaller devices) fast PLLs Eight (EP1S30 larger devices) fast PLLs
APEX
Four True-LVDS PLLs
APEX 20KE APEX 20KC
True-LVDS PLLs
Number channels transmitter/receiver block frequency Minimum input frequency Minimum input frequency Notes Table 3-8:
1GHz
also Stratix Stratix device fast PLLs general-purpose applications. EP20K400E larger devices have True-LVDS PLLs. APEX 20KE APEX 20KC devices, Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX10 contains four. Stratix supports frequency range 300-1000 (using DPA).
Stratix Stratix fast frequency range MHz, APEX True-LVDS frequency range GHz. Therefore, must update designs that data rate less than megabits second (Mbps) enhanced PLLs M512 blocks SERDES bypass mode. Additionally, must update designs that data rate faster than Mbps.
altpll Megafunction
Altera recommends that replace instances altclklock megafunction with altpll megafunction take advantage Stratix Stratix features. Although most cases retarget your APEX APEX design Stratix Stratix
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device with altclklock megafunction, there specific cases where must altpll megafunction, explained this section. MegaWizard Plug-In Manager, select altpll megafunction directory from Available Megafunctions (see Figure 3-9). altclklock megafunction also available from Quartus software backward compatibility, instantiates altpll megafunction when targeting Stratix Stratix devices. Quartus Compiler automatically selects whether altpll module uses either enhanced fast based design's needs feature requirements each PLL. Figure 3-9. altpll Megafunction Selection MegaWizard Plug-In Manager
compile APEX APEX 20KE, APEX 20KC designs using altclklock megafunction normal mode Stratix Stratix devices without updating megafunction. However, should replace altclklock megafunction with altpll megafunction. Quartus software cannot implement requested clock multiplication division PLL, compiler reports error message with appropriate reason stated.
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PLLs Clock Networks
APEX APEX 20KE, APEX 20KC devices have only external clock output available PLL. Therefore, when retargeting APEX APEX 20KE, APEX 20KC design that uses PLLs zero delay buffer mode external feedback mode Stratix Stratix device, should replace instances altclklock megafunction. APEX APEX 20KE, APEX 20KC altclklock module only uses clock output (internal external) compiled target Stratix Stratix device, design compiles successfully with warning that design uses Stratix Stratix external clock output, extclk0. However, APEX APEX 20KE, APEX 20KC more than clock output, must replace instances altclklock megafunction with altpll megafunction because Quartus Compiler does know which clock output external output back Stratix Stratix device fbin pin. example, APEX APEX 20KE, APEX 20KC design with altclklock megafunction uses clock0 output port feed external clock output clock1 output port feed internal logic array, Quartus software generates error during compilation must MegaWizard Plug-In Manager instantiate altpll megafunction. using altpll megafunction, choose which four external clock outputs take advantage Stratix Stratix features available zero delay buffer mode external feedback mode.
Timing Analysis
When Quartus software performs timing analysis APEX APEX 20KE, APEX 20KC designs, clock settings override project clock settings. However, during timing analysis Stratix Stratix designs using PLLs, project clock settings override input clock frequency duty cycle settings. MegaWizard Plug-In Manager does project clock settings determine altpll parameters. This saves time with designs that features such clock switchover reconfiguration because Quartus software perform timing analysis without recompiling design. important note following:
warning during compilation reports that project clock settings overrides clock settings. project clock setting overrides clock settings timingdriven compilation. compiler will check lock frequency range PLL. frequency specified project clock settings outside lock frequency range, clock settings will overridden. Performing timing analysis without recompiling your design does change programming files. must recompile your design update programming files.
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Default Required fMAX setting does override clock settings. Only individual clock settings override clock settings.
Therefore, enter different project clock settings corresponding settings accelerate timing analysis eliminating full compilation cycle.
more information about using Stratix Stratix PLLs, General-Purpose PLLs Stratix Stratix Devices chapter. Stratix Stratix element (IOE) architecture similar APEX architecture, with total registers latch each IOE. registers organized three sets: output registers drive single double-data rate (DDR) output path, input registers latch support single input path, output enable registers enhance clock-to-output enable timing SDRAM interfacing. synchronous reset signal available each three sets registers preset clear, neither. addition advanced architecture, Stratix Stratix features dedicated circuitry external interfacing, standards, differential on-chip termination, high-speed differential standard support.
Structure
External Interfacing
advanced Stratix Stratix architecture includes dedicated circuitry interface with external RAM. This circuitry provides enhanced support external high-speed memory devices such SDRAM FCRAM. SDRAM interface uses bidirectional signal, DQS, clock data, both transmitting receiving device. Stratix Stratix devices transmit signal with data signals minimize clock data skew. Stratix Stratix devices include groups programmable pins, bottom banks device. Each group consists that supports fixed number pins. number pins depends mode. When using external interfacing circuitry, drives dedicated clock network that feeds pins residing that bank. Stratix Stratix programmable delay chains that phase shift signal ensure data sampled appropriate point time. Therefore, Stratix Stratix devices make full IOEs, remove need build input data path logic array. make these assignments Quartus Assignment Organizer.
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Structure
more information external interfacing, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet Stratix Device Family Handbook.
Standard Support
Stratix Stratix devices support standards that APEX APEX devices support, including high-speed differential standards such LVDS, LVPECL, PCML, HyperTransporttechnology, differential HSTL input output clocks, differential SSTL output clocks. Stratix Stratix devices also introduce support SSTL-18 class Similar APEX devices, Stratix Stratix devices only support certain standards designated banks. addition, vref pins dedicated pins Stratix Stratix devices support input pins.
more information about standard support Stratix Stratix devices, Selectable Standards Stratix Stratix Devices chapter.
High-Speed Differential Standards
Stratix Stratix devices support high-speed differential interfaces speeds Mbps using high-speed PLLs that drive dedicated clock network SERDES. Each fast drive highspeed channels. Stratix Stratix devices enhanced PLLs M512 blocks provide Mbps performance SERDES bypass clock interfacing. There restriction number channels that clocked using this scenario. Stratix Stratix devices have different number differential channels than APEX devices. Tables 3-10 highlight number differential channels supported Stratix Stratix devices.
Table 3-9. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1S10
Count
Number Receiver Channels
Number Transmitter Channels
EP1S20
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Table 3-9. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1S25
Count
1,020
Number Receiver Channels
Number Transmitter Channels
EP1S30
1,020
EP1S40
1,020
1,508
EP1S60
1,020
1,508
EP1S80
1,508
Note Table 3-9:
information channel speeds, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Differential Interfaces chapter Stratix Device Handbook, Volume
Table 3-10. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1SGX10 EP1SGX10
Count
Number Transceivers
Number SourceSynchronous Channels
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Structure
Table 3-10. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1SGX25 EP1SGX25 EP1SGX25 EP1SGX40 EP1SGX40 Note Table 3-10:
information channel speeds, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Source-Synchronous Differential Interfaces Stratix Devices chapter Stratix Device Handbook, Volume
Count
672/1,020 1,020 1,020 1,020
Number Transceivers
Number SourceSynchronous Channels
differential within Stratix also provides dynamic phase alignment (DPA). enables differential operate Gbps channel. automatically continuously tracks fluctuations caused system variations self-adjusts eliminate phase skew between multiplied clock serial data. block contains dynamic phase selector phase detection selection, SERDES, synchronizer, data realigner circuit. bypass dynamic phase aligner without affecting basic source-synchronous operation channel using separate deserializer. compile APEX LVDS design that uses clock-data synchronization (CDS) Stratix Stratix device, Quartus software issues warning during compilation that Stratix Stratix devices support CDS. Stratix Stratix devices offer flexible solution using byte realignment circuitry correct byte misalignment shifting, slipping, data bits. Stratix Stratix devices activate byte realignment circuitry when external (rx_data_align) internal custom-made state machine asserts SYNC node high. APEX APEX 20KE, APEX 20KCdevices have dedicated transmitter clock output (LVDSTXOUTCLK). Stratix Stratix devices, transmitter dataout channel with LVDS clock (fast clock) generates transmitter clock output. Therefore, drive channel output clock pin, just dedicated clock output pins. This solution offers better versatility address various applications that require more complex clocking schemes.
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more information differential support, data realignment, transmitter clock output Stratix Stratix devices, High-Speed Differential Interfaces Stratix Devices chapter.
altlvds Megafunction
take full advantage high-speed differential standards available Stratix Stratix devices, should update each instance altlvds megafunction APEX APEX 20KE, APEX 20KC designs. MegaWizard Plug-In Manager, choose altlvds megafunction, select Stratix Stratix target device family, update megafunction, recompile your design. altlvds megafunction supports Stratix Stratix parameters that available APEX APEX 20KE, APEX 20KC devices. Tables 3-11 3-12 describe parameters LVDS receiver LVDS transmitter, respectively.
Table 3-11. altlvds Parameters Stratix LVDS Receiver Note Parameter
input_data_rate inclock_data_alignment rx_data_align
Function
Specifies data rate Mbps. This parameter replaces multiplication factor Indicates alignment rx_inclk rx_in data. Drives data alignment port fast enables byte realignment circuitry.
registered_data_align_input Registers rx_data_align input port clocked rx_outclock. common_rx_tx_pll
Indicates fast shared between receiver transmitter applications.
Table 3-12. altlvds Parameters Stratix LVDS Transmitter (Part Note Parameter
output_data_rate inclock_data_alignment outclock_alignment registered_input
Function
Specifies data rate Mbps. This parameter replaces multiplication factor Indicates alignment tx_inclk tx_in data. Specifies alignment tx_outclock tx_out data. Specifies clock source input synchronization registers, which either tx_inclock tx_coreclock. Used only when Registered Inputs option selected.
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Configuration
Table 3-12. altlvds Parameters Stratix LVDS Transmitter (Part Note Parameter
common_rx_tx_pll
Notes Tables 3-11 3-12:
specify these parameters MegaWizard Plug-In Manager. must specify data rate MegaWizard Plug-In Manager instead factor. same fast used clock both receiver transmitter only both running same frequency.
Function
Indicates fast shared between receiver transmitter applications.
Above standard offered APEX APEX 20K, Stratix devices, Stratix devices provide 3.175 Gbps transceivers. transceivers provide high-speed serial links chip-to-chip, backplane, line-side connectivity support number emerging high-speed protocols. find more information Stratix Family Data Sheet Stratix Family Handbook, Volume
Configuration
Stratix Stratix devices supports current configuration schemes, including enhanced configuration devices, passive serial (PS), passive parallel asynchronous (PPA), fast passive parallel (FPP), JTAG. Stratix Stratix devices also provide number configuration enhancements that take advantage when migrating APEX APEX designs Stratix Stratix devices.
Configuration Speed Schemes
configure Stratix Stratix devices maximum clock speed MHz, which faster than 66-MHz 33-MHz maximum configuration speeds APEX APEX devices, respectively. Similar APEX devices, 8-bit parallel data configure Stratix Stratix devices (the target device receive byte-wide configuration data each clock cycle) significantly speeding configuration times. select configuration scheme based MSEL pins driven. Stratix Stratix devices have three MSEL pins (APEX APEX devices have MSEL pins) determining configuration scheme.
more information about Stratix Stratix configuration schemes, Configuring Stratix Stratix Devices chapter.
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Remote Update Configuration
APEX device family introduced concept remote update configuration, where could send APEX device configuration files from remote source device would store files flash memory reconfigure itself with configuration data. Stratix Stratix devices enhance support remote update configuration with new, dedicated circuitry handle recover from errors. error occurs either during device configuration user mode, this circuitry reconfigures Stratix Stratix device known state. Additionally, Stratix Stratix devices have user watchdog timer ensure application configuration data executes successfully during user mode. User logic must continually reset this watchdog timer order validate that application configuration data functioning properly.
more information about remote local update modes, Remote System Configuration with Stratix Stratix Devices chapter.
JTAG Instruction Support
Stratix Stratix devices support JTAG instructions, PULSE_NCONFIG CONFIG_IO. PULSE_NCONFIG instruction emulates pulsing nCONFIG signal trigger reconfiguration, while actual nCONFIG device unaffected. CONFIG_IO instruction allows JTAG chain configure standards pins. Because this instruction interrupts device configuration, should reconfigure Stratix Stratix device after finish JTAG testing ensure proper device operation. Table 3-13 compares JTAG instruction support Stratix Stratix devices versus APEX APEX devices. further information about supported JTAG instructions, appropriate device family data sheet.
Table 3-13. JTAG Instruction Support (Part JTAG Instruction
SAMPLE/PRELOAD EXTEST BYPASS USERCODE IDCODE Instructions
Stratix
APEX
APEX
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Conclusion
Table 3-13. JTAG Instruction Support (Part JTAG Instruction
SignalTapII Instructions HIGHZ CLAMP PULSE_NCONFIG CONFIG_IO
Stratix
APEX
APEX
Conclusion
Stratix Stratix devices extend advanced features available APEX APEX device families deliver complete system-on-a-programmable-chip (SOPC) solution. following these guidelines, easily transition current APEX APEX designs take advantage features available Stratix Stratix devices.
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Stratix Board Design Guidelines
SGX53001-1.0
Introduction
Digital board design become more complicated over years. Devices have 0.13-m gate lengths powered 1.5-V power supplies. While trend toward miniaturization continues, device speeds increasing. FPGAs have embedded transceivers that support serial data transmission 3.125 Gigabits second (Gbps). low-voltage supply results decreased noise margin; therefore, small voltage noise board cause flip. Similarly, voltage noise directly increases clock jitter, which reduces timing margin. jitter large enough, transition boundaries become fuzzy, current data could confused past future bit. reduce voltage timing noise ensure error-free data transmission, good design techniques essential. following things critical when designing successful high-speed digital board:
Clean power supply design (see "Power Circuitry" page 4-6) Decoupling capacitor selection (see "Decoupling Circuitry Design" page 4-13) Analog ground power isolation (see "Ground Plane Island Design" page 4-30) Transmission line termination (see "Transmission Line Termination" page 4-52) Crosstalk minimization (see "Crosstalk" page 4-72) Impedance discontinuity minimization (see "Transmission Line Routing" page 4-58) Proper differential signal routing (see "Transmission Line Routing" page 4-58)
This document explains high-speed board design concepts techniques applied Stratix® devices explains major aspects successful high-speed board design. Stratix device Stratix development board used platforms tests measurements described this document. Topics covered include clock circuitry design, power circuitry design, power supply decoupling, transmission line topologies, length matching, versus coupling, termination techniques, time domain reflectometer (TDR) usage, Sparameters.
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Introduction
Board Design Overview
typical high-speed board design begins with product requirements document, concept review, functional specification. After specification finalized, actual system design begins with selection components. this point, timing analysis interfaces power analysis-to determine power requirements-is performed. Based power analysis, power supply modules regulators chosen, decoupling scheme specified. Based timing analysis, length-matching criteria buses established. Upon completion these tasks, well completion system design selection remaining components, schematics created. These typically reviewed among engineers make necessary changes, after which they given layout designer. layout guidelines document, which specifies place components board route traces, created given layout designer well. pre-layout simulation performed determine ideal stackup, trace widths, spacing, other routing requirements. changes schematic, based simulation results, incorporated schematic provided layout designer. When layout complete, post-layout simulation performed critical sections board ensure that there major signal integrity problems. Based results post-layout simulation, changes required incorporated into layout, finally layout released fabrication house board manufacturing. Figure shows typical board design process.
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Figure 4-1. Simplified View Typical High-Speed Board Design Process
Product Requirements
Function Specifications Document Created
System Design Begins
Components Specified Selected
Schematic Finalized
Post-Layout Simulation Performed
Layout Design
Simulation Results Positive?
Pre-Layout Simulation Performed
Simulation Results Positive?
Schematic/ System Design Problem?
Board Parameters and/or Stackup Adjusted
Board Handed-Off House
House Manufactures Boards
Board Sent Back House Problems
Bare Board Inspection Pass?
Board goes Assembly
Board Sent Back Assembly House Problems
Problem Assembly?
Assembled Board Tested Engineer
Does Board Work?
Problem Fab/ Assembly?
Design Complete Characterization Follows
Support Circuitry Design
Support circuitry includes clocks, power, decoupling. This section contains detailed guidelines designing these parts high-speed board.
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Support Circuitry Design
Clock Circuitry
Clocks serve references digital signals must designed very carefully. noise clock signal reduces timing margin digital signals. Typically, on-board clocks derived from crystal-based oscillators. Stratix development board, Altera standard 3.3-V SM7745DV series CMOS crystals from Pletronics highfrequency applications. This crystal stability less than jitter from from carrier. lowfrequency applications Altera uses standard SM7745HV series CMOS crystals from Pletronics. stability this crystal ppm, jitter specified. Altera recommends these equivalent crystals. maximum noise immunity, crystal oscillator's CMOS output typically needs converted differential standard like LVDS before Stratix device. ICS8545 CMOS LVDS buffer from Integrated Circuit Systems, Inc. achieves this conversion. side benefit using clock buffer like this that provides multiple outputs. This feature very helpful because clock lines need have source destination best signal integrity. Other things remember optimal clock performance are:
Place crystal oscillator close driver circuitry best jitter performance. Route differential clock lines tightly coupled each other. oscillators drivers need clean power supplies. Place series termination clock output trace long. Place parallel differential termination close receiver pins.
Whether particular trace long depends edge rate clock speed which signal propagates board. electrical length trace small (1/10 10%)1 compared rise time, then termination needed. Otherwise, series termination. propagation speed microstrip stripline, commonly used transmission line topologies, shown following equations2:
Speed Microstrip
inches 0.475 0.67
Some designers
cut-off point. important thing remember that length needs small. Refer High-Speed Digital Design: Handbook Black Magic Johnson Graham, pp186-188.
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Stratix Board Design Guidelines
Speed Stripline)
inches
Using typical FR-4 material, propagation speed microstrip stripline traces works 0.007021 inches/ps 0.005546 inches/ps, respectively. Expressed another way, signals travel ps/inch microstrip traces ps/inch stripline traces. Case Study: case study, microstrip trace length from output 156.25 crystal driver (see Figure 4-2) about 0.28 Stratix development board. signal takes 0.28 39.76 traverse this distance. rise time crystal output (see Pletronics SM7745HV data sheet). signal transit time less than signal rise time, termination needed. When clock being brought board through connector (J104), trace length from clock driver about four times crystal transit time calculated earlier, addition cable length. this case, termination definitely needed. R176 termination, shown Figure 4-2. Figure 4-2. Layout Example Clock Distribution
LVTTL LVDS driver Termination resistor clock trace XTAL Output (Short trace, termination required)
XTAL Trace from clock input (Long trace, termination required)
XTAL_CLK1 Input
specifications some standards always require termination regardless trace length. These include PCML, LVDS, LVPECL, SSTL-II, HSTL-II.
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Support Circuitry Design
Isolated Power Ground Plane Design
Isolated power ground planes created using ferrite beads. ferrite bead acts short presents impedance passage high-frequency noise. beneficial systems that have lots switching noise. Sources switching noise include switching power supplies simultaneous switching outputs. Stratix devices, Altera recommends isolating high-speed ground (GND_GXB) from digital ground (GND), that noise from digital ground does reach high-speed circuitry. Stratix development board, there three ground planes: GND, GND_PLL, GND_GXB, characterization purposes. most high-density designs, Altera recommends only ground planes: GND_GXB. board does have lots switching circuitry otherwise cleanly designed, ground plane acceptable. Currently, benefits split power planes transceiver quads under evaluation. Preliminary tests suggest that most cases benefits isolating power quads minimal. "Power Plane Island Design" "Ground Plane Island Design" more information.
Power Circuitry
gate lengths shrink, power supply voltages transistors also decrease. result, noise margin also decreases. reduced noise margin makes transistors even more sensitive noise power supply. features board must understood before power supply designed. Some characteristics high-density board with more FPGAs include:
Hundreds pins with varying voltage standards switching several frequencies. core highly unpredictable depends actual design loaded. user could load design that uses close 100% LEs, embedded memory, hard logic (like transceivers), everything full speed. Analog digital signals board. example, switching. digital while Stratix transceiver outputs analog signals. potential noise couple between different power ground planes.
Regulator Selection
Altera recommends selecting linear regulators much possible, because they easy design their performance less critical layout. must sometimes select switching regulators, because linear
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Stratix Board Design Guidelines
regulators cannot supply desired amount power efficiently. those cases, must design layout switching regulators very carefully. major switching components traces must closely contained same layer. Stratix development board uses Fairchild FAN5066 switching regulators (U36 U37) 3.3-V 1.5-V digital supplies. Refer "Switching Regulator Layout Example" page details layout these regulators Stratix development board. support board with characteristics listed earlier, power circuitry must able following:
Supply large amounts current core voltages. Supply clean power ground sensitive analog components such PLLs transceivers. Maintain good efficiency prevent excess heat dissipation regulators.
Voltage regulators come forms: linear switching. Linear regulators easy design provide very clean output voltage, often they cannot provide large amounts current without getting very hot. Switching regulators provide large amounts currents (over with good efficiency, there need heat sink. Switching regulators require very good design layout practices achieve good noise performance. switching regulator core supply, because current draw core high, linear regulators cannot supply necessary current without requiring large heat sink. example, core current needs input output voltages linear regulator 3.3/1.5 volts, heat dissipation would approximately (3.3 1.5) Watts. This much heat requires large heat sink linear regulator, which possible board because form factors, costs, aesthetics. sensitive circuitry such phase-locked loops (PLLs), transceivers, double-data rate (DDR) memory, linear regulators preferred. Choose linear regulator based current requirements. Sometimes small heat sink required, depending current being drawn from regulator voltage drop from input output. Refer 185: Thermal Management Using Heat Sinks more details regulator heat sink selection. there hundreds LVTTL signals I/O, which potentially switch same time, switching regulator necessary, because current requirement several Amperes.
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Switching Regulator Layout Example
Linear regulators relatively easy design out. Switching regulators, other hand, require great deal care. Typically schematics both linear switching regulators taken directly from vendor data sheet application note. Some linear regulators Altera recommends include Micrel MIC29502BU, National LMS1585 National LP2995M. Similarly, Altera used Fairchild FAN5066 switching regulators with good results. With switching regulators, component layout extremely important. explain this point further, consider actual example. Figure shows capture plot FAN5066 circuit from Stratix development board. This switching regulator runs from 5.0-V supply generate output voltage that equals voltage reference. reference voltage board applying required voltage CNTRL (pin 16). 12.0-V supply used only biasing draws very little current. overall circuitry consists FAN5066 switching controller, external FETs boost current output capability, associated resistors, diodes, inductors, capacitors recommended manufacturer. switching regulator essentially feedback loop consisting pulse width modulator (PWM). feedback loop compares actual output voltage desired voltage (reference voltage). actual output less than desired, then high drive (HIDRV) output asserted, which turns upper field effect transistor (FET) charges output capacitor (C73). result that output voltage climbs. actual output more than desired, drive (LODRV) output asserted, which turns lower discharges output capacitor (C73). result that output voltage drops. steady state output voltage equals input reference voltage. Figure shows schematic switching regulator used development board.
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Figure 4-3. Switching Regulator Schematic
Make This Trace Short Possible
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Support Circuitry Design
Figure 4-4. Switching Regulator Layout
Output Capacitor (C73) DC-DC Driver 5066 (U37)
Output Inductor (L37)
Lower (Q4)
Upper (Q3)
Input Capacitor (C57)
Figures through show waveforms gates upper lower FET. While lower switches from about upper switches from approximately These large magnitudes board with 3.3-, 2.5-, 1.5-volt logic signals. Routing fast switching signals close sensitive analog digital signals across multiple layers cause switching signals radiate energy other critical traces. Consequently, very important contain large switching signals compactly same layer.
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Stratix Board Design Guidelines
Figure 4-5. Switching Waveforms Output
Figure 4-6. Switching Waveforms Gate Upper
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Figure 4-7. Switching Waveforms Gate Lower
Altera compared performance improvement output ripple when using good layout versus poor layout. results excessive ripple output switching regulator because poor board layout, shown Figure 4-8. output ripple almost peak peak. This example extreme case, board this example designed with intentionally poor layout. layout later improved reducing length HIDRV LODRV signals minimizing count determine much improvement would result. With improved layout, noise decreased about peak peak.
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Stratix Board Design Guidelines
Figure 4-8. Excessive Ripple Output Switching Regulator
Altera recommends that follow switching regulator layout Stratix development board review Fairchild Semiconductor FAN5066 data sheet detail. guidelines summarized here:
Place components same layer, possible. Minimize trace lengths gate drives (HIDRV LODRV). Place decoupling capacitors close pins. Place HIDRV, LODRV, VCCQP output traces away from analog sections chip, including VCNTRL (pin 16), VFB, (feedback pins CEXT (pin routing switching signals (VCCQP, HIDRV, LODRV, output) component layer avoid radiation multiple layers through vias. Surround capacitor connected (CEXT) with ground guard trace place ground plane beneath
Decoupling Circuitry Design
divide decoupling capacitor circuitry into categories: bulk decoupling local decoupling. Bulk decoupling uses large decoupling capacitors (often tens hundreds microfarads), usually placed close regulators designed work frequencies. Local decoupling involves smaller capacitors (typically 0.01 that placed close chips designed decouple high frequency noise from power supply.
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Determining number decoupling capacitors depends expected current draw from power supply, rate current change, desired impedance between power plane ground plane frequency interest. switching sometimes even linear) regulators, manufacturers specify certain minimum bulk decoupling output regulator stability ensuring clean output.
Bulk Decoupling
amount bulk decoupling needed depends number outputs switching, load capacitance, slew rate, inductance planes routing traces vias. Estimate amount bulk decoupling needed follows: Determine worst case current draw power net. This draw depends many gates switch same time much load they need drive. example, assume there 3.3-V LVTTL pins switching, each with 11.5 loads, switch completed (These values fairly typical Stratix Stratix devices.) total worst case current required
3.3V Amps
Determine maximum noise margin degradation allowed logic circuit. This value depends standard being used. LVTTL, threshold shown Table 4-1. noise margin between margin between 0.45 0.25 Therefore, worst case noise margin 0.25 absolute maximum value noise allowed power supply while still guaranteeing successful data transfer. good design allows safety margin, this example specifies maximum value noise permitted. Call this parameter
Table 4-1. LVTTL Parameters (Part Symbol
Parameter
Output supply voltage High-level input voltage
Conditions
Minimum Maximum Units
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Table 4-1. LVTTL Parameters (Part Symbol
Parameter
Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum Maximum Units
-0.5 0.45
Using from step from step determine maximum impedance allowed power supply plane. example, equals Zmax 0.1/3.8 26.3 Next, determine power supply wiring inductance. This inductance depends actual routing path power supply plane device pin. This path includes vias, inductance balls actual connection die, inductance regulator output pin, inductance actual routing from regulator via. Approximate inductance with following formula:
Lvia 5.08h[ln(
Assume that height mils that diameter mils. Using these values above formula, inductance These values typical vias Stratix development board signal traversing about board thickness. Divide inductance number vias that parallel. vias, total inductance 0.14 Other factors that this result ball-to-die connection inductance traces, which harder estimate depend exact layout. Inductance plane very small (less than physical dimensions least lump these inductances into single approximation (Ltotal nH), which represents worst case inductance typical system, assuming wide traces power distribution. Given value power supply inductance, estimate frequency above which decoupling required. this equation:
Fcritical
26.3 838kHz 2Ltot
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Finally, this equation calculate value decoupling capacitor:
Cbypass
7.25F 2Fcritical .838 26.3
Consider example Stratix development board. There about LVTTL signals Stratix device banks calculation above LVTTL signals. signals, required value bulk decoupling increases factor (3.5)2, 12.25. Therefore, bulk decoupling equals 7.25 12.25 development board uses capacitor 3.3-V power supply (3.3V_S_IO) bulk decoupling Stratix device. This addition bulk decoupling required switching regulators associated filters output. With this level decoupling, there good performance.
Local Decoupling
Local decoupling designed work high frequencies. Unfortunately, high frequencies, discrete capacitors rarely effective themselves. There must combination discrete capacitors plane capacitance. analysis quite involved accuracy easy verify. experimental data more helpful creating design guidelines. Altera conducted several experiments this topic. Based these experiments, Altera recommends about decoupling capacitor power pin. results simulations using Agilent design system (ADS) software determined values capacitors required. amount local decoupling more difficult determine, because high frequency effects more pronounced local decoupling. Altera recommends using capacitor power pin. More detailed guidelines specific situations will available near future. should values capacitors, because doing create resonant peaks impedances. most cases best choose highest value capacitance available package required designer.
Simulating Decoupling Circuits
efficacy decoupling scheme indicated impedance between power plane ground plane across frequency interest. goal power supply decoupling scheme achieve lowest possible impedance across frequency interest. impedance low, then noise power rail shunted ground, whereas impedance high, noise stays power rail cause circuitry malfunction.
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Stratix Board Design Guidelines
this simulation, Altera placed decoupling capacitors different values parallel measured impedance from GHz. frequency interest different each application, focus frequency band interest your application. Using decoupling capacitors gives realistic number capacitors used typical decoupling scheme. behavior vias, pads, traces were captured using multilayer transmission line models ADS, which considers dielectric material dissipative losses. Eight different cases, summarized Table 4-2, were simulated wide range capacitor ratios.
Table 4-2. Simulation Cases Number Capacitors Case
1000
0.01
Waveform Name 2.2F
Z_double_decade Z_equal_ratio Z_reverse_decade Z_all_470pf_caps Z_all_1000pf_caps Z_all_point_01_caps Z_all_point_1_caps Z_all_2_point_2_caps
Figure shows simulation setup with only capacitor (only capacitor shown clarity), including parasitics, pads, routing trace vias, vias themselves. cases shown Table 4-2, model capacitor shown Figure applied repeatedly parallel. Each capacitor modeled series circuit. parasitic resistance parasitic inductance were obtained from data sheet published manufacturer capacitor. capacitor pads board were modeled 42-mil 32-mil square pads. vias were modeled circular vias with diameters mils hole diameters mils. routing distance from capacitor modeled trace, mils long mils wide, equal total distance routing both sides capacitor. These typical values were extracted from Stratix development board layout design.
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Figure 4-9. Simulation Setup Capacitor
Table shows extracted models 1000 0.01 capacitors from vendor datasheets (Panasonic AVX). Table 4-3. Extracted Models Capacitor Parasitics Capacitor Value
0.01 0.001
Part Number
ECJ1VB1C104K ECJ1VB1C103K 08056D225KAT2A ECJ-0EB1E471K ECJ-1VB1H102K
Vendor
Panasonic Panasonic AVX/Kyocera Panasonic Panasonic
Parasitic (nH)
1.50 0.83 1.00 0.86 1.13
Parasitic
0.07 0.10 0.02 0.10 0.05
(MHz)
Figure 4-10 shows simulated impedance profile eight cases listed Table 4-2.
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Figure 4-10. Impedance Simulation Results From Table
Z_all_470pf_caps Z_all_1000pf_caps magZ_all_point_01_caps magZ_all_point_1_caps magZ_double_decade magZ_equal_ratio magZ_reverse_decade magZ_all_2_point_2_caps
1E-2
freq,
1E10
Z_equal_ratio=Vout3/I_Probe3.i
following observations were made:
Decoupling very high frequencies cannot achieved discrete capacitors. must done with sandwiched power ground plane. Traditionally, number capacitors doubled every lower decade value. example, beginning with capacitor, would 0.01 capacitors. Case Table page 4-17 approximates this behavior. However, this approach often performs worse than when using equal numbers capacitors equal values, even reversing ratio (number capacitors halved each decade lower value). Using very large number values cause resonance spikes multiple frequencies, values possible contain magnitude resonance spike.
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Using capacitors gives lowest impedance profile without resonance spikes. Although 1000 capacitors (when used conjunction with caps) give impedance higher frequencies, they also result corresponding resonance spike.
study ratio versus 1000 capacitors affects impedance profile, Altera performed further simulations. Figure 4-11 shows impedance profiles when using 2.2-F caps versus using 1000 Only capacitors were used this simulation opposed allowing easy ratios. This difference significant. lower graph Figure 4-11 shows case when capacitors smoothest impedance profile lower impedance than other cases, except MHz. particular board significant noise frequency (approximately MHz), 1000 capacitor helpful. However, must ensure that there negligible noise resonant peaks. resonant peaks occur MHz, MHz, MHz, MHz, MHz, depending ratio 1000 caps caps. Figure 4-11. Impedance Profile With Combination 0.001 Capacitors
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Based simulation results, important select highest value possible particular package, because these capacitors have lowest impedance largest band frequency. Examples include lower than that unless there compelling reason such presence strong noise spike exact frequency where lower value capacitor resonates. Also, capacitor values (for example using 0.001 This mixing create undesired resonances. Stratix development board uses many mixed capacitor values decoupling, because best approach because allows flexibility test several approaches values.
Plane Capacitance
very high frequencies (above MHz), decoupling using discrete capacitors less effective. power plane capacitance decoupling noise these frequencies. understand concept plane capacitance studying classic parallel plate capacitor, shown Figure 4-12. Figure 4-12. Parallel Plane Capacitance
Power Island
Overlap Area
Ground Plane
electric field created when there power plane next ground plane. upper area Figure 4-12 shows power island plane, lower area shows ground plane, arrows represent electric field lines. This electric field gives rise capacitance, magnitude which shown
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where
permittivity free space
relative permittivity dielectric used
area overlap separation planes. there ground planes both sides power island, then capacitance needs calculated each side added determine total capacitance. Plane capacitance primary decoupling high frequencies, must integral part high speed design. high frequencies (above MHz), discrete capacitors very effective. example, consider following. Example: Determine parallel plate capacitance square inch area overlap FR-4 dielectric 4.5) separation mils. Solution: mils 1.016 10-4
permittivity free space 8.85 10-12
inch 6.4516 10-4
Applying these numbers equation page 4-21 yields Therefore, there about square inch area overlap typical FR-4 board with mils separation. value scales inverse linearly with separation linearly with area. Altera successfully used plane capacitance several boards. Case Study: Altera designed boards with Stratix test chip. first board, separation between ground 1.5-V transceiver power plane about mils. second board, ground
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islands were added (with approximate areas 0.13 square inches) next transceiver plane. islands were next layer separation mils. Figure 4-13 shows islands they appear board layout. Figure 4-13. Ground Island Used With 1.5V_XCVR Plane Increase Decoupling High Frequencies
Ground Island (Layer Power Plane (Layer
Figures 4-14 4-15 show reduction noise after adding islands. addition islands reduced noise from less than under same experimental conditions.
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Figure 4-14. Noise 1.5V_XCVR Plane With Ground Plane mils Away
Figure 4-15. Noise 1.5V_XCVR Plane With 0.13 Square Inch Island mils Away
When using split ground planes, best pair correct ground plane with correct power plane. example, 1.5V_XCVR GND_GXB planes islands should used rather than 1.5V_XCVR GND.
Plane Island Design
following sections discuss various issues related design power planes, ground planes, power ground islands.
4-24 Stratix Device Handbook, Volume
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Power Plane Island Design
Stratix devices have many power ground pins, important know connect them board. Table shows list power ground pins they connect Stratix development board. actual numbers, refer tables www.altera.com.
Table 4-4. Stratix Power Ground Pins (Part Name
VCCP_B[17.13]
Description
Digital power Stratix transceiver quads (banks) through Transmitter power Stratix transceiver quads (banks) through Receiver power Stratix transceiver quads (banks) through Power Stratix transceiver quads (banks) through guard rings. Analog power Stratix transceiver quads (banks) through PLLs
Voltage
(linear)
VCCT_B[17.13]
(linear)
VCCR_B[17.13]
(linear)
VCCG_B[17.13]
(linear)
VCCA_B[17.13]
(linear)
VCCG_PLL[12,11,8,6,5,2,1] Power supply guard ring VCCA_PLL[12,11,8,6,5,2,1] Analog power supply PLLs VCC_PLL5_OUTA VCC_PLL5_OUTB
output buffer supply PLL5 outputs [1.0] output buffer supply PLL5 outputs [3.2]
(linear) (linear) (linear) (linear)
VCC_PLL6_OUTA
output buffer supply PLL6 outputs [1.0] output buffer supply PLL6 outputs [3.2] Digital power supply device internal power Power supply I/Os banks
(linear)
VCC_PLL6_OUTB
(linear)
VCCINT VCCIO[8.7, 4.1]
(linear switching) Variable (linear switching)
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Table 4-4. Stratix Power Ground Pins (Part Name
GNDG_PLL[12,11,8,5,2,1]
Description
Ground guard rings PLLs
Voltage
GNDA_PLL[12,11,8,6,5,2,1] Analog ground PLLs GND_GXB
Ground high-speed circuitry 3.125 Gbps transceivers General-purpose ground
Notes Table 4-4:
Connect this desired voltage depending standard outputs chosen. example, Stratix development board, VCC_PLL6_OUTA VCC_PLL6_OUTB connect allow SSTLII clock (2.5V I/O) PLL6 output double data rate (DDR) memory application. Connect this standard signals bank. This value LVTTL, SSTL-II, Stratix development board, VCCIO7 connects because board uses SSTL_II standard that bank. other banks, connects
Table also shows recommended regulator (linear switching). circuitry pertaining PLLs transceivers should connected voltages generated from linear power supplies. General purpose core supplies switching linear. always better linear possible, some I/Os cores, current draw might large. transceivers have many types power supply pins. Altera recommends that isolate receive (VCCR_B[17.13]) transmit (VCCT_B[17.13]) power supplies each quad with ferrite bead. reason behind isolation prevent noise from quad leaking other quads. digital power supply (VCCP_B[17.13]) shared among quads because less sensitive noise. guard power supply VCCG_B[17.13] also shared among quads. islands shown Table 4-5:
Table 4-5. Islands Used Stratix Transceiver Quads (Part Islands
Island Island Island
Quads
quad VCCT VCCR pins (VCCT_B13 VCCR_B13) quad VCCT VCCR pins (VCCT_B14 VCCR_B14) quad VCCT VCCR pins (VCCT_B15 VCCR_B15)
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Table 4-5. Islands Used Stratix Transceiver Quads (Part Islands
Island Island Island Island
Quads
quad VCCT VCCR pins (VCCT_B16 VCCR_B16) quad VCCT VCCR pins (VCCT_B17 VCCR_B17) VCCP_B[17.13], example, digital supply quads VCCG_B[17.13], example, guard supply quads
Note Table 4-5:
Island required only 5-quad devices.
Figure 4-16 shows block diagram islands.
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Figure 4-16. Block Diagram Representation Quad Isolation
Island
Island
Ferrite Beads
Island
1.5V Linear Regulator
Island
Island (Only 5-Quad Devices)
Island
Island
Note Figure 4-16:
Island required only 5-quad devices.
Altera successfully used island approach powering Stratix transceivers Stratix development board. Figure 4-17 shows section schematic that shows islands. named 1.5V_XCVR output linear regulator that split into seven islands, namely: 1.5V_XCVR1, 1.5V_XCVR2, 1.5V_XCVR3, 1.5V_XCVR4, 1.5V_XCVR5, 1.5V_VCCP, 1.5V_VCCG. Altera currently evaluating degree which islands help reducing jitter.
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Figure 4-17. Section Schematic Showing Islands Transceiver Quads
Figure 4-18 shows layout islands. 1.5V_VCCG (guard) island different layer because layout constraints.
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Figure 4-18. Layout Islands Transceiver Quads
1.5V_XCVR4 1.5V_XCVR3 1.5V_XCVR5 1.5V_VCCP 1.5V_XCVR2 1.5V_XCVR1
Ground Plane Island Design
Stratix development board three types ground pins: GND, GND_GXB GND_PLL. GND_GXB used 3.125 Gbps transceiver ground, GND_PLL used ground, used general purpose ground board. die, GND_GXB separate planes, they connected trace package level. GND_PLL does have separate plane connected plane package level.
4-30 Stratix Device Handbook, Volume
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When designing your board must decide whether connect ground pins single ground plane board create separate ground planes GND_GXB, GND, GND_PLL connect them using ferrite beads. This difficult trade-off, there schools thought industry regarding splitting ground planes. Proponents isolating ground planes that good systems that generate noise because switching I/Os power supplies. idea that ferrite beads attenuate noise leaking from system ground (which noisy) clean ground. Noise-sensitive analog subsystems like transceivers require clean power ground, isolation provides better performance. ferrite beads must carefully selected allow plenty current handling, voltage loss, high impedance. "Resistors, Capacitors, Inductors Ferrite Beads" page 4-77 more details. Supporters solid ground plane approach claim that there benefit isolating ground planes, because noise cannot simply disappear from ground plane reaches analog circuitry some path other. layout also complicated having isolated ground planes because more layers might needed. same plane split into two, instead adding layer, layout designer must ensure that critical signals cross over split, because split causes impedance discontinuity. There answer this topic that applies systems. system relatively simple without many fast switching I/Os, there switching regulators, solid ground plane unlikely cause problems. However, system many fast, high-amplitude digital signals switching noisy external components such switching regulators, Altera recommends isolating ground planes. Stratix development board uses isolated ground approach. There three distinct ground nets: GND, GND_PLL, GND_GXB, separated several ferrite beads. Figure 4-19 shows section Stratix development board schematic highlighting isolation ground planes. Many ferrite beads were used parallel facilitate testing with several possible combinations. Altera tested performance this system with ferrite beads intact, shown Figure 4-19, with them shorted wire. Stratix EP1SGX40 device about used with design that Gray code counters. Stratix device interface running channels SPI-4.2 data running Gbps channel. usage about 46%. Stratix device also channels transceivers running PRBS data 3.125 Gbps external loopback. transmitter output 20th channel sent
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oscilloscope observe jitter diagram. This setup should result fairly heavy load devices should generate good deal noise power planes. test setup identical both tests, except shorted ferrite beads. tests showed jitter improvement approximately when isolating ground planes. devices loaded even more fully, improvement even greater. devices lightly loaded, improvement less. Figure 4-19. Isolation GND, GND_GXB GND_PLL
Ferrite Beads
GND_GXB
GND_PLL
Based test results benefit isolating ground planes noisy boards, Altera® recommends isolating GND_GXB planes with ferrite beads. determine many ferrite beads use,
4-32 Stratix Device Handbook, Volume
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Stratix Board Design Guidelines
consider following. power consumption quad about current draw about mW/1.5 Therefore, total expected current draw about Amps. Each ferrite bead resistance. there ferrite bead, voltage drop 37.5 which 2.5% 1.5-V supply. reduce this drop, multiple ferrite beads parallel. Stratix development board, there five beads parallel, that voltage drop reduced 0.5% supply voltage. GND_PLL plane, crucial separate ground plane. device package level, this plane shares ground plane with general-purpose logic ground. There separate plane development board GND_PLL testing flexibility. Altera recommends ground planes, GND_GXB, isolated ferrite beads. These planes especially important complex boards with many noisy signals switching regulators. board does have switching regulators switching signals, otherwise very cleanly designed, ground plane acceptable. Altera recommends connecting ground pins directly system GND.
Transmission Lines
This section discusses transmission line designs high-speed digital boards.
Transmission Line Topologies
This section provides brief overview main transmission line topologies commonly used high-speed digital boards. Refer transmission line design book, such Brian Wadell's Transmission Line Design Handbook, impedance equations design techniques.
Striplines
following sections detail variations stripline design topologies. Simple Stripline Simple stripline planar type transmission line well suited multilayer design. Figure 4-20 shows basic structure this transmission line. thin, centered conductive strip with width placed between conductive planes separated dielectric with thickness most basic stripline structure.
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Transmission Lines
Figure 4-20. Simple Stripline
Figures 4-21 4-22 show frequency domain simulation setup results simple stripline, respectively. Figure 4-21. Simulation Setup Simple Stripline
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Figure 4-22. Simulation Results Simple Stripline
Input Reflection Coefficient Forward Transmission,
dB(S(1,1)) freq,
-0.2 -0.4 -0.6 dB(S(2,1)) -0.8 -1.0 -1.2 -1.4 -1.6 freq,
Offset Stripline offset stripline configuration shown Figure 4-23. only difference between structure offset stripline normal stripline that conductor strip placed center (B/2 distance from planes). relative position conductor strip from B/2. This transmission line useful single-ended signals routed between ground plane power plane. strip placed closer ground plane, which less noisy than power plane. this there less noise power coupled signal improved ratio without need extra ground plane. must this structure when dielectric between planes constructed three layers dielectrics (two cores, prepeg, vice versa). Stratix development board there cores prepeg. This arrangement dielectrics produces better results because cores have lower permittivity thickness tolerances than prepegs.
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Transmission Lines
Figure 4-23. Offset Stripline
Figures 4-24 4-25 show frequency domain simulation setup results offset stripline, respectively. Figure 4-24. Simulation Setup Offset Stripline
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Figure 4-25. Simulation Results Offset Stripline
Input Reflection Coefficient dB(S(1,1)) freq, dB(S(2,1)) -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 freq, Forward Transmission,
Edge-Coupled Differential Stripline edge-coupled differential stripline shown Figure 4-26. Altera recommends using differential transmission lines noisy environments where common mode noise suppressed receiver. This type transmission line requires some degree coupling between conductive strips. coupling directly proportional distance differential transmission lines have operation modes. Even mode, which both traces excited with equal amplitude phase, mode, which traces excited with equal amplitude 180° phase. This structure must analyzed unit with proper excitation. differential signaling, mode desired operation mode canceling common mode noise. Figure 4-26. Edge-Coupled Differential Stripline
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Transmission Lines
Figures 4-27 4-28 show frequency domain simulation setup results 100- edge-coupled differential stripline, respectively. differential impedance ZDIFF (Zoo) excite port terminate others (three) with characteristic impedance input impedance
where: even mode characteristic impedance mode characteristic impedance ZDIFF differential characteristic impedance characteristic impedance Figure 4-27. Simulation Setup Edge-Coupled Differential Stripline
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Figure 4-28. Simulation Results Edge-Coupled Differential Stripline
Input Reflection Coefficient dB(S(1,1)) freq, dB(S(2,1)) -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 freq, Forward Transmission,
Edge-Coupled Differential Offset Stripline edge-coupled differential offset stripline topology, shown Figure 4-29, used when number dielectric layers exists between planes. signals this dielectric arrangement routed closer planes. This transmission line offers advantages differential transmission lines, plus flexibility wider traces without penalty total board thickness. Figure 4-29. Edge-Coupled Differential Offset Stripline
B/2+S B/2-S
Figures 4-30 4-31 show frequency domain simulation setup results 100- edge-coupled differential offset stripline, respectively. Stratix development board contains many edge-coupled
Altera Corporation February 2005
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Transmission Lines
differential striplines. Examples from board discussed "Crosstalk" page 4-72. This topology also known dual stripline, because there signal layers between power planes. Figure 4-30. Simulation Setup Edge-Coupled Differential Offset Stripline
Figure 4-31. Simulation Results Edge-Coupled Differential Offset Stripline
Input Reflection Coefficient dB(S(1,1)) freq, dB(S(2,1)) -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 freq, Forward Transmission,
Broadside-Coupled Differential Stripline Broadside-coupled differential stripline, shown Figure 4-32, some advantages over edge-coupled differential stripline, including higher coupling easier routing. disadvantages possibility
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traces becoming narrow manufacturability board board becoming thick compensate trace-width thickness ratio. This configuration helpful when differential high-speed lines reside inner rows BGA, impossible route lines (one differential pair) between vias pads. Figure 4-32. Broadside-Coupled Differential Stripline
Figures 4-33 4-34 show frequency domain simulation setup results 100- broadside-coupled differential stripline, respectively. Figure 4-33. Simulation Setup Broadside-Coupled Differential Stripline
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Figure 4-34. Simulation Results Broadside-Coupled Differential Stripline
Input Reflection Coefficient
-0.2 -0.4 -0.6
Forward Transmission,
dB(S(1,1))
dB(S(2,1))
-0.8 -1.0
-1.2 -1.4 -1.6
freq,
freq,
Broadside-Coupled Differential Offset Stripline broadside-coupled differential offset stripline structure, shown Figure 4-35, advantages broadside-coupled differential stripline with added flexibility that allows adjust differential impedance offsetting conductor strips. differential impedance increases offset dimension increases. Figure 4-35. Broadside-Coupled Differential Offset Stripline
Figures 4-36 4-37 show frequency domain simulation setup results 100- broadside-coupled differential offset stripline, respectively.
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Stratix development board uses edge coupling instead broadside coupling, with loose coupling between positive negative traces. Although tight coupling provides greater noise immunity, necessary loosen coupling because mechanical placement requirements connectors. With loose coupling, routing broadside coupled, thickness board increases. With loose coupling, edge-coupled routing preferred unless there flexibility increase board thickness. Figure 4-36. Simulation Setup Broadside-Coupled Differential Offset Stripline
Metal-i T[i], ND[i], E[i] Dielectric-i ER[i], H[i], TAND[i]
MLSUBSTRATE4 Subs T[4]=0.6 Er[1]=4.5 H[1]=13.0 Cond[4]=5.7E7 Num=1 nD[1]=0.022 rType [1]=ground Z=100 T[1]=0.6 rType [2]=s igna Cond[1]=5.7e rType [3]=s igna Er[2]=4.5 rType [4]=powe H[2]=10.0 nD[2]=0.022 T[2]=0.6 Cond[2]=5.7E7 Er[3]=4.5 VAR1 H[3]=13.0 wo=6.20727 opt{ nD[3]=0.022 T[3]=0.6 Cond[3]=5.7E7
ML1CTL_C Subs t="Subs ngth=1000.0 W=6.0 RLGC_File RLGC=no
Num=2 Z=100
COMBINE2ML COMB1 Couple d[1]="TL1" Couple d[2]="TL2" S=-(6+s RLGC_File RLGC=no
ML1CTL_C Subs t="Subs ngth=1000.0 W=6.0 RLGC_File RLGC=no
Figure 4-37. Simulation Results Broadside-Coupled Differential Offset Stripline
Input Reflection Coefficient dB(S(1,1)) freq, dB(S(2,1)) -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 freq, Forward Transmission,
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Transmission Lines
Microstrips
Microstrip topologies either simple differential. Microstrips most popular planar transmission lines because their cost easy integration with other passive active components PCBs. Simple Microstrip Figure 4-38 shows simple microstrip topology. microstrip conductive strip width thickness placed dielectric material backed with ground plane. Figure 4-38. Simple Microstrip
Figures 4-39 4-40 show frequency domain simulation setup results 50-W simple microstrip, respectively. Figure 4-39. Simulation Setup Simple Microstrip
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Figure 4-40. Simulation Results Simple Microstrip
Input Reflection Coefficient dB(S(1,1)) freq, -1.0 -1.2 freq, -0.4 dB(S(2,1)) -0.6 -0.8 -0.2 Forward Transmission,
Differential Microstrip differential microstrip topology, shown Figure 4-41, advantages simple microstrip, also provides common mode noise cancellation. main problem with differential microstrips that coupling between positive negative traces low. Figure 4-41. Differential Microstrip
Figures 4-42 4-43 show variants differential microstrip extracted from Stratix development board.
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Transmission Lines
Figure 4-42. Loosely Coupled Differential Microstrip
Differential Pairs
Differential Microstrip Loosely Coupled
Figure 4-43. Tightly Coupled Differential Microstrip
Tightly Coupled Microstrips
Figures 4-44 4-45 show frequency domain simulation setup results 100- tightly coupled differential microstrip, respectively.
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Figure 4-44. Simulation Setup Tightly Coupled Differential Microstrip
Figure 4-45. Simulation Results Tightly Coupled Differential Microstrip
Input Reflection Coefficient dB(S(1,1)) freq, -1.2 freq, -0.8 -1.0 dB(S(2,1)) -0.6 -0.2 -0.4 Forward Transmission,
Coplanar Wave Guides
There three types coplanar wave guides: simple, grounded, grounded differential. Simple Coplanar Wave Guide simple coplanar wave guide, shown Figure 4-46, used primarily microwave systems. This structure does require vias, easily mount passive active devices signal path, resulting
Altera Corporation February 2005
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Transmission Lines
low-loss, high-speed transmission line. simple coplanar wave guide requires that substrate thickness "infinite," that fields remain outside dielectric. cannot this structure multilayer boards because cannot have second layer. Figure 4-46. Simple Coplanar Wave Guide
Grounded Coplanar Wave Guide grounded coplanar wave guide used extensively communications systems that integrate different technologies such surface mount technology, multichip modules, multilayer boards. dielectric thickness must least five times spacing considered grounded coplanar wave guide; otherwise, considered microstrip with ground shield. Figure 4-47 shows grounded coplanar wave guide topology. Figure 4-47. Grounded Coplanar Wave Guide
Figures 4-48 4-49 show frequency domain simulation setup results grounded coplanar wave guide, respectively.
4-48 Stratix Device Handbook, Volume
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Figure 4-48. Simulation Setup Grounded Coplanar Wave Guide
Figure 4-49. Simulation Results Grounded Coplanar Wave Guide
Input Reflection Coefficient dB(S(1,1)) freq, dB(S(2,1)) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 freq, Forward Transmission,
Figure 4-50 shows Stratix development board's grounded coplanar wave guide edge-coupled differential offset stripline layout capture plot. This particular differential pair used 1.0-Gbps source synchronous lines.
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Transmission Lines
Figure 4-50. Layout Capture Plot Grounded Coplanar Wave Guide Edge-Coupled Differential Offset Stripline
Grounded Differential Coplanar Wave Guide grounded differential coplanar wave guide differential version grounded coplanar wave guide used high-speed digital systems that require maximum noise immunity. Figure 4-51 shows topology. same limitations apply this topology grounded coplanar wave guide. This topology does appear Stratix development board because loose coupling requirements. "Broadside-Coupled Differential Offset Stripline" page 4-42 more information.
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Figure 4-51. Grounded Differential Coplanar Wave Guide
Figures 4-52 4-53 show frequency domain simulation setup results 100- grounded differential coplanar wave guide, respectively. Figure 4-52. Simulation Setup Grounded Differential Coplanar Wave Guide
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Figure 4-53. Simulation Results Grounded Differential Coplanar Wave Guide
Input Reflection Coefficient dB(S(1,1)) freq, -0.1 -0.2 -0.3 dB(S(2,1)) -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 freq, Forward Transmission,
Transmission Line Termination
High-speed signals require termination beginning, end, both sides transmission line prevent reflected signal from ends from corrupting original signal. This section briefly describes several termination techniques. more details about each technique, refer AN315: Guidelines Designing High-Speed FPGA PCBs. Figure 4-54 shows different termination techniques.
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Figure 4-54. Termination Techniques
Series Parallel
Source
Transmission Line
Load
Source
Transmission Line
Load
Thevenin
Source
Transmission Line
Load
Source
Transmission Line
Load
Differential Parallel
Fly-by
Transmission Line
Load Source Transmission Line
Source
Load
Series Termination
With series termination, place termination resistor series with transmission line source transmission line. value resistor (Rs) value output impedance buffer must optimal performance. This always possible cases when buffer output impedance depends current setting voltage swing. most cases, using resistor series works well typical CMOS buffers such those Stratix devices. Series termination minimizes power dissipation, perfect impedance matching always possible, because buffer output impedance varies.
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Parallel Termination
With parallel termination, place resistor whose value equal impedance trace line receiver side. Ideally, resistor should directly pin. Parallel termination better than series termination when output impedance buffer unknown. With parallel termination, almost perfect impedance match between transmission line termination resistor. disadvantage with parallel termination that increases power dissipation because path ground.
Termination
termination identical parallel termination, except that resistors achieve impedance match. resistors also provide level. criteria determine value resistors. First, resistors parallel must equal line impedance. Second, resistors must form voltage divider that restored voltage equals desired level. With parallel termination, achieve almost perfect impedance match between transmission line termination resistors. also restore voltage AC-coupled signals. main disadvantages termination power dissipation added elements.
Termination
termination identical parallel termination except that termination impedance consists resistor capacitor. capacitor acts block, reducing static power dissipation. capacitor must chosen that time constant about rise time signal. Perform simulations choose best value capacitor. termination provides advantages parallel termination without power dissipation. main disadvantages rise fall time degradation added elements.
Differential Parallel Termination
With differential parallel termination, place termination resistor between positive negative signals, close receiver pins. This type termination subset parallel termination. Specific standards, example, SSTL-II interface, sometimes require both series parallel termination. Figure 4-55 shows termination shown this particular standard.
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Figure 4-55. Class Termination Memory Interfaces
1.25V Output Buffer Input Buffer
VREF 1.25V
Fly-By Termination
Fly-by termination precisely termination technique, placement technique termination resistors. understand fly-by, consider parallel (non fly-by) termination shown Figure 4-56. Layout constraints might prevent termination resistor, from being placed close receiver (the load). middle device there only inch trace length between termination point receiver pin, setup degrades signal quality, because extra stub length acts capacitive load. Figure 4-56. Normal Termination Resistor Placement
Transmission Line
Fly-by Termination
Source
Stratix
prevent this degradation, place termination resistor after load, shown Figure 4-57. Even resistor couple inches away, termination occurs transmission line, there significant reflections. trace from transmission line receiver kept small.
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Transmission Lines
Figure 4-57. Fly-By Termination Resistor Placement Technique
Transmission Line
Source
Fly-by Termination
Stratix
simulation setup fly-by termination shown Figure 4-58. upper circuit this diagram fly-by termination resistor placement, lower normal placement. Figure 4-59 shows some simulation results that show fly-by termination technique helps improve signal integrity. Figure 4-58. Simulation Setup Normal Versus Fly-By Termination
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simulation results shown Figure 4-59. signal quality remains same regardless away resistor provided th
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