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This section provides information on design transition, board design guidelines, and Stratix GX device path delay issues. This section includes the following chapter:

Chapter 3, Transitioning APEX Designs to Stratix & Stratix GX Devices Chapter 4, Stratix GX Board Design Guidelines Chapter 5, Quartus II Software Fitter Warnings

Section II. Design Guidelines
This section provides information on design transition, board design guidelines, and Stratix GX device path delay issues. This section includes the following chapter:
Chapter 3, Transitioning APEX Designs to Stratix & Stratix GX Devices Chapter 4, Stratix GX Board Design Guidelines Chapter 5, Quartus II Software Fitter Warnings
Revision History
The table below shows the revision history for Chapters 3 through 5. Chapter(s) Date / Version
3 4 5 February 2005 v3.0
Changes Made
Added chapter to Stratix GX Device Handbook.
February 2005 Added chapter to Stratix GX Device Handbook. v1.0 March 2005 v1.0 Added chapter to Stratix GX Device Handbook.
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Section II-1 Preliminary
Design Guidelines
Stratix GX Device Handbook, Volume 3
Section II-2 Preliminary
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3. Transitioning APEX Designs to Stratix & Stratix GX Devices
S52012-3.0
Introduction
General Architecture
Stratix and Stratix GX devices offer many new features and architectural enhancements. Enhanced logic elements (LEs) and the MultiTrack interconnect structure offer reduced resource utilization and considerable design performance improvement. The MultiTrack interconnect uses DirectDrive technology to ensure the availability of deterministic routing resources for any design block, regardless of its placement within the device. All architectural changes between Stratix and Stratix GX and APEX II or APEX 20K devices described in this section do not require any design changes. However, you must resynthesize your design and recompile in the Quartus® II software to target Stratix and Stratix GX devices.
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General Architecture
Logic Elements
Stratix and Stratix GX device LEs include several new, advanced features that improve design performance and reduce logic resource consumption (see Table 3-1). The Quartus II software automatically uses these new LE features to improve device utilization.
Table 3-1. Stratix & Stratix GX LE Features Feature Function Benefit
Conserves LE resources Register chain interconnects Direct path between the register output Provides fast shift register of an LE and the register input of an adjacent LE within the same logic array implementation Saves local interconnect routing block (LAB) resources within an LAB Look-up table (LUT) chain interconnects Direct path between the combinatorial Allows LUTs within the same LAB to output of an LE and the fast LUT input cascade together for high-speed wide of an adjacent LE within the same LAB fan-in functions, such as wide XOR operations Bypasses local interconnect for faster performance Allows the register output to feed back into the LUT of the same LE, such that the register is packed with its own fanout LUT Uses one set of LEs for implementing both an adder and subtractor Enhanced register packing mode Uses resources more efficiently
Register-to-LUT feedback path
Dynamic arithmetic mode
Improves performance for functions that switch between addition and subtraction frequently, such as correlators
Carry-select chain
Calculates outputs for a possible carryGives immediate access to result for in of 1 or 0 in parallel both a carry-in of 1 or 0 Increases speed of carry functions for high-speed operations, such as counters, adders, and comparators Supports direct asynchronous clear and preset functions Conserves LE resources Does not require additional logic resources to implement NOT-gate push-back
Asynchronous clear and asynchronous preset function
In addition to the new LE features described in Table 3-1, there are enhancements to the chains that connect LEs together. Carry chains are implemented vertically in Stratix and Stratix GX devices, instead of horizontally as in APEX II and APEX 20K devices, and continue across rows, instead of across columns, as shown in Figure 3-1. Also note that the Stratix and Stratix GX architectures do not support the cascade primitive. Therefore, the Quartus II Compiler automatically converts
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cascade primitives in APEX II and APEX 20K designs to a wire primitive when compiled for Stratix and Stratix GX devices. These architectural changes are transparent to the user and do not require design changes. Figure 3-1. Carry Chain Implementation in APEX II & APEX 20K Devices vs. Stratix & Stratix GX Devices
APEX II & APEX 20K Devices Stratix Devices
Carry Chains
Carry-Select Chains
LABs (with 10 LEs Each)
MultiTrack Interconnect
Stratix and Stratix GX devices use the MultiTrack interconnect structure to provide a high-speed connection between logic resources using performance-optimized routing channels of different lengths. This feature maximizes overall design performance by placing critical paths on routing lines with greater speed, resulting in minimal propagation delay.
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General Architecture
Stratix and Stratix GX device MultiTrack interconnect resources are described in Table 3-2.
Table 3-2. Stratix & Stratix GX Device MultiTrack Interconnect Resources Routing Type
Row Row Row Row Column Column Column
Interconnect
Direct link R4 R8 R24 C4 C8 C16
Adjacent LABs and / or blocks Four LAB units horizontally Eight LAB units horizontally Horizontal routing across the width of the device Four LAB units vertically Eight LAB units vertically Vertical routing across the length of the device
Direct link routing saves row routing resources while providing fast communication paths between resource blocks. Direct link interconnects allow an LAB, digital signal processing (DSP) block, or TriMatrix memory block to drive data into the local interconnect of its left and right neighbors. LABs, DSP blocks, and TriMatrix memory blocks can also use direct link interconnects to drive data back into themselves for feedback. The Quartus II software automatically uses these routing resources to enhance design performance.
For more information about LE architecture and the MultiTrack interconnect structure in Stratix and Stratix GX devices, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
DirectDrive Technology
When using APEX II or APE 20K devices, you must place critical paths in the same MegaLAB column to improve performance. Additionally, you should place critical paths in the same MegaLAB structure for optimal performance. However, this restriction does not exist in Stratix and Stratix GX devices because they do not contain MegaLAB structures. With the new DirectDrive technology in Stratix and Stratix GX devices, the actual distance between the source and destination of a path is the most important criteria for meeting timing performance. DirectDrive technology ensures that the same routing resources are available to each design block, regardless of its location in the device.
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Architectural Element Names
LAB: logic array block DSP: digital signal processing block DSPOUT: adder / subtractor / accumulator or summation block of the DSP block M512: 512-bit memory block M4K: 4-Kbit memory block M-RAM: 512-Kbit memory block
Elements within architectural blocks include:
LE: logic element IOC: I / O element PLL: phase-locked loop DSPMULT: DSP block multiplier SERDESTX: transmitter serializer / deserializer SERDESRX: receiver serializer / deserializer
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General Architecture
Table 3-3 highlights the new location syntax used for Stratix and Stratix GX devices.
Table 3-3. Stratix & Stratix GX Location Assignment Syntax Architectural Elements
Blocks
Example of Location Syntax Element Name Location Syntax Location
Description
Designates the LAB in row 1, column 1 Designates the first LE, N0, in the LAB located in row 1, column 1 Pin 5
Logic
Pins (1)
Note to Table 3-3:
Use the following guidelines with the new naming system:
Figure 3-2 show the Stratix and Stratix GX architectural element numbering convention. Figure 3-3 displays the floorplan view in the Quartus II software.
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Figure 3-2. Stratix & Stratix GX Architectural Elements Note (1)
M4K RAM Blocks are Two Units Wide and One Unit High
LAB (1, 18)
LAB (11, 18)
M512 (12, 18)
LAB (13, 18)
M4K (14, 18)
LAB (16, 18)
DSP Block (17, 1) is Two Units Wide and Eight Units High
LAB (1, 17)
LAB (11, 17)
M512 (12, 17)
LAB (13, 17)
M4K (14, 17)
LAB (16, 17)
LAB (1, 16)
LAB (11, 16)
M512 (12, 16)
LAB (13, 16)
M4K (14, 16)
LAB (16, 16)
DSPMULT (17, 7, 0) and (17, 7, 1)
LAB (1, 15)
LAB (11, 15)
M512 (12, 15)
LAB (13, 15)
M4K (14, 15)
LAB (16, 15)
M4K (14, 14)
LAB (16, 14)
DSPMULT (17, 5, 0) and (17, 5, 1)
M4K (14, 13) Mega RAM Block is 13 Units Wide and 13 Units High
LAB (16, 13)
DSPOUT (18, 1, 0) and (18, 1, 7)
Mega RAM (1, 2)
DSPMULT (17, 3, 0) and (17, 3, 1)
Pins (2)
M4K (14, 2)
LAB (16, 2) DSPMULT (17, 1, 0) and (17, 1, 1)
PLL (0, 1, 0)
LAB (1, 1)
LAB (11, 1)
M512 (12, 1)
LAB (13, 1)
M4K (14, 1)
LAB (16, 1)
(2) Origin (0, 0)
Notes to Figure 3-2:
(1) (2) (3) Figure 3-2 shows part of a Stratix and Stratix GX device. Large block elements use their lower-left corner for the coordinate location. The Stratix GX architectural elements include transceiver blocks on the right side of the device.
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TriMatrix Memory
Figure 3-3. LE Numbering as Shown in the Quartus II Software
TriMatrix Memory
TriMatrix memory has three different sizes of memory blocks, each optimized for a different purpose or application. M512 blocks consist of 512 bits plus parity (576 bits), M4K blocks consist of 4K bits plus parity (4, 608 bits), and M-RAM blocks consist of 512K bits plus parity (589, 824 bits). This new structure differs from APEX II and APEX 20K devices, which feature uniformly sized embedded system blocks (ESBs) either 4 Kbits (APEX II devices) or 2 Kbits (APEX 20K devices) large. Stratix and Stratix GX TriMatrix memory blocks give you advanced control of each memory block, with features such as byte enables, parity bit storage, and shift-register mode, as well as mixed-port width support and true dual-port mode operation.
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Table 3-4 compares TriMatrix memory with ESBs.
Table 3-4. Stratix & Stratix GX TriMatrix Memory Blocks vs. APEX II & APEX 20K ESBs Stratix & Stratix GX Features M512 RAM
Size (bits) Parity bits Byte enable True dual-port mode Embedded shift register Dedicated contentaddressable memory (CAM) support Pre-loadable initialization with a .mif (1) Packed mode (2) Feed-through behavior Output power-up condition 576 Yes No No
APEX II ESB M4K RAM
4, 608 Yes Yes Yes Yes
APEX 20K ESB
2, 048 No No
M-RAM
589, 824 4, 096 No No
No Yes Yes Yes Includes support Includes support Includes support for mixed width for mixed width for mixed width Yes No No No No Yes No Yes
Yes No
No Rising edge Powers up cleared even if using a .mif (1)
Yes Rising edge Powers up cleared even if using a .mif (1)
No Rising edge Powers up with unknown state
Yes Falling edge Powers up cleared or to initialized value, if using a .mif (1)
Notes to Table 3-4:
(1) (2) .mif: Memory Initialization File. Packed mode refers to combining two single-port RAM blocks into a single RAM block that is placed into true dual-port mode.
Stratix and Stratix GX TriMatrix memory blocks only support pipelined mode, while APEX II and APEX 20K ESBs support both pipelined and flow-through modes. Since all TriMatrix memory blocks can be pipelined, all input data and address lines are registered, while outputs can be either registered or combinatorial. You can use Stratix and Stratix GX memory block registers to implement input and output registers without utilizing additional resources. You can compile designs containing pipelined memory blocks (inputs registered) for Stratix and Stratix GX devices without any modifications. However, if an APEX II or
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TriMatrix Memory
APEX 20K design contains flow-through memory, you must modify the memory modules to target the Stratix and Stratix GX architectures (see "Memory Megafunctions" on page 3-12 for more information).
For more information about TriMatrix memory and converting flowthrough memory modules to pipelined, see the TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices chapter in the Stratix GX Device Handbook and AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs.
Same-Port Read-During-Write Mode
In same-port read-during-write mode, the RAM block can be in singleport, simple dual-port, or true dual-port mode. One port from the RAM block both reads and writes to the same address location using the same clock. When APEX II or APEX 20K devices perform a same-port readduring-write operation, the new data is available on the falling edge of the clock cycle on which it was written, as shown in Figure 3-4. When Stratix and Stratix GX devices perform a same-port read-during-write operation, the new data is available on the rising edge of the same clock cycle on which it was written, as shown in Figure 3-5. This holds true for all TriMatrix memory blocks. Figure 3-4. Falling Edge Feed-Through Behavior (APEX II & APEX 20K Devices) Note (1)
Note to Figure 3-4:
(1) Figures 3-4 and 3-5 assume that the address stays constant throughout and that the outputs are not registered.
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Figure 3-5. Rising Edge Feed-Through Behavior (Stratix & Stratix GX Devices) Note (1)
Note to Figure 3-5:
(1) Figures 3-4 and 3-5 assume that the address stays constant throughout and that the outputs are not registered.
Mixed-Port Read-During-Write Mode
Mixed-port read-during-write mode occurs when a RAM block in simple or true dual-port mode has one port reading and the other port writing to the same address location using the same clock. In APEX II and APEX 20K designs, the ESB outputs the old data in the first half of the clock cycle and the new data in the second half of the clock cycle, as indicated by Figure 3-6. Figure 3-6. Mixed-Port Feed-Through Behavior (APEX II & APEX 20K Devices) Note (1)
Note to Figure 3-6:
(1) Figure 3-6 assumes that outputs are not registered.
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TriMatrix Memory
Note to Figure 3-7:
(1) Figures 3-7 and 3-8 assume that the address stays constant throughout and that the outputs are not registered.
Note to Figure 3-8:
(1) Figures 3-7 and 3-8 assume that the address stays constant throughout and that the outputs are not registered.
Memory Megafunctions
To convert RAM and ROM originally targeting the APEX II or APEX 20K architecture to Stratix or Stratix GX memory, specify Stratix or Stratix GX as the target family in the MegaWizard Plug-In Manager. The software
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updates the memory module for the Stratix or Stratix GX architecture and instantiates the new synchronous memory megafunction, altsyncram, which supports both RAM and ROM blocks in the Stratix and Stratix GX architectures.
FIFO Conditions
Design Migration Mode in Quartus II Software
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TriMatrix Memory
If the functionality of the APEX II or APEX 20K memory megafunction differs from the altsyncram functionality and at least one clock feeds the memory megafunction, the Quartus II software converts the APEX II or APEX 20K memory megafunction to the Stratix or Stratix GX altsyncram megafunction. This conversion is useful for an initial evaluation of how a design might perform in Stratix or Stratix GX devices and should only be used for evaluation purposes. During this process, the Quartus II software generates a warning that the conversion may be functionally incorrect and timing results may not be accurate. Since the functionality may be incorrect and the compilation is only intended for comparative purposes, the Quartus II software does not generate a programming file. A functionally correct conversion requires manually instantiating the altsyncram megafunction and may require additional design changes. If the previous memory function does not have a clock (fully asynchronous), the fitting-evaluation conversion results in an error message during compilation and does not successfully convert the design.
See AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs for more information. Table 3-5 summarizes the possible scenarios when using design migration mode and the resulting behavior of the Quartus II software. The most common cases where design-migration mode may have difficulty converting the existing design are when:
A port is reading from an address that is being written to by another port (mixed-port read-during-write mode). If both ports are using the same clock, the read port in Stratix and Stratix GX devices do not see the new data until the next clock cycle, after the new data was written.
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There are differences in power-up behavior between APEX II, APEX 20K, and Stratix and Stratix GX devices. You should manually account for these differences to maintain desired operation of the system.
Table 3-5. Migration Mode Summary Memory Configuration
Single-port
Conditions
Possible Instantiated Megafunctions
Quartus II Warning Message(s)
Power-up differences. (1)
Programming File Generated
All inputs are registered. altram
Power-up differences. Mixed-port read- duringwrite. (1) Power-up differences. Mixed-port read- duringwrite. Read enable will be registered. (1)
alt3pram
Dual-port Read-enable ports are unregistered. Other inputs registered.
Dual-port
Any other unregistered port except read-enable ports. Clock available. At least one registered input. Clock available. No clock.
Compile for fitting- evaluation No purposes.
Single-port
Compile for fitting- evaluation No purposes. Error - no conversion possible. No
No clock
Note to Table 3-5:
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DSP Block
Simple multiplier mode Multiply-accumulator mode Two-multipliers adder mode Four-multipliers adder mode
Associated megafunctions are available in the Quartus II software to implement each mode of the DSP block.
DSP Block Megafunctions
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PLLs & Clock Networks
For more information about using DSP blocks in Stratix and Stratix GX devices, see the DSP Blocks in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook. Stratix and Stratix GX devices provide exceptional clock management with a hierarchical clock network and up to four enhanced phase-locked loops (PLLs) and eight fast PLLs versus the four general-purpose PLLs and four True-LVDS PLLs in APEX II devices. By providing superior clock interfacing, numerous advanced clocking features, and significant enhancements over APEX II and APEX 20K PLLs, the Stratix and Stratix GX device PLLs increase system performance and bandwidth.
PLLs & Clock Networks
Clock Networks
There are 16 global clock networks available throughout each Stratix or Stratix GX device as well as two fast regional and four regional clock networks per device quadrant, resulting in up to 40 unique clock networks per device. The increased number of dedicated clock resources available in Stratix and Stratix GX devices eliminate the need to use general-purpose I / O pins as clock inputs. Stratix EP1S25 and smaller devices have 16 dedicated clock pins and EP1S30 and larger devices have four additional clock pins to feed various clocking networks. In comparison, APEX II devices have eight dedicated clock pins and APEX 20KE and APEX 20KC devices have four dedicated clock pins.
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The dedicated clock pins in Stratix and Stratix GX devices can feed the PLL clock inputs, the global clock networks, and the regional clock networks. PLL outputs and internally-generated signals can also drive the global clock network. These global clocks are available throughout the entire device to clock all device resources. Stratix and Stratix GX devices are divided into four quadrants, each equipped with four regional clock networks. The regional clock network can be fed by either the dedicated clock pins or the PLL outputs within its device quadrant. The regional clock network can only feed device resources within its particular device quadrant. Each Stratix and Stratix GX device provides eight dedicated fast clock I / O pins FCLK7.0 versus four dedicated fast I / O pins in APEX II and APEX 20K devices. The fast regional clock network can be fed by these dedicated FCLK7.0 pins or by the I / O interconnect. The I / O interconnect allows internal logic or any I / O pin to drive the fast regional clock network. The fast regional clock network is available for generalpurpose clocking as well as high fan-out control signals such as clear, preset, enable, TRDY and IRDY for PCI applications, or bidirectional or output pins. EP1S25 and smaller devices have eight fast regional clock networks, two per device quadrant. The quadrants in EP1S30 and larger devices are divided in half, and each half-quadrant can be clocked by one of the eight fast regional networks. Additionally, each fast regional clock network can drive its neighboring half-quadrant (within the same device quadrant).
Table 3-6 highlights Stratix and Stratix GX PLL enhancements to existing APEX II, APEX 20KE and APEX 20KC PLL features.
Table 3-6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 1 of 2) Stratix & Stratix GX Feature Enhanced PLLs
Number of PLLs Two (EP1S30 and smaller devices) four (EP1S40 and larger devices) (9) 3 MHz
APEX II PLLs Fast PLLs
Four (EP1S25 and Four generalpurpose PLLs and smaller devices) four LVDS PLLs eight (EP1S30 and larger devices) (10) 15 MHz 1.5 MHz 420 MHz
APEX 20KE & APEX 20KC PLLs
Up to four generalpurpose PLLs. Up to two LVDS PLLs. (1) 1.5 MHz 420 MHz
Minimum input frequency Maximum input frequency
250 to 582 MHz (2) 644.5 MHz (11)
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PLLs & Clock Networks
Table 3-6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 2 of 2) Stratix & Stratix GX Feature Enhanced PLLs
Internal clock outputs per PLL External clock outputs per PLL 6 Four differential / eight singled-ended or one single-ended (4) Down to 160-ps increments (6)
APEX II PLLs Fast PLLs
APEX 20KE & APEX 20KC PLLs
Phase Shift Time shift M counter values N counter values PLL clock input sharing T1 / E1 rate conversion (8) Notes to Table 3-6:
Down to 125-ps increments (6)
500-ps to 1-ns resolution No 1 to 160 1 to 16 Yes Yes
0.4- to 1-ns resolution No 2 to 160 1 to 16 Yes Yes
EP20K200E and smaller devices only have two general-purpose PLLs. EP20K400E and larger devices have two LVDS PLLs and four general-purpose PLLs. For more information, see AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices. (2) The maximum input frequency for Stratix and Stratix GX enhanced PLLs depends on the I / O standard used with that input clock pin. For more information, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook. (3) Fast PLLs 1, 2, 3, and 4 have three internal clock output ports per PLL. Fast PLLs 7, 8, 9, and 10 have two internal clock output ports per PLL. (4) Every Stratix device has two enhanced PLLs with eight single-ended or four differential outputs each. Two additional enhanced PLLs in EP1S80, EP1S60, and EP1S40 devices each have one single-ended output. (5) Any I / O pin can be driven by the fast PLL global or regional outputs as an external clock output pin. (6) The smallest phase shift unit is determined by the voltage-controlled oscillator (VCO) period divided by 8. (7) There is a maximum of 3 ns between any two PLL clock outputs. (8) The T1 clock frequency is 1.544 MHz and the E1 clock frequency is 2.048 MHz, which violates the minimum clock input frequency requirement of the Stratix PLL. (9) Stratix GX EP1SGX10 and EP1SGX25 contain two. EP1SGX40 contains four. (10) Stratix GX EP1SGX10 and EP1SGX25 contain two. EP1SGX40 contains four. (11) Stratix GX supports clock rates of 1 Gbps using DPA.
Enhanced PLLs
Stratix and Stratix GX devices provide up to four enhanced PLLs with advanced PLL features. In addition to the feature changes mentioned in Table 3-6, Stratix and Stratix GX device PLLs include many new,
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advanced features to improve system timing management and performance. Table 3-7 shows some of the new features available in Stratix and Stratix GX enhanced PLLs.
Table 3-7. Stratix & Stratix GX Enhanced PLL Features Feature
PLL clock outputs can feed logic array (1) PLL locked output can feed the logic array (1) Multiplication allowed in zero-delay buffer mode or external feedback mode Programmable phase shift allowed in zero-delay buffer mode or external feedback mode (2) Phase frequency detector (PFD) disable Clock output disable (3) Programmable lock detect & gated lock Dynamic clock switchover PLL reconfiguration Programmable bandwidth Spread spectrum Notes to Table 3-7:
(1) (2) (3) (4) These features are also available in fast PLLs. In addition to the delay chains at each counter, you can specify the programmable phase shift for each PLL output at fine and coarse levels. Each PLL clock output has an associated clock enable signal. If the PLL is used in external feedback mode, the PLL will need to relock.
Description
Allows the PLL clock outputs to feed data ports of registers or combinatorial logic. Allows the PLL locked port to feed data ports of registers or combinatorial logic. The PLL clock outputs can be a multiplied or divided down ratio of the PLL input clock. The PLL clock outputs can be phase shifted. The phase shift is relative to the PLL clock output.
Programmable duty cycle (1) Allows variable duty cycle for each PLL clock output.
Allows the VCO to operate at its last set control voltage and frequency with some long term drift. PLL maintains lock with output clocks disabled. (4) Holds the lock signal low for a programmable number of input clock cycles. Enables the PLL to switch between two reference input clocks, either for clock redundancy or dual-clock domain applications. Allows the counters and delay elements within the PLL to be reconfigured in realtime without reloading a programmer object file (.pof). Provides advanced control of the PLL bandwidth by using the programmable control of the PLL loop characteristics. Modulates the target frequency over a frequency range to reduce electromagnetic interference (EMI) emissions.
Fast PLLs
Stratix and Stratix GX fast PLLs are similar to the APEX II True-LVDS PLLs in that the W setting, which governs the relationship between the clock input and the data rate, and the J setting, which controls the width
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PLLs & Clock Networks
of the high-speed differential I / O data bus, do not have to be equal. Additionally, Stratix and Stratix GX fast PLLs offer up to three clock outputs, two multiplied high-speed PLL clocks to drive the serializer / deserializer (SERDES) block and / or an external pin, and a low-speed clock to drive the logic array. You can use fast PLLs for both high-speed interfacing and for general-purpose PLL applications. Table 3-8 shows the differences between Stratix and Stratix GX fast PLLs and APEX II and APEX 20K True-LVDS PLLs.
Table 3-8. Stratix & Stratix GX Fast PLL vs. APEX II & APEX 20K True-LVDS PLL Feature
Number of fast PLLs or TrueLVDS PLLs (1)
Stratix & Stratix GX
Four (EP1S25 and smaller devices) fast PLLs Eight (EP1S30 and larger devices) fast PLLs (4) 20 300 to 840 MHz (5) 300 - M MHz 300 - M MHz
APEX II
Four True-LVDS PLLs
APEX 20KE APEX 20KC
Two True-LVDS PLLs (2)
18 200 MHz to 1GHz 50 MHz 30 MHz
The Stratix and Stratix GX fast PLL VCO frequency range is 300 to 840 MHz, and the APEX II True-LVDS PLL VCO frequency range is 200 MHz to 1 GHz. Therefore, you must update designs that use a data rate of less than 300 megabits per second (Mbps) to use the enhanced PLLs and M512 RAM blocks in SERDES bypass mode. Additionally, you must update designs that use a data rate faster than 840 Mbps.
altpll Megafunction
Altera recommends that you replace instances of the altclklock megafunction with the altpll megafunction to take advantage of new Stratix and Stratix GX PLL features. Although in most cases you can retarget your APEX II or APEX 20K design to a Stratix or Stratix GX
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You can compile APEX II, APEX 20KE, and APEX 20KC designs using the altclklock megafunction in normal mode for Stratix and Stratix GX devices without updating the megafunction. However, you should replace the altclklock megafunction with the altpll megafunction. If the Quartus II software cannot implement the requested clock multiplication and division of the PLL, the compiler reports an error message with the appropriate reason stated.
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PLLs & Clock Networks
APEX II, APEX 20KE, and APEX 20KC devices have only one external clock output available per PLL. Therefore, when retargeting an APEX II, APEX 20KE, or APEX 20KC design that uses PLLs in zero delay buffer mode or external feedback mode to a Stratix or Stratix GX device, you should replace instances of the altclklock megafunction. If an APEX II, APEX 20KE, or APEX 20KC altclklock module only uses one PLL clock output (internal or external) and is compiled to target a Stratix or Stratix GX device, the design compiles successfully with a warning that the design uses the Stratix or Stratix GX PLL external clock output, extclk0. However, if the APEX II, APEX 20KE, or APEX 20KC PLL has more than one PLL clock output, you must replace instances of the altclklock megafunction with the altpll megafunction because the Quartus II Compiler does not know which PLL clock output is fed to an external output pin or fed back to the Stratix or Stratix GX device fbin pin. For example, if an APEX II, APEX 20KE, or APEX 20KC design with an altclklock megafunction uses the clock0 output port to feed the external clock output pin and the clock1 output port to feed the internal logic array, the Quartus II software generates an error during compilation and you must use the MegaWizard Plug-In Manager to instantiate the altpll megafunction. By using the altpll megafunction, you can choose which of the four external clock outputs to use and take advantage of the new Stratix and Stratix GX PLL features now available in the zero delay buffer mode or external feedback mode.
Timing Analysis
When the Quartus II software performs a timing analysis for APEX II, APEX 20KE, or APEX 20KC designs, PLL clock settings override the project clock settings. However, during timing analysis for Stratix and Stratix GX designs using PLLs, the project clock settings override the PLL input clock frequency and duty cycle settings. The MegaWizard Plug-In Manager does not use the project clock settings to determine the altpll parameters. This saves time with designs that use features such as clock switchover or PLL reconfiguration because the Quartus II software can perform a timing analysis without recompiling the design. It is important to note the following:
A warning during compilation reports that the project clock settings overrides the PLL clock settings. The project clock setting overrides the PLL clock settings for timingdriven compilation. The compiler will check the lock frequency range of the PLL. If the frequency specified in the project clock settings is outside the lock frequency range, the PLL clock settings will not be overridden. Performing a timing analysis without recompiling your design does not change the programming files. You must recompile your design to update the programming files.
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A Default Required fMAX setting does not override the PLL clock settings. Only individual clock settings override the PLL clock settings.
Therefore, you can enter different project clock settings corresponding to new PLL settings and accelerate timing analysis by eliminating a full compilation cycle.
For more information about using Stratix and Stratix GX PLLs, see the General-Purpose PLLs in Stratix & Stratix GX Devices chapter. The Stratix and Stratix GX I / O element (IOE) architecture is similar to the APEX II architecture, with a total of six registers and a latch in each IOE. The registers are organized in three sets: two output registers to drive a single or double-data rate (DDR) output path, two input registers and a latch to support a single or DDR input path, and two output enable registers to enhance clock-to-output enable timing or for DDR SDRAM interfacing. A new synchronous reset signal is available to each of the three sets of registers for preset or clear, or neither. In addition to the advanced IOE architecture, the Stratix and Stratix GX IOE features dedicated circuitry for external RAM interfacing, new I / O standards, differential on-chip termination, and high-speed differential I / O standard support.
I / O Structure
External RAM Interfacing
The advanced Stratix and Stratix GX IOE architecture includes dedicated circuitry to interface with external RAM. This circuitry provides enhanced support for external high-speed memory devices such as DDR SDRAM and FCRAM. The DDR SDRAM interface uses a bidirectional signal, DQS, to clock data, DQ, at both the transmitting and receiving device. Stratix and Stratix GX devices transmit the DQS signal with the DQ data signals to minimize clock to data skew. Stratix and Stratix GX devices include groups of programmable DQS and DQ pins, in the top and bottom I / O banks of the device. Each group consists of a DQS pin that supports a fixed number of DQ pins. The number of DQ pins depends on the DQ bus mode. When using the external RAM interfacing circuitry, the DQS pin drives a dedicated clock network that feeds the DQ pins residing in that bank. The Stratix and Stratix GX IOE has programmable delay chains that can phase shift the DQS signal by 90° or 72° to ensure data is sampled at the appropriate point in time. Therefore, the Stratix and Stratix GX devices make full use of the IOEs, and remove the need to build the input data path in the logic array. You can make these I / O assignments in the Quartus II Assignment Organizer.
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I / O Structure
For more information on external RAM interfacing, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet in the Stratix GX Device Family Handbook.
I / O Standard Support
The Stratix and Stratix GX devices support all of the I / O standards that APEX II and APEX 20K devices support, including high-speed differential I / O standards such as LVDS, LVPECL, PCML, and HyperTransport technology, differential HSTL on input and output clocks, and differential SSTL on output clocks. Stratix and Stratix GX devices also introduce support for SSTL-18 class I & II. Similar to APEX II devices, Stratix and Stratix GX devices only support certain I / O standards in designated I / O banks. In addition, vref pins are dedicated pins in Stratix and Stratix GX devices and now support up to 40 input pins.
For more information about I / O standard support in Stratix and Stratix GX devices, see the Selectable I / O Standards in Stratix & Stratix GX Devices chapter.
High-Speed Differential I / O Standards
Stratix and Stratix GX devices support high-speed differential interfaces at speeds up to 840 Mbps using high-speed PLLs that drive a dedicated clock network to the SERDES. Each fast PLL can drive up to 20 highspeed channels. Stratix and Stratix GX devices use enhanced PLLs and M512 RAM blocks to provide up to 420 Mbps performance for SERDES bypass clock interfacing. There is no restriction on the number of channels that can be clocked using this scenario. Stratix and Stratix GX devices have a different number of differential channels than APEX II devices. Tables 3-9 and 3-10 highlight the number of differential channels supported in Stratix and Stratix GX devices.
Table 3-9. Number of Dedicated DIfferential Channels in Stratix Devices (Part 1 of 2) Note (1) Device
EP1S10
Pin Count
Number of Receiver Channels
Number of Transmitter Channels
EP1S20
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Table 3-9. Number of Dedicated DIfferential Channels in Stratix Devices (Part 2 of 2) Note (1) Device
EP1S25
Pin Count
Number of Receiver Channels
Number of Transmitter Channels
EP1S30
EP1S40
EP1S60
EP1S80
Note to Table 3-9:
(1) For information on channel speeds, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 and the High-Speed Differential I / O Interfaces chapter in the Stratix Device Handbook, Volume 2.
Table 3-10. Number of Dedicated DIfferential Channels in Stratix GX Devices (Part 1 of 2) Note (1) Device
EP1SGX10 C EP1SGX10 D
Pin Count
Number of Transceivers
Number of SourceSynchronous Channels
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I / O Structure
Table 3-10. Number of Dedicated DIfferential Channels in Stratix GX Devices (Part 2 of 2) Note (1) Device
EP1SGX25 C EP1SGX25 D EP1SGX25 F EP1SGX40 D EP1SGX40 G Note to Table 3-10:
(1) For information on channel speeds, see the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 and the High-Speed Source-Synchronous Differential I / O Interfaces in Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2.
Pin Count
Number of Transceivers
Number of SourceSynchronous Channels
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For more information on differential I / O support, data realignment, and the transmitter clock output in Stratix and Stratix GX devices, see the High-Speed Differential I / O Interfaces in Stratix Devices chapter.
altlvds Megafunction
To take full advantage of the high-speed differential I / O standards available in Stratix and Stratix GX devices, you should update each instance of the altlvds megafunction in APEX II, APEX 20KE, and APEX 20KC designs. In the MegaWizard Plug-In Manager, choose the altlvds megafunction, select Stratix or Stratix GX as the target device family, update the megafunction, and recompile your design. The altlvds megafunction supports new Stratix and Stratix GX parameters that are not available for APEX II, APEX 20KE, and APEX 20KC devices. Tables 3-11 and 3-12 describe the new parameters for the LVDS receiver and LVDS transmitter, respectively.
Table 3-11. New altlvds Parameters for Stratix LVDS Receiver Note (1) Parameter
Function
Indicates the fast PLL can be shared between receiver and transmitter applications.
Table 3-12. New altlvds Parameters for Stratix LVDS Transmitter (Part 1 of 2) Note (1) Parameter
Function
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Configuration
Table 3-12. New altlvds Parameters for Stratix LVDS Transmitter (Part 2 of 2) Note (1) Parameter
Notes to Tables 3-11 and 3-12:
(1) (2) (3) You can specify these parameters in the MegaWizard Plug-In Manager. You must specify a data rate in the MegaWizard Plug-In Manager instead of a W factor. The same fast PLL can be used to clock both the receiver and transmitter only if both are running at the same frequency.
Function
Indicates the fast PLL can be shared between receiver and transmitter applications.
Above the standard I / O offered by APEX II, APEX 20K, and Stratix devices, Stratix GX devices provide up to 20 3.175 Gbps transceivers. The transceivers provide high-speed serial links for chip-to-chip, backplane, and line-side connectivity and support a number of the emerging high-speed protocols. You can find more information in the Stratix GX Family Data Sheet in the Stratix GX Family Handbook, Volume 1.
Configuration
The Stratix and Stratix GX devices supports all current configuration schemes, including the use of enhanced configuration devices, passive serial (PS), passive parallel asynchronous (PPA), fast passive parallel (FPP), and JTAG. Stratix and Stratix GX devices also provide a number of new configuration enhancements that you can take advantage of when migrating APEX II and APEX 20K designs to Stratix and Stratix GX devices.
Configuration Speed & Schemes
You can configure Stratix and Stratix GX devices at a maximum clock speed of 100 MHz, which is faster than the 66-MHz and 33-MHz maximum configuration speeds for APEX II and APEX 20K devices, respectively. Similar to APEX II devices, you can use 8-bit parallel data to configure Stratix and Stratix GX devices (the target device can receive byte-wide configuration data on each clock cycle) significantly speeding up configuration times. You can select a configuration scheme based on how the MSEL pins are driven. Stratix and Stratix GX devices have three MSEL pins (APEX II and APEX 20K devices have two MSEL pins) for determining the configuration scheme.
For more information about Stratix and Stratix GX configuration schemes, see the Configuring Stratix & Stratix GX Devices chapter.
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Remote Update Configuration
The APEX 20K device family introduced the concept of remote update configuration, where you could send the APEX 20K device new configuration files from a remote source and the device would store the files in flash memory and reconfigure itself with the new configuration data. The Stratix and Stratix GX devices enhance support for remote update configuration with new, dedicated circuitry to handle and recover from errors. If an error occurs either during device configuration or in user mode, this new circuitry reconfigures the Stratix or Stratix GX device to a known state. Additionally, the Stratix and Stratix GX devices have a user watchdog timer to ensure the application configuration data executes successfully during user mode. User logic must continually reset this watchdog timer in order to validate that the application configuration data is functioning properly.
For more information about how to use the remote and local update modes, see the Remote System Configuration with Stratix & Stratix GX Devices chapter.
JTAG Instruction Support
Table 3-13. JTAG Instruction Support (Part 1 of 2) JTAG Instruction
SAMPLE / PRELOAD EXTEST BYPASS USERCODE IDCODE ICR Instructions
Stratix
APEX II
APEX 20K
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Conclusion
Table 3-13. JTAG Instruction Support (Part 2 of 2) JTAG Instruction
Stratix
APEX II
APEX 20K
Conclusion
The Stratix and Stratix GX devices extend the advanced features available in the APEX II and APEX 20K device families to deliver a complete system-on-a-programmable-chip (SOPC) solution. By following these guidelines, you can easily transition current APEX II and APEX 20K designs to take advantage of the new features available in Stratix and Stratix GX devices.
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4. Stratix GX Board Design Guidelines
SGX53001-1.0
Introduction
Digital board design has become more complicated over the years. Devices have 0.13-m gate lengths and are powered by 1.5-V power supplies. While the trend toward miniaturization continues, device speeds are increasing. FPGAs now have embedded transceivers that can support serial data transmission at 3.125 Gigabits per second (Gbps). The low-voltage supply results in decreased noise margin therefore, small voltage noise on the board can cause a bit to flip. Similarly, voltage noise directly increases the clock jitter, which reduces the timing margin. If the jitter is large enough, the bit transition boundaries can become fuzzy, and the current data bit could be confused for the past or future bit. To reduce voltage and timing noise and ensure error-free data transmission, good design techniques are essential. The following things are critical when designing a successful high-speed digital board:
Clean power supply design (see "Power Circuitry" on page 4-6) Decoupling capacitor selection (see "Decoupling Circuitry Design" on page 4-13) Analog ground and power isolation (see "Ground Plane & Island Design" on page 4-30) Transmission line termination (see "Transmission Line Termination" on page 4-52) Crosstalk minimization (see "Crosstalk" on page 4-72) Impedance discontinuity minimization (see "Transmission Line Routing" on page 4-58) Proper differential signal routing (see "Transmission Line Routing" on page 4-58)
This document explains high-speed board design concepts and techniques as applied to Stratix® GX devices and explains the major aspects of successful high-speed board design. The Stratix GX device and the Stratix GX development board are used as the platforms for the tests and measurements described in this document. Topics covered include clock circuitry design, power circuitry design, power supply decoupling, transmission line topologies, length matching, AC versus DC coupling, termination techniques, time domain reflectometer (TDR) usage, and Sparameters.
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Introduction
Board Design Overview
A typical high-speed board design begins with a product requirements document, a concept review, and a functional specification. After the specification is finalized, actual system design begins with the selection of key components. At this point, timing analysis for all the interfaces and power analysis-to determine the power requirements-is performed. Based on the power analysis, power supply modules and regulators are chosen, and a decoupling scheme is specified. Based on the timing analysis, length-matching criteria for the buses is established. Upon completion of these tasks, as well as completion of the system design and selection of remaining components, the schematics are created. These are typically reviewed among engineers who make any necessary changes, after which they are given to the layout designer. A layout guidelines document, which specifies how to place components on the board and how to route the traces, is created and given to the layout designer as well. A pre-layout simulation is performed to determine the ideal stackup, trace widths, spacing, and other routing requirements. Any changes to the schematic, based on the simulation results, are incorporated in the schematic and provided to the layout designer. When the layout is complete, a post-layout simulation is performed on the critical sections of the board to ensure that there are no major signal integrity problems. Based on the results of the post-layout simulation, any changes required are incorporated into the layout, and finally the layout is released to the fabrication house for board manufacturing. Figure 4-1 shows a typical board design process.
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Figure 4-1. Simplified View of a Typical High-Speed Board Design Process
Product Requirements
Function Specifications Document is Created
System Design Begins
Components are Specified and Selected
Schematic is Finalized
Post-Layout Simulation is Performed
Layout Design
Pre-Layout Simulation is Performed
Board Parameters and / or Stackup is Adjusted
Board is Handed-Off to Fab House
Fab House Manufactures the Boards
Board is Sent Back to the Fab House to Fix Problems
Yes No
Board goes to Assembly
Board is Sent Back to Assembly House to Fix Problems
Assembled Board is Tested by the Engineer
Design is Complete Characterization Follows
Support Circuitry Design
Support circuitry includes clocks, power, and decoupling. This section contains detailed guidelines for designing these parts of a high-speed board.
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Support Circuitry Design
Clock Circuitry
Place the crystal oscillator close to the driver circuitry for best jitter performance. Route the differential clock lines tightly coupled to each other. The oscillators and the drivers need clean power supplies. Place series termination at the clock output if the trace is too long. Place parallel differential termination close to the receiver pins.
1 inches / ps 85 0.475 r + 0.67
1 Some designers
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inches / ps
LVTTL to LVDS driver Termination resistor for SMA clock trace XTAL Output (Short trace, no termination required)
XTAL Trace from SMA clock input (Long trace, termination required)
The specifications for some I / O standards always require termination regardless of the trace length. These include PCML, LVDS, LVPECL, SSTL-II, and HSTL-II.
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Support Circuitry Design
Isolated Power & Ground Plane Design
Power Circuitry
As gate lengths shrink, the power supply voltages of transistors also decrease. As a result, the noise margin also decreases. The reduced noise margin makes the transistors even more sensitive to noise on the power supply. The features of the board must be understood before the power supply can be designed. Some key characteristics of a high-density board with one or more FPGAs include:
Regulator Selection
Altera recommends selecting linear regulators as much as possible, because they are easy to design and their performance is less critical to layout. You must sometimes select switching regulators, because linear
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regulators cannot supply the desired amount of power efficiently. In those cases, you must design and layout the switching regulators very carefully. All major switching components and traces must be closely contained on the same layer. The Stratix GX development board uses Fairchild FAN5066 switching regulators (U36 and U37) for 3.3-V and 1.5-V digital supplies. Refer to "Switching Regulator Layout Example" on page 4-8 for details on the layout of these regulators on the Stratix GX development board. To support a board with the characteristics listed earlier, the power circuitry must be able to do the following:
Supply large amounts of current to the core and I / O voltages. Supply clean power and ground to sensitive analog components such as PLLs and transceivers. Maintain good efficiency to prevent excess heat dissipation on the regulators.
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Support Circuitry Design
Switching Regulator Layout Example
Linear regulators are relatively easy to design and lay out. Switching regulators, on the other hand, require a great deal of care. Typically schematics for both the linear and switching regulators can be taken directly from the vendor data sheet or the application note. Some of the linear regulators Altera recommends include Micrel MIC29502BU, National LMS1585 and National LP2995M. Similarly, Altera has used Fairchild FAN5066 for switching regulators with good results. With switching regulators, component layout is extremely important. To explain this point further, consider an actual example. Figure 4-3 shows a capture plot of the FAN5066 circuit from the Stratix GX development board. This switching regulator runs from a 5.0-V supply and can generate an output voltage that equals the voltage reference. Set the reference voltage on the board by applying the required voltage on the CNTRL pin (pin 16). The 12.0-V supply is used only for biasing and draws very little current. The overall circuitry consists of the FAN5066 switching controller, external FETs (Q3 and Q4) to boost the current output capability, and the associated resistors, diodes, inductors, and capacitors as recommended by the manufacturer. The switching regulator is essentially a feedback loop consisting of a pulse width modulator (PWM). The feedback loop compares the actual output voltage to the desired voltage (reference voltage). If the actual output is less than desired, then the high drive (HIDRV) output is asserted, which turns the upper field effect transistor (FET) on and charges the output capacitor (C73). The end result is that the output voltage climbs. If the actual output is more than desired, the low drive (LODRV) output is asserted, which turns the lower FET on and discharges the output capacitor (C73). The end result is that the output voltage drops. In steady state the output voltage equals the input reference voltage. Figure 4-4 shows the schematic of the switching regulator used in the SGX development board.
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Figure 4-3. Switching Regulator Schematic
Make This Trace as Short as Possible
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Support Circuitry Design
Figure 4-4. Switching Regulator Layout
Output Capacitor (C73) DC-DC Driver Fan 5066 (U37)
Output Inductor (L37)
Lower FET (Q4)
Upper FET (Q3)
Input Capacitor (C57)
Figures 4-5 through 4-7 show the waveforms at the gates of the upper and the lower FET. While the lower FET switches from about 0 V to 5 V, the upper FET switches from approximately 0 V to 10 V. These are large magnitudes on a board with 3.3-, 2.5-, or 1.5-volt logic signals. Routing fast switching signals close to sensitive analog and digital signals and across multiple layers can cause the switching signals to radiate energy to other critical traces. Consequently, it is very important to contain the large switching signals compactly on the same layer.
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Figure 4-5. Switching Waveforms at the Output of the FET
Figure 4-6. Switching Waveforms at the Gate of the Upper FET
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Support Circuitry Design
Figure 4-7. Switching Waveforms at the Gate of the Lower FET
Altera has compared the performance improvement of the output ripple when using a good layout versus a poor layout. The results of excessive ripple at the output of a switching regulator because of poor board layout, are shown in Figure 4-8. The output ripple is almost 1.5 V peak to peak. This example may be an extreme case, but the board in this example was designed with an intentionally poor layout. The layout was later improved by reducing the length of the HIDRV and LODRV signals and minimizing via count to determine how much improvement would result. With the improved layout, the noise decreased to about 71 mV peak to peak.
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Figure 4-8. Excessive Ripple at the Output of a Switching Regulator
Altera recommends that you follow the switching regulator layout of the Stratix GX development board and review the Fairchild Semiconductor FAN5066 data sheet in detail. The guidelines are summarized here:
Place all components on the same layer, if possible. Minimize the trace lengths for the gate drives (HIDRV and LODRV). Place all the 0.1 F decoupling capacitors close to the pins. Place the HIDRV, LODRV, VCCQP and the FET output traces far away from the analog sections of the chip, including VCNTRL (pin 16), VFB, and IFB (feedback pins 4 and 5), and CEXT (pin 1). Do all routing for the switching signals (VCCQP, HIDRV, LODRV, and FET output) on the component layer to avoid radiation to multiple layers through the vias. Surround the capacitor connected to pin 1 (CEXT) with a ground guard trace and place a ground plane beneath it.
Decoupling Circuitry Design
You can divide decoupling capacitor circuitry into two categories: bulk decoupling and local decoupling. Bulk decoupling uses large decoupling capacitors (often tens to hundreds of microfarads), usually placed close to the regulators and designed to work for low frequencies. Local decoupling involves smaller capacitors (typically 2.2 F, 0.1 F, or 0.01 F) that are placed close to the chips and are designed to decouple high frequency noise from the power supply.
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Support Circuitry Design
Determining the number of decoupling capacitors depends on the expected current draw from the power supply, the rate of current change, and the desired impedance between the power plane and the ground plane at the frequency of interest. For switching (or sometimes even linear) regulators, the manufacturers specify a certain minimum bulk decoupling at the output of the regulator for stability and for ensuring a clean output.
Bulk Decoupling
The amount of bulk decoupling needed depends on the number of outputs switching, the load capacitance, the slew rate, and the inductance of the planes and routing traces and vias. Estimate the amount of bulk decoupling needed as follows: 1. Determine the worst case current draw on the power net. This draw depends on how many gates can switch at the same time and how much load they need to drive. For example, assume there are 100 3.3-V LVTTL I / O pins switching, each with 11.5 pF loads, and the switch is completed in 1 ns. (These values are fairly typical for Stratix and Stratix GX devices.) The total worst case current required is:
Table 4-1. LVTTL Parameters (Part 1 of 2) Symbol
Parameter
Output supply voltage High-level input voltage
Conditions
Minimum Maximum Units
3.0 1.7 3.6 4.1 V V
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Table 4-1. LVTTL Parameters (Part 2 of 2) Symbol
Parameter
Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum Maximum Units
-0.5 0.7 V V 0.45 V
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Support Circuitry Design
Finally, use this equation to calculate the value of the decoupling capacitor:
Local Decoupling
Local decoupling is designed to work at high frequencies. Unfortunately, at high frequencies, discrete capacitors are rarely effective by themselves. There must be a combination of discrete capacitors and plane capacitance. The analysis is quite involved and its accuracy is not easy to verify. So, experimental data is more helpful for creating design guidelines. Altera has conducted several experiments on this topic. Based on these experiments, Altera recommends about one decoupling capacitor per power pin. The results of simulations using Agilent design system (ADS) software determined the values of capacitors required. The amount of local decoupling is more difficult to determine, because high frequency effects are more pronounced for local decoupling. Altera recommends using one capacitor per power pin. More detailed guidelines for specific situations will be available in the near future. You should not mix values of capacitors, because doing so can create resonant peaks of impedances. In most cases it is best to choose the highest value of the capacitance available in the package required by the designer.
Simulating Decoupling Circuits
The efficacy of a decoupling scheme is indicated by the impedance between the power plane and the ground plane across the frequency of interest. The goal of a power supply decoupling scheme is to achieve the lowest possible impedance across the frequency of interest. If the impedance is low, then the noise on the power rail is shunted to the ground, whereas if the impedance is high, the noise stays on the power rail and can cause the circuitry to malfunction.
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In this simulation, Altera placed 25 decoupling capacitors of different values in parallel and measured the impedance from 1 MHz to 10 GHz. The frequency of interest can be different for each application, so focus on the frequency band of interest for your application. Using 25 decoupling capacitors gives a realistic number of capacitors used in a typical decoupling scheme. The behavior of vias, pads, and traces were captured using the multilayer transmission line models of ADS, which considers the dielectric material and its dissipative losses. Eight different cases, summarized in Table 4-2, were simulated to get a wide range of capacitor ratios.
Table 4-2. Simulation Cases Number of Capacitors Case 470 pF
1000 pF
0.01 F
Waveform Name 2.2F
Figure 4-9 shows the simulation setup with only one capacitor (only one capacitor is shown for clarity), including the parasitics, pads, routing trace to the vias, and the vias themselves. For the cases shown in Table 4-2, the model of the capacitor shown in Figure 4-9 was applied repeatedly in parallel. Each capacitor is modeled as a series RLC circuit. The parasitic resistance (R) and the parasitic inductance (L) were obtained from the data sheet published by the manufacturer of the capacitor. The capacitor pads on the board were modeled as 42-mil by 32-mil square pads. The vias were modeled as circular vias with pad diameters of 20 mils and hole diameters of 10 mils. The routing distance from the capacitor pad to the via was modeled as a trace, 50 mils long and 25 mils wide, equal to the total distance for routing on both sides of the capacitor. These are typical values and were extracted from the Stratix GX development board layout design.
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Support Circuitry Design
Figure 4-9. Simulation Setup for One Capacitor
Table 4-3 shows the extracted models of 470 pF, 1000 pF, 0.01 F, 0.1 F, and 2.2 F capacitors from the vendor datasheets (Panasonic and AVX). Table 4-3. Extracted Models of Capacitor Parasitics Capacitor Value
0.1 F 0.01 F 2.2 F 470 pF 0.001 F
Part Number
ECJ1VB1C104K ECJ1VB1C103K 08056D225KAT2A ECJ-0EB1E471K ECJ-1VB1H102K
Vendor
Panasonic Panasonic AVX / Kyocera Panasonic Panasonic
Parasitic L (nH)
Parasitic R ()
SRF (MHz)
Figure 4-10 shows the simulated impedance profile for the eight cases listed in Table 4-2.
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Figure 4-10. Impedance Simulation Results From Table 4-2
mag mag
1E8 freq, Hz
The following observations were made:
Decoupling at very high frequencies cannot be achieved by discrete capacitors. It must be done with a sandwiched power and ground plane. Traditionally, the number of capacitors is doubled for every lower decade in value. For example, beginning with one 0.1 F capacitor, you would use two 0.01 F capacitors. Case 1 in Table 4-2 on page 4-17 approximates this behavior. However, this approach often performs worse than when using equal numbers of capacitors of equal values, or even reversing the ratio (number of capacitors halved for each decade lower in value). Using a very large number of values can cause resonance spikes at multiple frequencies, so use as few values as possible to contain the magnitude of the resonance spike.
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Using all 2.2 F capacitors gives the lowest impedance profile without any resonance spikes. Although 1000 pF capacitors (when used in conjunction with 2.2 F caps) do give the low impedance dip at higher frequencies, they also result in the corresponding resonance spike.
To study how the ratio of 2.2 F versus 1000 pF capacitors affects the impedance profile, Altera performed further simulations. Figure 4-11 shows the impedance profiles when using all 24 2.2-F caps versus using a mix of 2.2 F and 1000 pF. Only 24 capacitors were used in this simulation as opposed to 25, allowing for easy ratios. This difference is not significant. The lower red graph in Figure 4-11 shows the case when all 24 capacitors are 2.2 F. It has the smoothest impedance profile and is lower in impedance than other cases, except for a dip at 129 MHz. If a particular board has significant noise at the frequency of the dip (approximately 129 MHz), a 1000 pF capacitor is helpful. However, you must ensure that there is negligible noise at the resonant peaks. The resonant peaks occur at 54 MHz, 75 MHz, 92 MHz, 106 MHz, and 118 MHz, depending on the ratio of 1000 pF caps to 2.2 F caps. Figure 4-11. Impedance Profile With a Combination of 2.2 F & 0.001 F Capacitors
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Based on the simulation results, it is important to select the highest value possible in a particular package, because these capacitors have the lowest impedance for the largest band of frequency. Examples include 2.2 F, 1.0 F, and 0.1 F. Do not go lower than that unless there is a compelling reason to do so, such as the presence of a strong noise spike at the exact frequency where the lower value capacitor resonates. Also, do not mix capacitor values (for example using 10 of 0.1 F and 10 of 0.001 F). This mixing can create undesired resonances. The Stratix GX development board uses many mixed capacitor values for decoupling, not because it is the best approach but because it allows the flexibility to test several approaches and values.
Plane Capacitance
For very high frequencies (above 300 MHz), decoupling using discrete capacitors is less effective. Use power plane capacitance for decoupling noise at these frequencies. You can understand the concept of plane capacitance by studying the classic parallel plate capacitor, shown in Figure 4-12. Figure 4-12. Parallel Plane Capacitance
Power Island
Ground Plane
An electric field is created when there is a power plane next to a ground plane. The upper area in Figure 4-12 shows the power island or plane, the lower area shows the ground plane, and the arrows represent the electric field lines. This electric field gives rise to a capacitance, the magnitude of which is shown by:
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where
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Ground Island (Layer 12) Power Plane (Layer 11)
Figures 4-14 and 4-15 show the reduction in noise after adding the islands. The addition of the islands reduced the noise from 70 mV p-p to less than 50 mV p-p under the same experimental conditions.
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Plane & Island Design
The following sections discuss various issues related to the design of power planes, ground planes, and power and ground islands.
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Power Plane & Island Design
Stratix GX devices have many power and ground pins, and it is important to know how to connect them on the board. Table 4-4 shows the list of power and ground pins and how they connect on the Stratix GX development board. For the actual pin numbers, refer to the pin tables at www.altera.com.
Table 4-4. Stratix GX Power & Ground Pins (Part 1 of 2) Pin Name
Description
Digital power for Stratix GX transceiver quads (banks) 13 through 17 Transmitter power for Stratix GX transceiver quads (banks) 13 through 17 Receiver power for Stratix GX transceiver quads (banks) 13 through 17 Power for Stratix GX transceiver quads (banks) 13 through 17 guard rings. Analog power for Stratix GX transceiver quads (banks) 13 through 17. PLLs
Voltage
1.5 V (linear)
3.3 V (linear)
PLL output buffer supply for PLL5 outputs 1.0 PLL output buffer supply for PLL5 outputs 3.2
1.5 V (linear) 1.5 V (linear) 3.3 V, 2.5 V or 1.5 V (1) (linear) 3.3 V, 2.5 V or 1.5 V (1) (linear)
PLL output buffer supply for PLL6 outputs 1.0 PLL output buffer supply for PLL6 outputs 3.2 Digital power supply for device internal power Power supply for I / Os in the banks 8, 7, 4.1
3.3 V, 2.5 V or 1.5 V (1) (linear)
VCCINT VCCIO8.7, 4.1
1.5 V (linear or switching) Variable (2) (linear or switching)
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Table 4-4. Stratix GX Power & Ground Pins (Part 2 of 2) Pin Name
Description
Ground for the guard rings of PLLs 1, 2, 5, 6, 8, 11, and 12 11, and 12
Voltage
Ground for the high-speed circuitry in the 3.125 Gbps transceivers General-purpose ground
Notes for Table 4-4:
Table 4-5. Islands Used for Stratix GX Transceiver Quads (Part 1 of 2) Islands
Island 1 Island 2 Island 3
Quads
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Table 4-5. Islands Used for Stratix GX Transceiver Quads (Part 2 of 2) Islands
Island 4 Island 5 Island 6 Island 7
Quads
Note to Table 4-5:
(1) Island 5 is required only for the 5-quad devices.
Figure 4-16 shows a block diagram of the islands.
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Figure 4-16. Block Diagram Representation for Quad Isolation
Island 1
Island 2
Ferrite Beads
Island 3
1.5V Linear Regulator
Island 4
Island 5 (Only for 5-Quad Devices)
Island 6
Island 7
Note to Figure 4-16:
(1) Island 5 is required only for the 5-quad devices.
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Figure 4-17. Section of Schematic Showing the Islands for the Transceiver Quads
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Figure 4-18. Layout of the Islands for the Transceiver Quads
Ground Plane & Island Design
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