Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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Athlon64 Dual-Core Processor Product Data Sheet
Compatible with Existing 32-Bit Code Base Including support SSE, SSE2, SSE3 MMXTM, 3DNow!technology legacy instructions *SSE3 supported later processors. Runs existing operating systems drivers Local APIC on-chip
Power Management Multiple low-power states including C1E* *C1E supported Rev. later processors. System Management Mode (SMM) ACPI-compliant, including support processor performance states
AMD64 Technology AMD64 technology instruction extensions 64-bit integer registers, 48-bit virtual addresses, 939-Pin Package Specific Features 40-bit physical addresses Eight additional 64-bit integer registers total) Refer Functional Data Sheet, Eight additional 128-bit SSE/SSE2/SSE3 registers 939-Pin Package, order# 31411, functional, total) electrical, mechanical details 939-pin package processors. Dual-Core Architecture Discrete cache structures each core Electrical Interfaces HyperTransportTechnology Devices 16-bit link supporting speeds (2000 MT/s) Gigabytes/s each direction 64-Kbyte 2-Way Associative ECC-Protected Data Caches 64-bit operations cycle, 3-cycle latency 64-Kbyte 2-Way Associative Parity-Protected Instruction Caches With advanced branch prediction 16-Way Associative ECC-Protected Caches Exclusive cache architecture-storage addition caches Mbyte cache Machine Check Architecture Includes hardware scrubbing major ECC-protected arrays HyperTransporttechnology: LVDS-like differential, unidirectional SDRAM: SSTL_2 JEDEC specification Clock, reset, test signals also SDRAM-like electrical specifications
Packaging 939-pin lidded micro 1.27-mm pitch 31x31-row array 40mm 40mm organic substrate Organic attach Integrated Memory Controller Low-latency, high-bandwidth 144-bit SDRAM 100, 133, 166, Supports four unbuffered DIMMs checking with double-bit detect single-bit correct
Publication Issue Date:
33425 January 2007
Revision:
3.10
Advanced Micro Devices
Athlon64 Dual Core Product Data Sheet
33425
Rev. 3.10 January 2007
Socket Specific Features
Refer Socket Processor Functional Data Sheet, order# 31117, functional mechanical details socket processors. Refer Family Processor Electrical Data Sheet, order# 31119, electrical details socket processors. Electrical Interfaces HyperTransporttechnology: LVDS-like differential, unidirectional DDR2 SDRAM: SSTL_1.8 JEDEC specification Clock, reset, test signals also DDR2 SDRAM-like electrical specifications Packaging Lidded micro 31x31 grid array 1.27-mm pitch Compliant with RoHS Directive 2002/95/EC) with lead used only small amounts specifically exempted applications Integrated Memory Controller Low-latency, high-bandwidth 144-bit DDR2 SDRAM controller operating Supports four unbuffered DIMMs checking with double-bit detect singlebit correct
33425
Rev. 3.10 January 2007
Athlon64 Dual Core Product Data Sheet
Revision History
Date
January 2007 September 2006 June 2006
Revision
3.10 3.08 3.02
Description
Fourth Public release. Added support low-power state Rev. later processors. Third Public release. Added RoHS compliance statement. Added asterisk note SSE3. Public release. Added Socket Specific Features Created heading 939-Pin Package Specific Features Placed Electrical Interfaces, Packaging, Integrated Memory Controller bullets under 939-Pin Package Specific Features heading. Initial public release.
2005
3.00
2005 2007 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. information contained herein preliminary advance nature subject change without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, Arrow logo, Athlon combinations thereof, 3DNow! trademarks Advanced Micro Devices, Inc. HyperTransport licensed trademark HyperTransport Technology Consortium. trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.

Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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