SGX51002-1.1 Transceiver Blocks Stratix® devices incorporate
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Stratix Transceivers
SGX51002-1.1
Transceiver Blocks
Stratix® devices incorporate dedicated embedded circuitry right side device, which contains high-speed 3.1875-Gbps serial transceiver channels. Each Stratix transceiver block contains four full-duplex channels supporting logic transmit receive high-speed serial data streams. transceiver block uses channels deliver bidirectional point-to-point data transmissions with 3.1875 Gbps data transition channel. There transceiver channels available single Stratix device. Table shows number transceiver channels available each Stratix device.
Table 2-1. Stratix Transceiver Channels Device
EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
Number Transceiver Channels
Figure shows elements transceiver block, including four channels, supporting logic, buffers. Each transceiver channel consists receiver transmitter. supporting logic contains transmitter generate high-speed clock used four transmitters. receiver within each transceiver channel generates receiver reference clocks. supporting logic also contains state machines manage rate matching XAUI GIGE applications, addition channel bonding XAUI applications.
Altera Corporation June 2006
Figure 2-1. Stratix Transceiver Block
Note
Receiver Channel Logic Array Channel Transmitter Channel
Receiver Pins
Transmitter Pins
Receiver Channel Logic Array Channel Transmitter Channel
Receiver Pins
Transmitter Pins
Logic Array
XAUI Receiver State Machine
XAUI Transmitter State Machine
Channel Aligner State Machine
Transmitter
Logic Array
Receiver Channel Logic Array Channel Transmitter Channel
Receiver Pins
Transmitter Pins
Receiver Channel Logic Array Channel Transmitter Channel
Receiver Pins
Transmitter Pins
Notes Figure 2-1:
Each receiver channel CRU, which shown this diagram. more information, refer section "Receiver Path" page 2-13. possible transmitter clock inputs, refer section "Transmitter Path" page 2-5.
Stratix Device Handbook, Volume
Altera Corporation June 2006
Stratix Transceivers
Each Stratix transceiver channel consists transmitter receiver. transmitter contains following:
Transmitter Transmitter phase compensation FIFO buffer Byte serializer 8B/10B encoder Serializer (parallel serial converter) Transmitter output buffer
receiver contains following:
Input buffer Clock recovery unit (CRU) Deserializer Pattern detector word aligner Rate matcher channel aligner 8B/10B decoder Receiver logic array interface
Stratix transceiver functions through Quartus software. programmable pre-emphasis, programmable equalizer, programmable dynamically well. Each Stratix transceiver channel also capable BIST generation verification addition various loopback modes. Figure shows block diagram Stratix transceiver channel. Stratix transceivers provide physical coding sublayer (PCS) physical media attachment (PMA) implementation protocols such 10-gigabit XAUI GIGE. portion transceiver consists logic array interface, 8B/10B encoder/decoder, pattern detector, word aligner, rate matcher, channel aligner, BIST pseudo-random binary sequence pattern generator/verifier. portion transceiver consists serializer/deserializer, CRU, buffers.
Altera Corporation June 2006
Stratix Device Handbook, Volume
Channel Receiver Deserializer Word Aligner Clock Recovery Unit Channel Aligner Rate Matcher 8B/10B Decoder Byte Deserializer Phase Compensation FIFO
Note Figure 2-2:
Stratix Device Handbook, Volume
Receiver Reference Clock Receiver
Figure 2-2. Stratix Transceiver ChanneL
Channels
Note
There four transceiver channels transceiver block.
Transmitter Serializer Byte Serializer Phase Compensation FIFO 8B/10B Encoder Transmitter Transmitter Reference Clock
Altera Corporation June 2006
Stratix Transceivers
Transmitter Path
This section describes data path through Stratix transmitter (see Figure 2-2). Data travels through Stratix transmitter following modules:
Transmitter Transmitter phase compensation FIFO buffer Byte serializer 8B/10B encoder Serializer (parallel serial converter) Transmitter output buffer
Transmitter
Each transceiver block transmitter PLL, which receives reference clock generates following signals:
High-speed serial clock used serializer Slow-speed reference clock used receiver Slow-speed clock used logic array (divisible double-width mode)
INCLK clock input into transmitter PLL. There INCLK clock transceiver block. This clock either REFCLKB pin, routing, inter-transceiver routing line. section "Stratix Clocking" page 2-30 more information about intertransceiver lines. transmitter each transceiver block clocks circuits transmit path. transmitter also used train receiver PLL. transmit channels used transceiver block, transmitter turned off. Figure block diagram transmitter PLL.
Altera Corporation June 2006
Stratix Device Handbook, Volume
Figure 2-3. Transmitter Block Diagram
High Speed Clock Speed Clock
Note
Clock Driver
INCLK
Down
Charge Pump Loop Filter
Inter Quad Routing (IQ1) Inter Quad Routing (IQ0) Global Clks, Bus, Routing
Note Figure 2-3:
divider divides
Stratix Device Handbook, Volume
Dedicated Local REFCLKB
Altera Corporation June 2006
Stratix Transceivers
transmitter support 3.1875 Mbps. input clock frequency speed grade devices limited REFCLKB other clock routing resources. speed grade devices, maximum input clock frequency 312.5 with REFCLKB pin, maximum 156.25 other clock routing resources. optional PLL_LOCKED port available indicate whether transmitter locked reference clock. transmitter programmable loop bandwidth that high. loop bandwidth parameter statically Quartus software. Table lists adjustable parameters transmitter PLL.
Table 2-2. Transmitter Specifications Parameter
Input reference frequency range Data rate support Multiplication factor Bandwidth Note Table 2-2:
Multiplication factors only achieved with pre-divider REFCLKB pin.
Specifications
Mbps 3.1875 Gbps Low, high
Transmitter Phase Compensation FIFO Buffer
transmitter phase compensation FIFO buffer resides transceiver block boundary. This FIFO buffer compensates phase differences between transmitter reference clock (inclk) interface clock (tx_coreclk). phase difference between clocks must less than 360° interface clock must also frequency locked transmitter reference clock. phase compensation FIFO buffer four words deep cannot bypassed.
Byte Serializer
byte serializer takes double-width words bits) from interface converts them single width word bits) transceiver. transmit data path after byte serializer single width bits). byte serializer bypassed when single width mode bits) used interface.
Altera Corporation June 2006
Stratix Device Handbook, Volume
8B/10B Encoder
8B/10B encoder translates 8-bit wide data control enable into 10-bit encoded data. encoded data maximum length 8B/10B encoder bypassed. Figure diagrams encoding process. Figure 2-4. Encoding Process
ctrl
8b-10b conversion
sent last
sent first
Transmit State Machine
transmit state machine operates either XAUI mode GIGE mode, depending protocol used. GIGE Mode GIGE mode, transmit state machines convert idle ordered sets (/K28.5/, /Dx.y/) either /I1/ /I2/ ordered sets. /I1/ consists negative-ending disparity /K28.5/ (denoted /K28.5/-) followed neutral /D5.6/. /I2/ consists positive-ending disparity /K28.5/ (denoted /K28.5/+) negative-ending disparity /D16.2/ (denoted /D16.2/-). transmit state machines convert ordered sets match /C1/ /C2/, which configuration ordered sets. (/C1/ /C2/ defined (/K28.5/, /D21.5/) (/K28.5/, /D2.2/), respectively.) Both /I1/ /I2/ ordered sets guarantee negative-ending disparity after each ordered set. GIGE transmit state machine statically disabled Quartus software, even using GIGE protocol mode.
Stratix Device Handbook, Volume
Altera Corporation June 2006
Stratix Transceivers
XAUI Mode transmit state machine translates XAUI XGMII code group XAUI code group. Table shows code conversion.
Table 2-3. Code Conversion XGMII
XGMII
through
Code-Group
Dxx.y K28.0 K28.3 K28.5 K28.5 K28.4 K27.7 K29.7 K30.7
Description
Normal data Idle ||I|| Idle ||T|| Sequence Start Terminate Error Reserved code groups
IEEE 802.3 IEEE 802.3 reserved code reserved code groups groups Other value K30.7
Invalid XGMII character
XAUI idle code groups, /K28.0/ (/R/) /K28.5/ (/K/), automatically randomized based PRBS7 pattern with x7+x6+1 polynomial. /K28.3/ (/A/) code group automatically generated between idle code groups. idle randomization /A/, /K/, code groups done automatically transmit state machine.
Serializer (Parallel-to-Serial Converter)
serializer converts parallel 8-bit 10-bit data into serial stream, transmitting first. serialized stream then transmit buffer. Figure diagram serializer.
Altera Corporation June 2006
Stratix Device Handbook, Volume
Figure 2-5. Serializer
Low-speed parallel clock High-speed serial clock
Serial data output buffer)
Transmit Buffer
Stratix transceiver buffers support 1.5-V pseudo current mode logic (PCML) standard rate 3.1875 Gbps, across inches trace, across connectors. Additional standards, LVDS, 3.3-V PCML, LVPECL, supported when coupled. common mode output driver output buffer, shown Figure 2-6, consists programmable output driver programmable pre-emphasis circuit.
2-10 Stratix Device Handbook, Volume
Altera Corporation June 2006
Stratix Transceivers
Figure 2-6. Output Buffer
Serializer
Output Buffer
Programmable Pre-Emphasis Programmable Output Driver
Programmable Termination
Output Pins
Programmable Output Driver programmable output driver drive 1,600 Table shows available settings each termination value. dynamically statically set. output driver requires either internal external termination source.
Table 2-4. Programmable (Differential) Termination Setting
Note Table 2-4:
Note Setting (mV)
400, 800, 1000, 1200, 1400, 1600 480, 960, 1200, 1440 600, 1200, 1500
differential measured (see Figure 2-7).
Altera Corporation June 2006
2-11 Stratix Device Handbook, Volume
Figure 2-7. Differential
Single-Ended Waveform Positive Channel Negative Channel Ground
Differential Waveform
(VID (Differential) (single-ended)) p-n=0V
Programmable Pre-Emphasis programmable pre-emphasis module controls output driver boost high frequency components, compensate losses transmission medium, shown Figure 2-8. pre-emphasis dynamically statically set. There five possible pre-emphasis settings through with being highest being pre-emphasis. Figure 2-8. Programmable Pre-Emphasis Model
VS(p-p) VPP(p-p)
Time
Time
2-12 Stratix Device Handbook, Volume
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Stratix Transceivers
Pre-emphasis percentage defined VPP/VS where differential emphasized voltage (peak-to-peak) differential steady-state voltage (peak-to-peak). Programmable Transmitter Termination programmable termination statically Quartus software. values off. Figure shows setup programmable termination. Figure 2-9. Programmable Transmitter Termination
Programmable Output Driver
Receiver Path
This section describes data path through Stratix receiver (refer Figure page 2-4). Data travels through Stratix receiver following modules:
Input buffer Clock Recovery Unit (CRU) Deserializer Pattern detector word aligner Rate matcher channel aligner 8B/10B decoder Receiver logic array interface
Receiver Input Buffer
Stratix receiver input buffer supports 1.5-V PCML standard rate 3.1875 Gbps. Additional standards, LVDS, 3.3-V PCML, LVPECL supported when coupled. common mode input buffer receiver support Stratix GX-to-Stratix coupling.
Altera Corporation June 2006
2-13 Stratix Device Handbook, Volume
Figure 2-10 shows diagram receiver input buffer, which contains:
Programmable termination Programmable equalizer
Figure 2-10. Receiver Input Buffer
Programmable Termination Input Pins Programmable Equalizer Differential Input Buffer
Programmable Termination programmable termination statically Quartus software. Figure 2-11 shows setup programmable receiver termination. Figure 2-11. Programmable Receiver Termination
Differential Input Buffer
external termination, then receiver must externally terminated biased Figure 2-12 shows example external termination/biasing circuit.
2-14 Stratix Device Handbook, Volume
Altera Corporation June 2006
Stratix Transceivers
Figure 2-12. External Termination Biasing Circuit
Receiver External Termination Biasing Stratix Device
50/60/75- Termination Resistance
Receiver
R1/R2 {R2/(R1 RXIP RXIN
Receiver External Termination Biasing Transmission Line
Programmable Equalizer
programmable equalizer module boosts high frequency components incoming signal compensate losses transmission medium. There five possible equalization settings compensate 10", 20", 30", trace. These settings should interpreted loosely. programmable equalizer dynamically statically.
Receiver
Each transceiver block four receiver PLLs CRUs, each which dedicated receive channel. receive channel associated with particular receiver used, then receiver powered down channel. Figure 2-13 diagram receiver circuits.
Altera Corporation June 2006
2-15 Stratix Device Handbook, Volume
Figure 2-13. Receiver Circuit
Receiver
rx_locked
Low-Speed TX_PLL_CLK Inter Transceiver Routing (IQ2) CRUCLK Global Clks, Bus, Routing down down Charge Pump Loop Filter
Dedicated Local REFCLKB
rx_locktorefclk rx_locktodata RX_IN
rx_freqlocked[] rx_riv[ High-speed RCVD_CLK Low-speed RCVD_CLK
Note Figure 2-13:
receiver PLLs CRUs capable supporting 3.1875 Gbps. input clock frequency speed grade devices limited REFCLKB other clock routing resources. maximum input clock frequency speed grade devices 312.5 REFCLKB 156.25 with other clock routing resources. optional RX_LOCKED port (active signal) available indicate whether locked reference clock. receiver programmable loop bandwidth, which low, medium, high. loop bandwidth parameter statically Quartus software. Table lists adjustable parameters receiver CRU. parameters listed statically programmable Quartus software.
Table 2-5. Receiver Adjustable Parameters (Part Parameter
Input reference frequency range Data rate support
Specifications
Mbps 3.1875 Gbps
2-16 Stratix Device Handbook, Volume
Altera Corporation June 2006
Stratix Transceivers
Table 2-5. Receiver Adjustable Parameters (Part
Multiplication factor detector Bandwidth length detector 125, 250, 500, 1,000 Low, medium, high 10-bit 20-bit mode: steps 8-bit 16-bit mode: steps Note Table 2-5:
Multiplication factors only achieved with predivider REFCLKB port trained with speed clock from transmitter PLL.
built-in switchover circuit select whether voltage-controlled oscillator trained reference clock data. optional port rx_freqlocked monitors when locked data mode. automatic mode, following conditions must switch from locked reference locked data mode:
within prescribed frequency threshold setting (125 PPM, PPM, PPM, 1,000 PPM) reference clock. reference clock output phase matched (phases within UI).
automatic switchover circuit overridden using optional ports rx_lockedtorefclk rx_locktodata. Table shows possible combinations these signals.
Table 2-6. Possible Combinations rx_lockedtorefclk rx_locktodata rx_locktodata
rx_lockedtorefclk
(lock mode)
Auto Reference DATA
rx_lockedtorefclk rx_locktodata ports used, default auto mode.
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2-17 Stratix Device Handbook, Volume
Deserializer (Serial-to-Parallel Converter)
deserializer converts serial stream into parallel 10-bit data bus. deserializer receives least significant first. Figure 2-14 diagram deserializer. Figure 2-14. Deserializer
High-speed serial clock Low-speed parallel clock
Word Aligner
word aligner aligns incoming data based specific byte boundaries. word aligner three customizable modes operation: bit-slip mode, 16-bit mode, 10-bit mode, last which available basic SONET modes. word aligner also non-customizable modes operation, which XAUI GIGE modes. Figure 2-15 shows word aligner bit-slip mode.
2-18 Stratix Device Handbook, Volume
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Stratix Transceivers
Figure 2-15. Word Aligner Bit-Slip Mode
Word Aligner
Patterm Detector
Manual Alignment Mode
Bit-Slip Mode
10-Bit Mode
16-Bit Mode
7-Bit Mode
A1A2 Mode
A1A1A2A2 Mode
bit-slip mode, byte boundary modified barrel shifter slip byte boundary time user-controlled bit-slip port. bit-slip mode supports both 8-bit 10-bit data paths operating single double-width mode. pattern detector active bit-slip mode, detects user-defined pattern that specified MegaWizard® Plug-In Manager. bit-slip mode available only Custom mode SONET mode. Figure 2-16 shows word aligner 16-bit mode.
Altera Corporation June 2006
2-19 Stratix Device Handbook, Volume
Figure 2-16. Word Aligner 16-Bit Mode
Word Aligner
Pattern Detector
Manual Alignment Mode
16-Bit Mode
16-Bit Mode
A1A2 Mode
A1A1A2A2 Mode A1A2 Mode A1A1A2A2 Mode
16-bit mode, word aligner pattern detector automatically aligns detects user-defined 16-bit alignment pattern. This pattern format A1A2 A1A1A2A2 (for SONET protocol). re-alignment byte boundary done user-controlled port. 16-bit mode supports only 8-bit data path single-width double-width mode. 16-bit mode available only Custom mode SONET mode. A1A1A2A2 word alignment pattern option available only SONET mode cannot used Custom mode. Figure 2-17 shows word aligner 10-bit mode.
2-20 Stratix Device Handbook, Volume
Altera Corporation June 2006
Stratix Transceivers
Figure 2-17. Word Aligner 10-Bit Mode
Word Aligner
Pattern Detector
Manual Alignment Mode
10-Bit Mode
7-Bit Mode
10-Bit Mode
10-bit mode, word aligner automatically aligns user's predefined 10-bit alignment pattern. pattern detector detect full 10-bit pattern only lower seven bits pattern. word aligner pattern detector detect both positive negative disparity pattern. user-controlled enable port available word aligner. 10-bit mode available only Custom mode. Figure 2-18 shows word aligner XAUI mode.
Altera Corporation June 2006
2-21 Stratix Device Handbook, Volume
Figure 2-18. Word Aligner XAUI Mode
Word Aligner
Synchronization State Machines
GigE Mode
XAUI Mode
XAUI GIGE modes, word alignment controlled state machine that adheres IEEE 802.3ae standard XAUI IEEE 802.3 standard GIGE. alignment pattern predefined /K28.5/ code group. XAUI mode available only XAUI protocol, GIGE mode available only GIGE protocol.
Channel Aligner
channel aligner available only XAUI mode bonds four channels within transceiver. channel aligner adheres IEEE 802.3ae, clause specification channel bonding. channel aligner 16-word deep FIFO buffer with state machine overlooking channel bonding process. state machine looks (/K28.3/) each channel aligns /A/s transceiver. When four columns (denoted //A//) detected, rx_channelalign port goes high, signifying that channels transceiver have been bonded. reception four consecutive misaligned /A/s restarts channel alignment sequence de-asserts rx_channelalign. Figure 2-19 shows misaligned channels before channel aligner channel alignment after channel aligner.
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Stratix Transceivers
Figure 2-19. Before After Channel Aligner
Lane Lane
Lane
Lane
Lane
Lane
Lane
Lane
Rate Matcher
rate matcher, which available only XAUI GIGE modes, consists 12-word deep FIFO buffer FIFO controller. rate matcher bypassed when device XAUI GIGE mode. multi-crystal environment, rate matcher compensates 100-ppm difference between source receiver clocks. GIGE Mode GIGE mode, rate matcher adheres specifications clause IEEE 802.3 documentation, idle additions removals. rate matcher performs clock compensation only /I2/ ordered sets, composing /K28.5/+ followed /D16.2/-. rate matcher does perform clock compensation other ordered combinations. /I2/ added deleted automatically based number words FIFO buffer. 9'h19C given control data ports when FIFO overflow underflow condition.
Altera Corporation June 2006
2-23 Stratix Device Handbook, Volume
XAUI Mode XAUI mode, rate matcher adheres clause IEEE 802.3ae specification clock rate compensation. rate matcher performs clock compensation columns (/K28.0/), denoted //R//. //R// added deleted automatically based number words FIFO buffer.
8B/10B Decoder
8B/10B decoder converts 10-bit encoded code group into 8-bit data control bit. 8B/10B decoder bypassed. following diagram conversion from 10-bit encoded code group into 8-bit data 1-bit control. Figure 2-20. 8B/10B Decoder Conversion
received last 8b-10b conversion
received first
Parallel data
ctrl
There optional error status ports available 8B/10B decoder, rx_errdetect rx_disperr. Table shows values ports from given error. These status signals aligned with code group which error occurred.
Table 2-7. Error Signal Values Types Errors
errors Invalid code groups Disparity errors
rx_errdetect
1'b0 1'b1 1'b1
rx_disperr
1'b0 1'b0 1'b1
2-24 Stratix Device Handbook, Volume
Altera Corporation June 2006
Stratix Transceivers
Receiver State Machine
receiver state machine operates GIGE XAUI modes. GIGE mode, receiver state machine replaces invalid code groups with 9'h1FE. XAUI mode, receiver state machine translates XAUI code group XAUI XGMII code group. Table shows code conversion. conversion adheres IEEE 802.3ae specification.
Table 2-8. Code Conversion XGMII
IEEE 802.3 reserved code groups
XGMII
through Dxx.y
code-group
K28.0 K28.3 K28.5 K28.5 K28.4 K27.7 K29.7 K30.7 Invalid code group IEEE 802.3 reserved code groups Idle ||I||
Description
Normal Data
Idle ||T|| Sequence Start Terminate Error Invalid XGMII character Reserved code groups
Byte Deserializer
byte deserializer takes single width word bits) from transceiver logic converts into double-width words bits) phase compensation FIFO buffer. byte deserializer bypassed when single width mode bits) used interface.
Phase Compensation FIFO Buffer
receiver phase compensation FIFO buffer resides transceiver block programmable logic device (PLD) boundary. This buffer compensates phase difference between recovered clock within transceiver recovered clock after transferred core. phase compensation FIFO buffer four words deep cannot bypassed.
Altera Corporation June 2006
2-25 Stratix Device Handbook, Volume
Loopback Modes
Stratix transceiver built-in loopback modes debug testing. loopback modes Stratix MegaWizard Plug-In Manager Quartus software. Only loopback mode single instance transceiver block. loopback mode applies used channels transceiver block. available loopback modes are:
Serial loopback Parallel loopback Reverse serial loopback
Serial Loopback
Serial loopback exercises transceiver logic except output buffer input buffer. loopback function dynamically switchable through rx_slpbk port channel channel basis. output reduced. select output tri-stated when serial loopback option selected. Figure 2-21 shows data path serial loopback mode. Figure 2-21. Data Path Serial Loopback Mode
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
BIST Generator
Active Path Non-Active Path
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Stratix Transceivers
Parallel Loopback
parallel loopback mode exercises digital logic portion transceiver data path. analog portions loopback path. received data retimed. Figure 2-22 shows data path parallel loopback mode. This option dynamically switchable. Reception external signal possible this mode. Figure 2-22. Data Path Parallel Loopback Mode
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
BIST Generator
Active Path Non-Active Path
Reverse Serial Loopback
reverse serial loopback exercises analog portion transceiver. This loopback mode dynamically switchable through tx_srlpbk port channel channel basis. Asserting rxanalogreset reverse serial loopback mode powers down receiver buffer CRU, preventing data loopback. Figure 2-23 shows data path reverse serial loopback mode.
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2-27 Stratix Device Handbook, Volume
Figure 2-23. Data Path Reverse Serial Loopback Mode
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
Active Path Non-Active Path
BIST Generator
BIST (Built-In Self Test)
Stratix transceiver built-in self test modes debug testing. BIST modes Stratix MegaWizard Plug-In Manager Quartus software. Only BIST mode single instance transceiver block. BIST mode applies channels used transceiver. following list available BIST modes:
PRBS generator verifier Incremental mode generator verifier High-frequency generator Low-frequency generator Mixed-frequency generator
Figures 2-24 2-25 diagrams BIST PRBS data path BIST incremental data path, respectively.
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Stratix Transceivers
Figure 2-24. BIST PRBS Data Path
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
BIST Generator
Active Path Non-active Path
Figure 2-25. BIST Incremental Data Path
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
BIST Generator
Active Path Non-active Path
Table shows BIST data output verifier alignment pattern.
Table 2-9. BIST Data Output Verifier Alignment Pattern (Part BIST Mode
PRBS 8-bit PRBS 10-bit
Output
Polynomials
Verifier Word Alignment Pattern
1000000011111111 1111111111
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2-29 Stratix Device Handbook, Volume
Table 2-9. BIST Data Output Verifier Alignment Pattern (Part BIST Mode
PRBS 16-bit PRBS 20-bit Incremental 10-bit K28.5, K27.7, Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7, K29.7 K28.5, K27.7, Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7, K29.7 1010101010 0011111000 0011111010 1100000101
Output
Polynomials
Verifier Word Alignment Pattern
1000000011111111 1111111111 0101111100 (K28.5)
Incremental 20-bit
0101111100 (K28.5)
High frequency frequency Mixed frequency Note Table 2-9:
This output repeats.
Stratix Clocking
Stratix global clock driven certain REFCLKB pins, transmitter outputs, receiver outputs. REFCLKB pins (except transceiver block transceiver block drive intertransceiver global clock lines well feed transmitter receiver PLLs. output transmitter only feed global clock lines reference clock port receiver PLL. Figures 2-26 2-27 diagrams Inter-Transceiver line connections well global clock connections EP1SGX25F EP1SGX40G devices. devices with fewer transceivers, ignore information about unavailable transceiver blocks.
2-30 Stratix Device Handbook, Volume
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Stratix Transceivers
Figure 2-26. EP1SGX25F Device Inter-Transceiver Global Clock Connections
Note
Transceiver Block Global Clocks, Bus, General Routing refclkb
Transmitter
Global Clocks, Bus, General Routing
Receiver PLLs
Transceiver Block Global Clocks, Bus, General Routing
Transmitter
refclkb
Global Clocks, Bus, General Routing
Receiver PLLs
Transceiver Block Global Clocks Global Clocks, Bus, General Routing refclkb Transmitter
Global Clocks, Bus, General Routing
Receiver PLLs
Transceiver Block Global Clocks, Bus, General Routing
Transmitter
refclkb
Global Clocks, Bus, General Routing
Receiver PLLs
Notes Figure 2-26:
lines inter-transceiver block lines. pre-divider used, path drive logic array, local, global clocks allowed. There four receiver PLLs each transceiver block.
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2-31 Stratix Device Handbook, Volume
Figure 2-27. EP1SGX40G Device Inter-Transceiver Global Clock Connections
Transceiver Block
Global Clks, Bus, Routing
Note
refclkb
Global Clks, Bus, Routing
Receiver PLLs
Transceiver Block
Global Clks, Bus, Routing
refclkb
Global Clks, Bus, Routing
Receiver PLLs
Transceiver Block
Global Clks, Bus, Routing
Global Clocks
refclkb
Global Clks, Bus, Routing
Receiver PLLs
Transceiver Block
Global Clks, Bus, Routing
refclkb
Global Clks, Bus, Routing
Receiver PLLs
Global Clks, Bus, Routing
Transceiver Block
refclkb
Global Clks, Bus, Routing
Receiver PLLS
Notes Figure 2-27:
lines inter-transceiver block lines. pre-divider used, path drive logic array, local, global clocks allowed. There four receiver PLLs each transceiver block.
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Stratix Transceivers
receiver also drive fast regional, regional clocks, local routing adjacent associated transceiver block. Figures 2-28 through 2-31 show which fast regional regional clock resource used recovered clock. EP1SGX25 device, receiver recovered clocks from transceiver blocks drive RCLK[1.0] while transceiver blocks drive RCLK[7.6]. regional clocks feed logic their associated regions. Figure 2-28. EP1SGX25 Receiver Recovered Clock Regional Clock Connection
Stratix Transceiver Blocks Block
RCLK[11.10]
Block
Block
RCLK[9.8]
Block
addition, receiver PLL's recovered clocks drive fast regional lines (FCLK) shown Figure 2-29. fast regional clocks feed logic their associated regions.
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2-33 Stratix Device Handbook, Volume
Figure 2-29. EP1SGX25 Receiver Recovered Clock Fast Regional Clock Connection
FCLK[1.0]
Stratix Transceiver Blocks Block
Block
Block
Block
FCLK[1.0]
EP1SGX40 device, receiver recovered clocks from transceivers drive RCLK[1.0] while transceivers drive RCLK[7.6]. regional clocks feed logic their associated regions.
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Stratix Transceivers
Figure 2-30. EP1SGX40 Receiver Recovered Clock Regional Clock Connection
Stratix Transceiver Blocks Block
RCLK[11.10]
Block
Block
Block
RCLK[9.8]
Block
Figure 2-31 shows possible recovered clock connection fast regional clock resource. fast regional clocks drive logic their associated regions.
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2-35 Stratix Device Handbook, Volume
Figure 2-31. EP1SGX40 Receiver Recovered Clock Fast Regional Clock Connection
Stratix
FCLK[1.0] Transceiver Blocks
Block
Block
Block
Block
Block
FCLK[1.0]
Table 2-10 summarizes possible clocking connections transceivers.
Table 2-10. Possible Clocking Connections Transceivers (Part Destination Source
REFCLKB Transmitter Receiver GCLK RCLK FCLK
Transmitter
Receiver
GCLK
RCLK
FCLK
Lines
2-36 Stratix Device Handbook, Volume
Altera Corporation June 2006
Stratix Transceivers
Table 2-10. Possible Clocking Connections Transceivers (Part Destination Source
lines Notes Table 2-10:
REFCLKB from transceiver block transceiver block does drive inter-transceiver lines GCLK lines. Inter-transceiver line inter-transceiver line drive transmitter PLL, while inter-transceiver line drives receiver PLLs.
Transmitter
Receiver
GCLK
RCLK
FCLK
Lines
Other Transceiver Features
Other important features Stratix transceivers power down reset capabilities, external voltage reference bias circuitry, swapping.
Individual Power-Down Reset Transmitter Receiver
Stratix transceivers offer power saving advantage with their ability shut functions that needed. device individually reset receiver transmitter blocks PLLs. Stratix device either globally power down reset transmitter receiver channels each channel separately. Table 2-11 shows connectivity between reset signals Stratix logical blocks.
Altera Corporation June 2006
2-37 Stratix Device Handbook, Volume
Other Transceiver Features
Power-down functions static, other words., they implemented upon device configuration programmed, through Quartus software, static values. Resets static well dynamic inputs coming from logic array pins.
Table 2-11. Reset Signal Stratix Blocks Transmitter Phase Compensation FIFO Module/ Byte Serializer
Transmitter XAUI State Machine
Receiver Deskew FIFO Module
Reset Signal
Receiver Phase Comp FIFO Module/ Byte Deserializer
Receiver XAUI State Machine
Transmitter 8B/10B Encoder
Transmitter Analog Circuits
Transmitter Analog Circuits
Receiver 8B/10B Decoder
rxdigitalreset rxanalogreset txdigitalreset pll_areset pllenable
Voltage Reference Capabilities
Stratix transceivers provide voltage reference bias circuitry. set-up internal bias controlling transmitter output drivers' voltage swing-as well provide voltage/current biasing other analog circuitry-use internal bandgap voltage reference provide bias internal pull-up PMOS resistors termination serial interface receiver transmitter channels (independent power supply drift, process changes, temperature variation) external resistor, which connected external voltage power supply,
2-38 Stratix Device Handbook, Volume
Altera Corporation June 2006
Receiver Analog Circuits
Receiver Rate Matcher
Receiver Word Aligner
Transmitter Serializer
Receiver Deserializer
Receiver
BIST Generators
Transmitter
BIST Verifiers
Stratix Transceivers
accurately tracked internal bias circuit. Moreover, reference voltage internal resistor bias current generated replicated analog circuitry each channel.
Hot-Socketing Capabilities
Each Stratix device capable hot-socketing. Because Stratix devices used mixed-voltage environment, they have been designed specifically tolerate possible power-up sequence. Signals driven into Stratix devices before during power-up without damaging device. Once operating conditions reached device configured, Stratix devices operate according your specifications. This feature provides Stratix transceiver line card behavior, insert into system without powering system down, offering more flexibility.
Applications Protocols Supported with Stratix Devices
Each Stratix transceiver block designed operate serial rate from Mbps 3.1875 Gbps channel. wide, data rate range allows Stratix transceivers support wide variety standard future protocols such 10-Gigabit Ethernet XAUI, InfiniBand, Fibre Channel, Serial RapidIO. Stratix devices ideal many highspeed communication applications such high-speed backplanes, chipto-chip bridges, high-speed serial communications standards support.
Stratix Example Application Support
Stratix devices used many applications, including:
Backplanes traffic management quality service (QOS) Switch fabric applications complete backplane switch fabric transceivers Chip-to-chip applications such Gigabit Ethernet XAUI XGMII bridge, Gigabit Ethernet XGMII POS-PHY4 bridge, POS-PHY4 NPSI bridge, NPSI backplane bridge
Altera Corporation June 2006
2-39 Stratix Device Handbook, Volume
Applications Protocols Supported with Stratix Devices
High-Speed Serial Protocols
With wide, serial data rate range, Stratix devices support multiple, high-speed serial protocols. Table 2-12 shows some protocols that Stratix devices support.
Table 2-12. High-Speed Serial Protocols Transfer Protocol
SONET backplane Gigabit Ethernet XAUI Gigabit fibre channel InfiniBand Fibre channel (1G, Serial RapidIOPCI Express SMPTE 292M 2.488 3.125 3.1875 1.0625, 2.125 1.25, 2.5, 3.125 1.485
Stratix (Gbps) (Supports 3.1875 Gbps)
2-40 Stratix Device Handbook, Volume
Altera Corporation June 2006
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