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Section III. Advanced Configuration Schemes
This section discusses configuring configuration chains that contain mixture Altera® device families, combining different configuration schemes your board using CPLD flash memory configure your Altera FPGA. recommended that read chapters Volume your target device family before reading this section. This section includes following chapters:
Chapter Configuring Mixed Altera FPGA Chains Chapter Combining Different Configuration Schemes Chapter Using Flash Memory Configure FPGAs
Revision History
Refer each chapter specific revision history. information when each chapter updated, refer Chapter Revision Dates section, which appears complete handbook.
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Section III--1 Preliminary
Revision History
Configuration Handbook, Volume
Section III-2 Preliminary
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Configuring Mixed Altera FPGA Chains
CF52008-2.2
Introduction
mixture Stratix® series, Cyclone® series, APEXII, MercuryTM, APEX 20K, ACEX® FLEX® devices configured same configuration chain, provided that devices chain support selected configuration method, such passive serial (PS). This chapter discusses guidelines should follow when combining different device families same configuration chain. devices your configuration chain require 10-k pull-up resistors, external 10-k pull-up resistors should used support devices chain. pull-up resistors should tied supply that provides acceptable input voltage high level devices chain. DCLK, DATA0, nCONFIG, nSTATUS, CONF_DONE signals should tied together every device configuration chain. concurrent configuration using enhanced configuration devices, each device chain devices separate DCLK line, while DCLK, nCONFIG, nSTATUS, CONF_DONE shared. This ensures that configuration begins ends same time each device. Additionally, device detects error pulls nSTATUS low, devices chain will reset restart configuration.
General Guidelines
more information about connecting configuration control signals together, refer "Board Layout Tips Debugging Techniques" page 10-1 Configuration Handbook. FPGA configuration device that supports JTAG programming placed same JTAG chain. multi-device JTAG chains, external resistors should used TCK, TDI, pins. pull-up resistors should pulled supply that provides acceptable input voltage high level devices chain. interface signals JTAG pins Altera devices that have different VCCIO levels, need insert level shifters. will need insert level shifters tolerant voltage driven previous device's pin. example, first device JTAG chain back where VCCIO 5.0-V second device bank where VCCIO 1.8-V cannot accept 5.0-V inputs, need insert level shifter in-between devices' TDO-TDI interface.
Altera Corporation April 2007
Guidelines Configuration Chains with APEX 20KE Devices
Additionally, will need insert level shifters will recognize voltage driven previous device's input voltage high level (VIH). example, first device JTAG chain back where VCCIO 1.8-V second device bank where VCCIO 5.0-V does recognize 1.8-V logic high level, need insert level shifter in-between devices' TDO-TDI interface.
Guidelines Configuration Chains with APEX 20KE Devices
your configuration chain contains APEX 20KE device(s), must follow APEX 20KE power sequencing requirement outlined Configuring APEX 20KE APEX 20KC Devices Chapter Configuration Handbook. guidelines below should followed successful configuration your configuration chain with APEX 20KE Devices:
configuration schemes, 10-k pull-up resistors nCONFIG, nSTATUS, CONF_DONE. configuration schemes, ensure nCONFIG held upon power-up until both VCCINT VCCIO power supplies stable. using configuration device, nCONFIG must pulled-up VCCINT APEX 20KE device. using nINIT_CONF enhanced configuration device EPC2 device, need isolate 1.8-V VCCINT from configuration device's 3.3-V supply adding diode between nCONFIG nINIT_CONF pin.
Configuration Handbook, Volume
Altera Corporation April 2007
Configuring Mixed Altera FPGA Chains
Document Revision History
Table shows revision history this document.
Table 8-1. Document Revision History Date Document Version
April 2007 v2.2 August 2005 v2.1 July 2004 v2.0 September 2003 v1.0
Changes Made
Added document revision history. Removed active cross references refering document outside Chapter Added Stratix Cyclone device information throughout chapter. Initial Release.
Summary Changes
Altera Corporation April 2007
Configuration Handbook, Volume
Document Revision History
Configuration Handbook, Volume
Altera Corporation April 2007
Combining Different Configuration Schemes
CF52009-2.2
Introduction
This chapter shows configure Altera® FPGAs using multiple configuration schemes same board. Combining JTAG configuration with passive serial (PS) active serial (AS) configuration your board useful prototyping environment because allows multiple methods configure your FPGA. example, your production environment calls configuration using configuration device, would have reprogram your configuration device every time wanted test design change your FPGA. include FPGA same JTAG chain configuration device, FPGA reconfigure JTAG without having reprogram configuration device. this chapter, generic term "download cable" includes Altera Blaster universal serial (USB) port download cable, MasterBlasterserial/USB communications cable, EthernetBlaster, ByteBlasterII parallel port download cable, ByteBlasterMVparallel port download cable. this section, generic term "FPGA" includes Stratix® series, Cyclone® series, APEXII, APEX 20K, MercuryTM, ACEX® FLEX® devices. figures this chapter will only show configuration interface connections. detailed information about pull-up resistor values other pins specific FPGA configuration device, refer appropriate chapter Configuration Handbook.
Passive Serial JTAG
Figure shows configuration interface connections when using download cable JTAG program configuration device configuration device used configure FPGAs. Figure 9-1, multiple FPGAs daisy-chained together MSEL pins should select configuration mode.
Altera Corporation April 2007
Passive Serial JTAG
Figure 9-1. JTAG Programming Configuration Device with Configuration FPGA Using Configuration Device
Download Cable (JTAG Mode) 10-Pin Male Header
FPGA MSEL DCLK CONF_DONE nCONFIG nSTATUS DATA0
nCEO
FPGA
MSEL
Configuration Device
DATA DCLK
DCLK CONF_DONE nCONFIG nSTATUS DATA0
nCEO
nINIT_CONF MSEL
FPGA
DCLK CONF_DONE nCONFIG nSTATUS DATA0
nCEO N.C.
Notes Figure 9-1:
should connected same supply voltage configuration device. APEX 20KE devices, nCONFIG should pulled VCCINT. internal pull-up resistors configuration device used, external pull-up resistors should used these pins.
Figure shows configuration interface connections when configuration device FPGA same JTAG chain. Make sure signal drives high enough voltage meet next device's minimum high-level input voltage (VIH). output will drive voltage bank's VCCIO where resides. example, resides bank whose VCCIO will drive download cable used JTAG program configuration device FPGA. configuration device used configure FPGA. MSEL pins should select configuration mode.
Configuration Handbook, Volume
Altera Corporation April 2007
Combining Different Configuration Schemes
there configuration device board, upon power-up should allow FPGA finish configuration before attempting JTAG configuration.
Figure 9-2. JTAG Programming Configuration Device FPGA with Configuration FPGA Using Configuration Device
Download Cable (JTAG Mode) 10-Pin Male Header
FPGA MSEL
DCLK CONF_DONE nCONFIG nSTATUS DATA0 Configuration Device DATA DCLK
nCEO
N.C.
nINIT_CONF
TRST
Notes Figure 9-2:
should connected same supply voltage configuration device. APEX 20KE devices, nCONFIG should pulled VCCINT. internal pull-up resistors configuration device used, external pull-up resistors should used these pins.
download cables used different modes (e.g., JTAG mode mode) each mode, header download cable connects different pins FPGA. Therefore, separate 10-pin headers required your board order support different modes download cable. Figure shows schematic with download cables. download cable used JTAG mode JTAG program
Altera Corporation April 2007
Configuration Handbook, Volume
Passive Serial JTAG
configuration device. second download cable used mode configure FPGA using configuration. MSEL pins should select configuration mode. Figure 9-3. JTAG Programming Configuration Device with Configuration FPGA Using Configuration Device Download Cable
Download Cable (JTAG Mode) 10-Pin Male Header Download Cable Mode) 10-Pin Male Header
FPGA MSEL
DCLK CONF_DONE nCONFIG nSTATUS DATA0 Configuration Device
nCEO
N.C.
DATA DCLK
nINIT_CONF
Notes Figure 9-3:
should connected same supply voltage configuration device. APEX 20KE devices, nCONFIG should pulled VCCINT. internal pull-up resistors configuration device used, external pull-up resistors should used these pins. configure FPGA with download cable, should either remove configuration device from socket place switch five common signals between download cable configuration device.
should attempt configuration with download cable while configuration device connected FPGA.
Configuration Handbook, Volume
Altera Corporation April 2007
Combining Different Configuration Schemes
configure FPGA using download cable while configuration device connected FPGA, signals driven nSTATUS CONF_DONE pins will pull pins configuration device low. This will reset configuration device cause configure FPGA. perform configuration with download cable, should either remove configuration device from socket when using download cable, place switch five common signals between download cable configuration device. Figure shows schematic which allows configuration FPGA with either mode download cable JTAG mode download cable. Additionally, FPGA configured using configuration device. download cable used JTAG mode JTAG program configuration device FPGA. Figure configuration device FPGA same JTAG chain. Make sure signal drives high enough voltage meet next device's minimum highlevel input voltage (VIH). output will drive voltage bank's VCCIO where resides. example, resides bank whose VCCIO will drive second download cable used mode configure FPGA using configuration. MSEL pins should select configuration mode.
Altera Corporation April 2007
Configuration Handbook, Volume
Passive Serial JTAG
Figure 9-4. Combining JTAG Programming Configuration Device FPGA with Configuration FPGA Using Configuration Device Download Cable
Download Cable (JTAG Mode) 10-Pin Male Header Download Cable Mode) 10-Pin Male Header
FPGA MSEL
DCLK CONF_DONE nCONFIG nSTATUS DATA0 Configuration Device
nCEO
N.C.
DATA DCLK
nINIT_CONF
TRST
Notes Figure 9-4:
should connected same supply voltage configuration device. APEX 20KE devices, nCONFIG should pulled VCCINT. internal pull-up resistors configuration device used, external pull-up resistors should used these pins. configure FPGA with download cable, should either remove configuration device from socket place switch five common signals between download cable configuration device.
Figures also apply fast passive parallel (FPP) mode, except DATA[7.0] connected from enhanced configuration device FPGA(s) that supports configuration. MSEL pins need accordingly.
Configuration Handbook, Volume
Altera Corporation April 2007
Combining Different Configuration Schemes
Active Serial JTAG
devices that support configuration (e.g., Stratix Cyclone series devices), combine configuration scheme with JTAG-based configuration (see Figure 9-5). This setup uses 10-pin download cable headers board. download cable used JTAG mode configure Stratix Cyclone series FPGA directly JTAG interface. other download cable used mode program serial configuration device in-system programming interface. MSEL pins should select configuration mode. configuring device using both schemes simultaneously, JTAG configuration takes precedence configuration will terminated.
Figure 9-5. Combining JTAG Programming Configuration Device FPGA with Configuration FPGA Using Configuration Device Download Cable
Serial Configuration Device
Stratix Cyclone series FPGA nSTATUS CONF_DONE nCEO nCONFIG N.C. MSEL
DATA DCLK ASDI
DATA DCLK nCSO ASDO
Download Cable (JTAG Mode) 10-Pin Male Header (top View)
ByteBlaster Mode) 10-Pin Male Header
Note Figure 9-5:
should connected
Altera Corporation April 2007
Configuration Handbook, Volume
Document Revision History
Document Revision History
Table shows revision history this document.
Table 9-2. Document Revision History Date Document Version
April 2007 v2.2 August 2005 v2.1 July 2004 v2.0 September 2003 v1.0
Changes Made
Added document revision history. Removed active cross references refering document outside Chapter Added Stratix Cyclone device information throughout chapter. Initial Release.
Summary Changes
Configuration Handbook, Volume
Altera Corporation April 2007
Using Flash Memory Configure FPGAs
CF52010-2.2
Introduction
Altera introduces higher-density FPGAs, configuration stream size also increases. result, designs require more configuration devices store data configure these devices. alternative, flash memory used store configuration data. flash memory controller required read write flash memory perform configuration. MAX® 3000A 7000 device implement flash memory controller. flash memory controller interface with microprocessor receive configuration data parallel port (Figure 10-1). controller generates programming command sequence program flash memory extract configuration data configure FPGAs. flash memory controller supports various commands such
Device Configuration Using Flash Memory 3000A Devices
Programming flash memory Configuring FPGAs
reference design that uses 3000 device available Altera site. reference design used with Fujitsu flash.
Altera Corporation April 2007
10-1
Device Configuration Using Flash Memory 3000A Devices
Figure 10-1. Configuring FPGA through Flash Memory 3000A Controller
APEX 20KE Device
3000A Device DCLK nCONFIG DATA0 nSTATUS CONF_DONE Flash WP#/ACC DA[7.0] ADD[21.0] RY_DY
DCLK nCONFIG DATA0 nSTATUS CONF_DONE INIT_DONE MSEL[1.0]
nCEO
DA[7.0] ADD[21.0]
Download Cable 10-Pin Male Header
N.C. nCEO
DCLK nCONFIG
RY_DY
DATA0 nSTATUS CONF_DONE INIT_DONE MSEL[1.0] DATA_MOD DATA_PC CONF_STATUS APEX 20KE Device Input Rst# CLOCK RSTB Download Cable 10-Pin Male Header
Flash Memory Controller Design Specification
controller will check flash memory programmed successfully after board powers flash memory programmed successfully, then controller configures FPGAs. flash memory programmed successfully, then controller waits commands from microprocessor. receiver decodes commands receives from microprocessor following:
Program flash memory Configure FPGA
10-2 Configuration Handbook, Volume
Altera Corporation April 2007
Using Flash Memory Configure FPGAs
After command executed, controller returns idle mode waits next command. Figure 10-2 shows controller state machine. Figure 10-2. Flash Memory Controller State Machine
Check Flash Memory been Programmed
Configure APEX Devices
IDLE Wait Commands from from
Done Programming
Decode Command
Program Flash Memory
Configure APEX Devices
Flash Memory Controller Functionality
controller writes byte special location flash memory when programs memory. After POR, controller checks this special location flash memory byte written there not. byte written, then flash memory been programmed controller proceed configuring FPGAs reading data from flash memory. this byte there value expected, controller will idle wait programmed microprocessor.
Altera Corporation April 2007
10-3 Configuration Handbook, Volume
Device Configuration Using Flash Memory 3000A Devices
Getting Data from Microprocessor
microprocessor uses parallel port interface with controller. There types signals involved this connection (see Figure 10-3), 3-bit input signal from microprocessor controller, 2-bit output signal from controller microprocessor. input signal includes following three signals:
STB: Strobe signal from microprocessor indicate that microprocessor's data valid. data_mode: Indicates whether controller command mode data mode. When data_mode high, controller command mode; when data_mode low, controller data mode. data: Content this signal depends data_mode. data command mode data mode.
output signal contains following signals:
ACK: Acknowledge signal handshaking signal from controller microprocessor. conf_status: Indicates configuration status.
Figure 10-3. Getting Data from Microprocessor
Data_mode
Mode
Data Mode
Data
Note Figure 10-3:
Data sent both positive negative edges signal.
10-4 Configuration Handbook, Volume
Altera Corporation April 2007
Using Flash Memory Configure FPGAs
controller receives data command from microprocessor rising falling edges signal. After receiving this data, controller will send acknowledgement signal microprocessor initiate sending next data. acknowledge signal (ACK) should same logic level last received signal. de-asserting ACK, controller stop microprocessor from sending data. Figure 10-4 shows relationship. Figure 10-4. Sending Acknowledge Signal (ACK) Microprocessor
Data_mode
Mode
Data Mode
Data
Note Figure 10-4:
data received each signal edge (both positive negative).
Programming Flash Memory
After receiving command from microprocessor, controller first erases then starts programming flash memory. separate state machine required generate programming command sequence programming pulse width. While programming flash memory, controller must check command (data_mode=1) been received not. command indicates data from microprocessor, controller will exit Program_Flash_memory state into idle mode.
Altera Corporation April 2007
10-5 Configuration Handbook, Volume
Device Configuration Using Flash Memory 7000 Devices
Another state machine required read serialize byte data from flash memory generate DCLK DATA0. controller needs monitor CONF_DONE signals from FPGAs determine configuration complete. When configuration done, controller exits configure state goes back idle mode.
Device Configuration Using Flash Memory 7000 Devices
Figure 10-5 shows schematic this configuration scheme with 7000 device. sample design files 7000 device (Design File Configuring APEX20K Devices Design File Configuring FLEX® FLEX 6000 Devices) available Altera site.
Figure 10-5. Device Configuration Using External Memory 7000 Device
Oscillator 7000 Device
nSTATUS
APEX APEX 20K, ACEX Mercury, FLEX 10K, FLEX 6000 Device MSEL0
nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO MSEL1
Memory
DATA[] ADDR[] RESTART ADDR[] RESTART
INIT_DONE CONF_DONE DCLK DATA0 nCONFIG
APEX APEX 20K, ACEX Mercury, FLEX 10K, FLEX 6000 Device
MSEL0 nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO MSEL1
N.C.
Notes Figure 10-5:
FLEX 6000 devices have single MSEL pin, which tied ground, DATA0 renamed DATA. pull-up resistors APEX 20KE APEX 20KC devices, pull-up resistors nSTATUS, CONF_DONE, INIT_DONE pins should
10-6 Configuration Handbook, Volume
Altera Corporation April 2007
Using Flash Memory Configure FPGAs
Figure 10-6 shows timing waveform configuring APEXII, APEX 20K, MercuryTM, ACEX® FLEX 10K, FLEX 6000 device using external memory 7000 device. Figure 10-6. Timing Waveform Configuration Using External Memory 7000 Device
nSTATUS nCONFIG DCLK DATA0 D[7.0] ADDR[15.0] CONF_DONE RESTART INIT_DONE
Design Example Using 3000 Devices
MAX® 3000 device used stream data from flash memory into large FPGA. This configuration technique allows faster configuration times. Since fixed-frequency oscillator available clock system) used generate clock configuration, clock frequency high (the maximum APEX 20KE device). Flash memory type nonvolatile memory that used data storage device. Flash memory erased reprogrammed units memory called blocks. This section describes configure FPGA with flash memory. using 3000 device configure higher density FPGAs, flash memory store configuration data 3000 device serialize transmit data FPGA. This configuration technique used with APEX, ACEX, FLEX devices.
Configuring FPGAs
Figure 10-7 shows device that uses EPM3128A device flash memory configure FPGAs.
Altera Corporation April 2007
10-7 Configuration Handbook, Volume
Configuring FPGAs
Figure 10-7. Device Configuration Using Flash Memory EPM3128A Device
Oscillator EPM3128A Device
APEX, ACEX, FLEX
MSEL0 nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO MSEL1
Flash Memory
DATA[] ADDR[] RESTART nSTATUS ADDR[] RESTART INIT_DONE CONF_DONE DCLK DATA0 nCONFIG
APEX, ACEX, FLEX
MSEL0 nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO N.C. MSEL1
Notes Figure 10-7
FLEX 6000 devices have single MSEL pin, which tied ground. Additionally, DATA0 renamed DATA. Pull-up resistors except APEX 20KE devices. APEX 20KE devices, pull resistors nSTATUS, CONF_DONE, INIT_DONE pins open-drain APEX, ACEX, FLEX devices. corresponding pins EPM3128A should also open_drain.
VHDL design file called MAXconfig, shown "Configuration Design File" section, allows EPM3128A device control configuration process. MAXconfig design configures FPGA using configuration data stored attached flash memory. MAXconfig design contains sequencer address generator, which drives correct data FPGA's programming pins. MAXconfig design file available Altera site When MAXconfig design reset, MAXconfig design reads data from flash memory, byte time. MAXconfig design then serializes sends data APEX, ACEX, FLEX device. serialized data sent FPGA using passive serial interface pins such DCLK, DATA, nSTATUS, INIT_DONE, nCONFIG. Since passive serial mode used, flash pins directly connected APEX, ACEX, FLEX device.
10-8 Configuration Handbook, Volume
Altera Corporation April 2007
Using Flash Memory Configure FPGAs
Flash memory programmed prior being onto board with standard programming equipment programmed in-system processor test equipment. Since different flash memories have different algorithms, consult flash memory data sheet programming information. Figure 10-8 shows configuration timing waveform EPM3128A device downloading data APEX, ACEX, FLEX device. Figure 10-8. Configuration Timing Waveform
nSTATUS nCONFIG DCLK DATA0 D[7.0] ADDR[15.0] CONF_DONE RESTART INIT_DONE DATA
Configuration Design File
This section shows MAXconfig design file that controls configuration process APEX, ACEX, FLEX devices: library ieee; ieee.std_logic_1164.all; ieee.std_logic_unsigned.all; entity MAXconfig port clock std_logic; init_done: std_logic; nStatus: std_logic; std_logic_vector(7 downto restart: std_logic; Conf_Done: std_logic; Data0 Dclk std_logic; std_logic;
Altera Corporation April 2007
10-9 Configuration Handbook, Volume
Configuring FPGAs
nConfig: bufferstd_logic; increase size memory, change size std_logic_vector ADDR output -std_logic_vector signal inc: ADDR std_logic_vector(15 downto std_logic); polarity signal determined type Flash device end; architecture MAXconfig -The following encoding done such that represents nConfig signal: constant constant constant constant constant constant start :std_logic_vector(2 downto "000"; downto "100"; status :std_logic_vector(2 downto "001"; wait_40us :std_logic_vector(2 downto "101"; config :std_logic_vector(2 downto "011"; init :std_logic_vector(2 downto "111";
signal :std_logic_vector(2 downto signal count :std_logic_vector(2 downto signal data0_int, dclk_int:std_logic; signal :std_logic_vector(15 downto signal :std_logic_vector(2 downto signal waitd :std_logic_vector(11 downto -The width signal `waitd' determined frequency. (APEX 20KE devices), -`waitd' bits. (FLEX 10KE ACEX devices) `waitd' bits. calculate -the width `waitd' signal fordifferent frequencies, calculate following: -(multiply tcf2ck clock frequency)+ -Then convert this value binary obtain width. -For example, (FLEX 10KE ACEX devices), converting 1360 ((40us 33MHz)+40=1360) binary code, `waitd' 11-bit signal. signal `waitd' will -signal waitd :std_logic_vector(10 downto begin -The following process used divide CLOCK: PROCESS (clock,restart) begin restart then (others '0'); else (clock'EVENT clock '1') THEN
10-10 Configuration Handbook, Volume
Altera Corporation April 2007
Using Flash Memory Configure FPGAs
PROCESS; PROCESS (clock,restart) begin restart then pp<=start; count (others '0'); (others '0'); waitd (others '0'); else clock'event clock='1' then -The following test used divide CLOCK. value compared must such that -condition true maximum rate (tclk 17.5 min) APEX 20KE devices -and maximum rate (tclk=30ns min) FLEX 10KE ACEX devices. (div then case when start count (others '0'); (others '0'); waitd (others '0'); wait_nCfg_8us; -This state used order verify tcfg timing (nCONFIG pulse width). -Tcfg min= clock cycle clock (APEX 20KE devices). different -clocks, multiply clock frequency. example, 33MHz (FLEX 10KE ACEX devices) this -value 8*33=264. This clock CLOCK divided divider -div-. when wait_nCfg_8us count (others '0'); (others '0'); waitd waitd waitd then -For FLEX 10KE ACEX devices this line waitd then status; -This state used have nCONFIG when status count (others (others waitd (others wait_40us; high. '0'); '0'); '0');
-This state used generate tcf2ck timing (nCONFIG high first rising edge DCLK).
Altera Corporation April 2007
10-11 Configuration Handbook, Volume
Configuring FPGAs
-Tcf2ck 40µs 2280 clock clock CLOCK -divide divider -div-Tcf2ck 40µs 1320 clock This clock CLOCK -divided -For other clock frequency,
cycles 57MHz (APEX 20KE) clock. This cycles 33MHz (FLEX 10KE/ACEX) clock. divider -div-) multiply tcf2ck clock frequency.
when wait_40us count (others '0'); (others '0'); waitd waitd waitd 2280 then -For (FLEX 10KE ACEX devices), this line then config;
waitd 1320
-This state used increment memory address. same state when -the Conf_Done high clock cycles added order have initialization completed. when config count count Conf_Done='1' then waitd waitd count=7 then waitd 2320 then -Modification: clock cycles. APEX 20KE devices, 2280+40=2320 -For FLEX 10KE ACEX devices, 1320+40=1360. This line becomes: waitd= 1360 then pp<= init; when init count (others (others waitd (others nStatus start; else init; when others start; case; '0'); '0'); '0'); then
10-12 Configuration Handbook, Volume
Altera Corporation April 2007
Using Flash Memory Configure FPGAs
else inc; count count; PROCESS; dclk_int div(2) when pp=config else '0'; -The following process used serialize data byte PROCESS (count,D,pp) begin pp=config then case count when "000" data0_int D(0); when "001" data0_int D(1); when "010" data0_int D(2); when "011" data0_int D(3); when "100" data0_int D(4); when "101" data0_int D(5); when "110" data0_int D(6); when "111" data0_int D(7); when others null; case; else data0_int '0'; PROCESS; nConfig pp(0); nconfig; Dclk when pp(1)='0' else dclk_int; Data0 when pp(1)='0' else data0_int; ADDR inc; end;
Conclusion
Altera provides high-density FPGAs that require larger configuration files. using flash memory device EPM3128A device design, FPGA quickly configured.
Altera Corporation April 2007
10-13 Configuration Handbook, Volume
Document Revision History
Document Revision History
Table 10-1 shows revision history this document.
Table 10-1. Document Revision History Date Document Version
April 2007 v2.2 August 2005 v2.1 July 2004 v2.0
Changes Made
Added document revision history. Removed active cross references refering document outside Chapter
Summary Changes
Removed Intel flash reference design. Updated Figure 10-1. Removed Flash Memory Content Verification section.
September 2003 v1.0
Initial Release.
10-14 Configuration Handbook, Volume
Altera Corporation April 2007
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