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Quartus Version Handbook Volume Verification
QII5V3_7.1
Copyright 2007 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
Preliminary
Altera Corporation
Contents
Chapter Revision Dates xxix About this Handbook xxxi
Contact Altera xxxi Third-Party Software Product Information xxxi Typographic Conventions xxxii
Section Simulation
Chapter Quartus Simulator
Introduction Simulation Flow Functional Simulation Timing Simulation Timing Simulation Using Fast Timing Model Simulation Waveform Editor Creating VWFs Count Value 1-11 Clock 1-11 Arbitrary Value 1-12 Random Value 1-13 Generating Testbench 1-14 Grid Size 1-14 Time Bars 1-14 Stretch Compress Waveform Interval 1-15 Time 1-16 Arrange Group Order 1-17 Simulator Settings 1-17 Simulation Verification Options 1-21 Simulation Output Files Options 1-24 Simulation Report 1-25 Simulation Waveform 1-25 Simulating Bidirectional 1-26 Logical Memories Report 1-27 Simulation Coverage Reports 1-27 Comparing Waveforms 1-28 Debugging with Quartus Simulator 1-29 Breakpoints 1-29 Updating Memory Content 1-30
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Last Simulation Vector Outputs Conventional Debugging Process Accessing Internal Signals Simulation Scripting Support Conclusion Referenced Documents Document Revision History
1-30 1-30 1-30 1-32 1-33 1-33 1-34
Chapter Mentor Graphics ModelSim Support
Introduction Background Software Compatibility Altera Design Flow with ModelSim ModelSim-Altera Software Functional Simulation Functional Simulation Libraries Simulation Models Altera Megafunction Simulation Models Low-Level Primitive Simulation Models Simulating VHDL Designs Create Simulation Libraries Create Simulation Libraries Using ModelSim Create Simulation Libraries Using ModelSim Command Prompt Compile Simulation Models into Simulation Libraries Compile Simulation Models into Simulation Libraries Using ModelSim Compile Simulation Models into Simulation Libraries ModelSim Command Prompt Compile Testbench Design Files into Work Library Compile Testbench Design Files into Work Library Using ModelSim Command Prompt Loading Design Loading Design Using ModelSim Command Prompt 2-10 Running Simulation 2-10 Running Simulation Using ModelSim Command Prompt 2-10 Simulating Verilog Designs 2-10 Create Simulation Libraries 2-10 Create Simulation Libraries Using ModelSim 2-11 Create Simulation Libraries Using ModelSim Command Prompt 2-11 Compile Simulation Models into Simulation Libraries 2-11 Compile Simulation Models into Simulation Libraries Using ModelSim 2-11 Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt 2-12 Compile Testbench Design Files into Work Library 2-12 Compile Testbench Design Files into Work Library Using ModelSim Command Prompt 2-12
Preliminary
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Contents
Loading Design 2-12 Loading Design Using ModelSim Command Prompt 2-13 Running Simulation 2-13 Running Simulation Using ModelSim Command Prompt 2-13 Verilog Functional Simulation with Altera Memory Blocks 2-13 Post-Synthesis Simulation 2-16 Generating Post-Synthesis Simulation Netlist 2-16 Simulating VHDL Designs 2-17 Create Simulation Libraries 2-17 Create Simulation Libraries Using ModelSim 2-17 Create Simulation Libraries Using ModelSim Command Prompt 2-18 Compile Simulation Models into Simulation Libraries Using ModelSim 2-18 Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt 2-18 Compile Testbench VHDL Output File into Work Library 2-18 Compile Testbench VHDL Output File into Work Library Using ModelSim Command Prompt 2-19 Loading Design 2-19 Loading Design Using ModelSim Command Prompt 2-19 Running Simulation 2-19 Running Simulation Using ModelSim Command Prompt 2-20 Simulating Verilog Designs 2-20 Create Simulation Libraries 2-20 Create Simulation Libraries Using ModelSim 2-20 Create Simulation Libraries Using ModelSim Command Prompt 2-20 Compile Simulation Models into Simulation Libraries Using ModelSim 2-21 Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt 2-21 Compile Testbench Verilog Output File into Work Library 2-21 Compile Testbench Verilog Output File into Work Library Using ModelSim Command Prompt 2-21 Loading Design 2-22 Loading Design Using ModelSim Command Prompt 2-22 Running Simulation 2-22 Running Simulation Using ModelSim Command Prompt 2-23 Gate-Level Timing Simulation 2-23 Generating Gate-Level Timing Simulation Netlist 2-23 Generating Different Timing Model 2-24 Operating Condition Example: Generate Timing Models Stratix Devices 2-25 Perform Timing Simulation Using Post-synthesis Netlist 2-26 Gate-Level Simulation Libraries 2-27 Simulating VHDL Designs 2-30 Create Simulation Libraries 2-30 Create Simulation Libraries Using ModelSim 2-30 Create Simulation Libraries Using ModelSim Command Prompt 2-31 Compile Simulation Models into Simulation Libraries Using ModelSim 2-31 Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt 2-31
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Compile Testbench VHDL Output File into Work Library 2-31 Compile Testbench VHDL Output File into Work Library Using ModelSim Command Prompt 2-32 Loading Design 2-32 Loading Design Using ModelSim Command Prompt 2-33 Running Simulation 2-33 Running Simulation Using ModelSim Command Prompt 2-33 Simulating Verilog Designs 2-33 Create Simulation Libraries 2-33 Create Simulation Libraries Using ModelSim 2-34 Create Simulation Libraries Using ModelSim Command Prompt 2-34 Compile Simulation Models into Simulation Libraries Using ModelSim 2-34 Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt 2-35 Compile Testbench Verilog Output File into Work Library 2-35 Compile Testbench Verilog Output File into Work Libraries Using ModelSim Command Prompt 2-35 Loading Design 2-35 Loading Design Using ModelSim Command Prompt 2-36 Running Simulation 2-36 Running Simulation Using ModelSim Command Prompt 2-36 Simulating Designs that Include Transceivers 2-37 Stratix Functional Simulation 2-37 Example: Performing Functional Simulation Stratix Verilog 2-37 Example: Performing Functional Simulation Stratix VHDL 2-37 Stratix Post-Fit (Timing) Simulation 2-38 Example: Performing Timing Simulation Stratix Verilog 2-38 Example: Performing Timing Simulation Stratix VHDL 2-39 Stratix Functional Simulation 2-39 Example: Performing Functional Simulation Stratix Verilog 2-40 Example: Performing Functional Simulation Stratix VHDL 2-41 Stratix Post-Fit (Timing) Simulation 2-41 Example: Performing Timing Simulation Stratix Verilog 2-42 Example: Performing Timing Simulation Stratix VHDL 2-42 Transport Delays 2-43 +transport_path_delays 2-43 +transport_int_delays 2-43 Using NativeLink Feature with ModelSim 2-44 Setting NativeLink 2-44 Performing Simulation Using NativeLink 2-44 Performing Gate-Level Simulation Using NativeLink 2-47 Setting Testbench 2-48 Creating Testbench 2-49 Scripting Support 2-50 Generating Post-Synthesis Simulation Netlist ModelSim 2-50 Commands 2-50 Command Prompt 2-51 Generating Gate-Level Timing Simulation Netlist ModelSim 2-51 Commands 2-51
Preliminary Altera Corporation
Contents
Command Line Software Licensing Licensing Set-Up LM_LICENSE_FILE Variable Conclusion Referenced Documents Document Revision History
2-51 2-51 2-52 2-52 2-52 2-53
Chapter Synopsys Support
Introduction Software Requirements Using Quartus Design Flow Using Quartus Design Flow .3-2 Functional Simulations Megafunctions Requiring Atom Libraries Functional Simulation with Altera Memory Blocks Compiling Functional Library Files with Compiler Directives Post-Synthesis Simulation Generating Post-Synthesis Simulation Netlist Gate-Level Timing Simulation Generating Gate-Level Timing Simulation Netlist Generating Different Timing Model Operating Condition Example: Generate Timing Models Stratix Devices Perform Timing Simulation Using Post-Synthesis Netlist 3-10 Common Software Compiler Options 3-11 Using VirSim 3-11 Debugging Support Command-Line Interface 3-12 Simulating Designs that Include Transceivers 3-12 Stratix Functional Simulation 3-12 Example Compiling Library Files Functional Stratix Simulation Verilog .3-13 Stratix Post-Fit (Timing) Simulation 3-13 Example Compiling Library Files Timing Stratix Simulation Verilog .3-13 Stratix Functional Simulation 3-13 Example Compiling Library Files Functional Stratix Simulation Verilog .3-14 Stratix Post-Fit (Timing) Simulation 3-15 Example Compiling Library Files Timing Stratix Simulation Verilog .3-15 Using Routines with Software 3-15 Preparing Linking Programs Verilog Code 3-15 Transport Delays 3-16 +transport_path_delays 3-16 +transport_int_delays 3-16 Using NativeLink with Software 3-17 Setting NativeLink 3-17 Performing Simulation Using NativeLink 3-17
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Preliminary
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Performing Gate-Level Simulation Using NativeLink Setting Testbench Creating Testbench Scripting Support Generating Post-Synthesis Simulation Netlist Commands Command Prompt Generating Gate-Level Timing Simulation Netlist Commands Command Prompt Conclusion Referenced Documents Document Revision History
3-19 3-20 3-21 3-22 3-22 3-22 3-22 3-22 3-23 3-23 3-23 3-23 3-24
Chapter Cadence NC-Sim Support
Introduction Software Requirements Simulation Flow Overview Operation Modes Quartus Software Simulation Flow Overview Functional Simulation Create Libraries Basic Library Setup Using Multiple cds.lib Files Create cds.lib File Command-Line Mode Create cds.lib File Mode Functions, Altera Megafunctions, Altera Primitives Libraries Megafunctions Requiring Atom Libraries 4-10 Simulating Design with Memory 4-10 Compile Source Code Testbenches 4-12 Compilation Command-Line Mode 4-12 Compilation Mode 4-13 Elaborate Your Design 4-14 Elaboration Command-Line Mode 4-14 Elaboration Mode 4-15 Signals View 4-16 Adding Signals Command-Line Mode 4-16 Adding Signals Mode 4-17 Simulate Your Design 4-19 Functional/RTL Simulation Command-Line Mode 4-20 Functional/RTL Simulation Mode 4-20 Post-Synthesis Simulation 4-21 Quartus Simulation Output Files 4-21 Create Libraries 4-22
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Compile Project Files Libraries 4-22 Elaborate Your Design 4-22 Signals View 4-22 Simulate Your Design 4-23 Gate-Level Timing Simulation 4-23 Generating Gate-Level Timing Simulation Netlist 4-23 Generating Different Timing Model 4-24 Operating Condition Example: Generate Timing Models Stratix Cyclone Devices 4-25 Perform Timing Simulation Using Post-Synthesis Netlist 4-26 Quartus Timing Simulation Libraries 4-27 Create Libraries 4-27 Compile Project Files Libraries 4-27 Elaborate Your Design 4-28 Compiling Standard Delay Output File (VHDL Only) Command-Line Mode 4-28 Compiling Standard Delay Output File (VHDL Only) Mode 4-29 Signals View 4-30 Simulate Your Design 4-30 Simulating Designs that Include Transceivers 4-30 Stratix Functional Simulation 4-30 Example Compiling Library Files Functional Stratix Simulation Verilog .4-31 Example Compiling Library Files Functional Stratix Simulation VHDL 4-31 Stratix Post-Fit (Timing) Simulation 4-31 Example Compiling Library Files Timing Stratix Simulation Verilog .4-31 Example Compiling Library Files Timing Stratix Simulation VHDL 4-32 Stratix Functional Simulation 4-32 Example Compiling Library Files Functional Stratix Simulation Verilog .4-34 Example Compiling Library Files Functional Stratix Simulation VHDL 4-35 Stratix Post-Fit (Timing) Simulation 4-35 Example Compiling Library Files Timing Stratix Simulation Verilog .4-35 Example Compiling Library Files Timing Stratix Simulation VHDL 4-36 Pulse Reject Delays 4-36 -PULSE_R 4-36 -PULSE_INT_R 4-36 Using NativeLink Feature with NC-Sim 4-37 Setting NativeLink 4-37 Performing Simulation Using NativeLink 4-37 Performing Gate Level Simulation Using NativeLink 4-40 Setting Testbench 4-40 Creating Testbench 4-42 Incorporating Routines 4-43 Dynamically Link Library 4-43
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Dynamically Load Library Statically Link Library with NC-Sim Scripting Support Generate NC-Sim Simulation Output Files Commands: Command Prompt Conclusion Referenced Documents Document Revision History
4-44 4-47 4-48 4-49 4-49 4-49 4-49 4-50 4-50
Chapter Simulating Altera Third-Party Simulation Tools
Introduction Functional Simulation Flow Verilog VHDL Functional Simulation (IPFS) Models Instantiate Your Design Perform Simulation Simulating Altera Using Quartus NativeLink Feature Quartus Project Select Third-Party Simulation Tool Specify Path Third-Party Simulator Specify Testbench Settings Analyze Elaborate Quartus Project Functional Simulation Simulating Altera Without Quartus NativeLink Feature Design Language Examples 5-11 Verilog Example: Simulating IPFS Model ModelSim Software 5-11 VHDL Example: Simulating IPFS Model ModelSim Software 5-12 NC-VHDL Example: Simulating IPFS Model NC-VHDL Software 5-14 Verilog Example: Simulating Your IPFS Model 5-15 Single-Step Process 5-15 Two-Step Process (Compilation Simulation) 5-16 Conclusion 5-16 Referenced Documents 5-16 Document Revision History 5-17
Section Timing Analysis
Chapter Quartus TimeQuest Timing Analyzer
Introduction Setting Quartus TimeQuest Timing Analyzer Launching Quartus TimeQuest Timing Analyzer Directly from Quartus Software Stand-Alone Mode Command-Line Mode Getting Started with Quartus TimeQuest Timing Analyzer
Preliminary
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Contents
Specifying Clock Requirements Specifying Input Output Port Requirements Reporting 6-11 Timing Analysis Overview 6-14 Constraints Files 6-19 Fitter Timing Analysis Files 6-19 Specifying Files Place-and-Route 6-19 Specifying Files Static Timing Analysis 6-20 Synopsys Design Constraints File Precedence 6-20 Quartus TimeQuest Timing Analyzer Flow Guidelines 6-21 Create Quartus Project Specify Design Files 6-22 Perform Initial Compilation 6-22 Creating Post-Map Database 6-23 Creating Post-Fit Database 6-23 Specify Design Timing Requirements 6-23 Create Timing Netlist 6-24 Specify Timing Constraints 6-25 Generate Constraint Reports 6-25 Save Timing Constraints 6-26 Compile Design 6-26 Verify Timing 6-27 Create Timing Netlist 6-27 Read Synopsys Design Constraints File 6-27 Update Timing Netlist 6-28 Generate Timing Reports 6-28 Clock Analysis 6-28 Clock Setup Check 6-29 Clock Hold Check 6-30 Recovery Removal 6-32 Multicycle Paths 6-34 Clock Specification 6-34 Clocks 6-35 Generated Clocks 6-36 Virtual Clocks 6-39 Multi-Frequency Clocks 6-40 Automatic Clock Detection 6-41 Derive Clocks 6-42 Default Clock Constraints 6-44 Clock Groups 6-44 Clock Effect Characteristics 6-45 Clock Latency 6-46 Clock Uncertainty 6-47 Derive Clock Uncertainty 6-48 Application Examples 6-48 Specifications Analysis 6-51 Input Output Delay 6-51 Input Delay 6-51
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Output Delay 6-53 Timing Exceptions 6-54 Precedence 6-55 False Path 6-55 Minimum Delay 6-56 Maximum Delay 6-57 Multicycle Path 6-59 Constraint Exception Removal 6-60 Collections 6-61 Application Examples 6-62 Timing Reports 6-63 report_timing 6-63 report_clock_transfers 6-67 report_clocks 6-68 report_min_pulse_width 6-68 report_net_timing 6-70 report_sdc 6-70 report_ucp 6-71 report_path 6-72 report_datasheet 6-73 report_rskm 6-74 report_tccs 6-75 report_path 6-75 check_timing 6-77 report_clock_fmax_summary 6-79 create_timing_summary 6-80 Timing Analysis Features 6-81 Multi-Corner Analysis 6-81 Advanced Timing Board Trace Model Assignments 6-83 Wildcard Assignments Collections 6-83 Resetting Design 6-85 Quartus TimeQuest Timing Analyzer 6-86 View Pane 6-87 View Pane: Splitting 6-87 View Pane: Removing Split Windows 6-88 Tasks Pane 6-89 Opening Project Writing Synopsys Design Constraints File 6-89 Netlist Setup Folder 6-90 Reports Folder 6-90 Macros Folder 6-91 Console Pane 6-91 Report Pane 6-92 Constraints 6-92 Name Finder 6-94 Target Pane 6-96 Editor 6-96 Conclusion 6-97
Preliminary
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Contents
Referenced Documents 6-97 Document Revision History 6-98
Chapter Switching Quartus TimeQuest Timing Analyzer
Introduction Benefits Switching Quartus TimeQuest Analyzer Chapter Contents Switching Quartus TimeQuest Analyzer Compile Your Design Create File Conversion Utility Perform Timing Analysis with Quartus TimeQuest Timing Analyzer Quartus TimeQuest Analyzer Default Timing Analyzer Differences Between Quartus TimeQuest Quartus Classic Timing Analyzers Terminology Netlist Collections Constraints Constraint Files Constraint Entry Time Units MegaCore Functions Name Format 7-10 Constraint File Priority 7-10 Constraint Priority 7-11 Ambiguous Constraints 7-12 Clocks 7-13 Related Unrelated Clocks 7-13 Clock Offset 7-14 Clock Latency 7-15 Offset Latency Example 7-15 Clock Offset Scenario 7-16 Clock Latency Scenario 7-17 Clock Uncertainty 7-18 Derived Generated Clocks 7-19 Automatic Clock Detection 7-19 derive_clocks Command 7-20 derive_pll_clocks Command 7-22 Hold Relationship 7-23 Clock Objects 7-23 Hold Multicycle 7-24 Fitter Behavior 7-27 Fitter Performance 7-27 Reporting 7-27 Paths Pairs 7-28 Default Reports 7-28
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Netlist Names 7-29 Non-Integer Clock Periods 7-29 Other Features 7-30 Scripting 7-32 Timing Assignment Conversion 7-33 Setup Relationship 7-33 Hold Relationship 7-34 Clock Latency 7-34 Clock Uncertainty 7-34 Inverted Clock 7-35 Clock 7-35 Default Required fMAX Assignment 7-35 Virtual Clock Reference 7-36 Clock Settings 7-37 Multicycle 7-37 Clock Enable Multicycle 7-38 Constraints 7-38 Input Output Delay 7-39 Requirement 7-40 Requirement 7-43 Requirement 7-45 Minimum Requirement 7-48 Requirement 7-50 Combinational Path Delay Scenario 7-50 Minimum Requirement 7-51 Timing Path 7-52 Maximum Delay 7-52 Minimum Delay 7-52 Maximum Clock Arrival Skew 7-53 Maximum Data Arrival Skew 7-53 Constraining Skew Output 7-53 Conversion Utility 7-55 Unsupported Global Assignments 7-56 Recommended Global Assignments 7-56 Clock Conversion 7-58 Instance Assignment Conversion 7-59 Phase Shift Conversion 7-61 Requirement Conversion 7-62 Entity-Specific Assignments 7-63 Paths between Unrelated Clock Domains 7-63 Unsupported Instance Assignments 7-64 Reviewing Conversion Results 7-64 Warning Messages 7-64 Ignored Variable <assignment> 7-65 Global <name> <value> 7-65 QSF: Expected <name> <expected value> <actual value> .7-65
Preliminary
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Contents
QSF: Found Global Fmax Requirement. Translation will done using derive_clocks .7-65 Report Database found. based assignments will migrated 7-65 Ignored Entity Assignment (Entity <entity>): <variable> <value> -from <from> <to> 7-65 Ignoring OFFSET_FROM_BASE_CLOCK assignment clock <clock> 7-66 Clock <clock> FMAX_REQUIREMENT clock generated 7-66 Clock Settings defined file 7-66 Clocks 7-66 Clock Transfers 7-66 Path Details 7-67 Unconstrained Paths 7-67 Names 7-68 Other 7-68 Re-Running Conversion Utility 7-68 Notes 7-68 Output Load Assignments 7-68 Constraint Target Types 7-69 Constraints with Timing Wizard 7-69 HardCopy Stratix Device Handoff 7-69 Unsupported Features 7-69 Constraint Passing 7-70 Optimization 7-70 Clock Network Delay Reporting 7-70 PowerPlay Power Analysis 7-70 Project Management 7-71 Conversion Utility 7-71 Minimum Requirement Conversion 7-71 Referenced Documents 7-71 Document Revision History 7-72
Chapter Quartus Classic Timing Analyzer
Introduction Timing Analysis Tool Setup Static Timing Analysis Overview Clock Analysis Clock Setup Check Clock Hold Check Multicycle Paths Clock Settings Individual Clock Settings Default Clock Settings Clock Types Base Clocks Derived Clocks Undefined Clocks Clocks 8-10
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Clock Uncertainty Clock Latency Timing Exceptions Multicycle Destination Multicycle Setup Exception Destination Multicycle Hold Exception Source Multicycle Setup Exception Source Multicycle Hold Exception Default Hold Multicycle Clock Enable Multicycle Setup Relationship Hold Relationship Maximum Delay Minimum Delay False Paths Analysis External Input Delay Output Delay Assignments Input Delay Assignment Output Delay Assignment Virtual Clocks Asynchronous Paths Recovery Removal Recovery Report Removal Report Skew Management Maximum Clock Arrival Skew Maximum Data Arrival Skew Generating Timing Analysis Reports with report_timing Other Timing Analyzer Features Wildcard Assignments Assignment Groups Fast Corner Analysis Early Timing Estimation Timing Constraint Checker Latch Analysis Timing Analysis Using Quartus Assignment Editor Timing Settings Clock Settings Dialog More Timing Settings Dialog Timing Reports Advanced List Path Early Timing Estimate Assignment Groups Scripting Support Creating Clocks Base Clocks Derived Clocks Clock Latency
8-11 8-12 8-15 8-15 8-15 8-16 8-17 8-18 8-19 8-19 8-22 8-24 8-25 8-26 8-26 8-27 8-28 8-30 8-31 8-31 8-31 8-33 8-34 8-35 8-35 8-36 8-38 8-38 8-38 8-40 8-40 8-41 8-42 8-43 8-43 8-44 8-45 8-46 8-47 8-49 8-51 8-51 8-52 8-53 8-53 8-53 8-53
Preliminary
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Contents
Clock Uncertainty Timing Paths Input Delay Assignment Maximum Minimum Delay Maximum Clock Arrival Skew Maximum Data Arrival Skew Multicycle Output Delay Assignment Report Timing Setup Hold Relationships Assignment Group Virtual Clock MAX+PLUS Timing Analysis Methodology fMAX Relationships Slack Timing Timing Timing Timing Minimum (min tCO) Timing Minimum (min tPD) Timing Analyzer Tool Conclusion Referenced Documents Document Revision History
8-54 8-54 8-54 8-55 8-55 8-55 8-56 8-56 8-57 8-57 8-57 8-58 8-58 8-58 8-59 8-60 8-60 8-60 8-61 8-62 8-62 8-62 8-62 8-63 8-63 8-64
Chapter Synopsys PrimeTime Support
Introduction Quartus Settings Generating PrimeTime Software Files Files Generated PrimeTime Software Environment Netlist File Generating Multiple Operating Conditions with TimeQuest Script Generated File Summary Running PrimeTime Software 9-10 Analyzing Quartus Projects 9-10 Other pt_shell Commands 9-11 PrimeTime Timing Reports 9-12 Sample PrimeTime Software Timing Report 9-12 Comparing Timing Reports from Quartus Classic Timing Analyzer PrimeTime Software 9-13 Clock Setup Relationship Slack 9-13 Clock Hold Relationship Slack 9-17 Input Delay Output Delay Relationships Slack 9-21 Static Timing Analyzer Differences 9-23
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Quartus Classic Timing Analyzer PrimeTime Software Rise/Fall Support Minimum Maximum Delays Recovery/Removal Analysis Encrypted Intellectual Property Blocks Registered Clock Signals Multiple Source Destination Register Pairs Latches LVDS Clock Latency Input Output Delay Assignments Generated Clocks Derived from Generated Clocks Quartus TimeQuest Timing Analyzer PrimeTime Software Encrypted Intellectual Property Blocks Latches LVDS Quartus TimeQuest Timing Analyzer File PrimeTime Compatibility Clock Data Paths Inverting Non-Inverting Propagation Multiple Rise/Fall Numbers Timing Virtual Generated Clocks Generated Clocks Derived from Generated Clocks Conclusion Referenced Documents Document Revision History
9-23 9-23 9-23 9-23 9-24 9-24 9-25 9-25 9-25 9-26 9-26 9-26 9-26 9-26 9-27 9-27 9-27 9-27 9-28 9-28 9-28 9-28 9-28 9-28 9-29
Section III. Power Estimation Analysis
Chapter PowerPlay Power Analysis
Introduction 10-1 Quartus Early Power Estimator File 10-2 PowerPlay Early Power Estimator File Generator Compilation Report 10-4 Types Power Analyses 10-6 Factors Affecting Power Consumption 10-6 Device Selection 10-6 Environmental Conditions 10-7 Flow 10-7 Heat Sink Thermal Compound 10-7 Ambient Temperature 10-8 Board Thermal Model 10-8 Design Resources 10-8 Number, Type, Loading Pins 10-8 Number Type Logic Elements, Multiplier Elements, Blocks 10-8 Number Type Global Signals 10-9 Signal Activities 10-9
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PowerPlay Power Analyzer Flow Operating Conditions 10-10 Signal Activities Data Sources 10-12 Simulation Results 10-12 Using Simulation Files Modular Design Flows 10-14 Complete Design Simulation 10-15 Modular Design Simulation 10-15 Multiple Simulations Same Entity 10-16 Overlapping Simulations 10-17 Partial Simulations 10-17 Node Name Matching Considerations 10-17 Glitch Filtering 10-18 Node Entity Assignments 10-20 Timing Assignments Clock Nodes 10-21 Default Toggle Rate Assignment 10-21 Vectorless Estimation 10-21 Using PowerPlay Power Analyzer 10-22 Common Analysis Flows 10-22 Signal Activities from Full Post-Fit Netlist (Timing) Simulation 10-22 Signal Activities from (Functional) Simulation, Supplemented Vectorless Estimation 10-22 Signal Activities from Vectorless Estimation, User-Supplied Input Activities 10-23 Signal Activities from User Defaults Only 10-23 Generating File Using Quartus Simulator 10-23 Generating File Using Third-Party Simulator 10-27 Running PowerPlay Power Analyzer Using Quartus 10-29 PowerPlay Power Analyzer Compilation Report 10-37 Summary 10-38 Settings 10-38 Simulation Files Read 10-38 Operating Conditions Used 10-38 Thermal Power Dissipated Block 10-38 Thermal Power Dissipation Block Type (Device Resource Type) 10-38 Thermal Power Dissipation Hierarchy 10-39 Core Dynamic Thermal Power Dissipation Clock Domain 10-39 Current Drawn from Voltage Supplies 10-39 Confidence Metric Details 10-39 Signal Activities 10-40 Messages 10-40 Specific Rules Reporting 10-40 Scripting Support 10-40 Running PowerPlay Power Analyzer from Command Line 10-41 Conclusion 10-42 Referenced Documents 10-42 Document Revision History 10-43
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Section Signal Integrity
Chapter Signal Integrity Analysis with Third-Party Tools
Introduction 11-1 Need FPGA Board Signal Integrity Analysis 11-3 Double Counting Problem FPGA Output Timing 11-4 Defining Double Counting Problem 11-4 Solution Double Counting 11-5 Model Selection: IBIS HSPICE 11-7 FPGA Board Signal Integrity Analysis Flow 11-8 Create Board Trace Model Assignments 11-10 Enable Output File Generation 11-10 Generate Output Files 11-10 Customize Output Files 11-11 Simulations Third-Party Tools 11-11 Interpret Simulation Results 11-12 Simulation with IBIS Models 11-12 Elements IBIS Model 11-12 Creating Accurate IBIS Models 11-13 Download IBIS Models 11-13 Generate Custom IBIS Models with IBIS Writer 11-14 Design Simulation Using Mentor Graphics HyperLynx Software 11-17 Configuring LineSim Altera IBIS Models 11-20 Integrating Altera IBIS Models into LineSim Simulations 11-21 Running Interpreting LineSim Simulations 11-24 Simulation with HSPICE Models 11-25 Supported Devices Signaling 11-26 Creating Accurate HSPICE Models 11-26 Creating HSPICE Model Files Using Quartus 11-27 Creating HSPICE Model Files Using Scripting Command Line 11-28 Customizing HSPICE Model Files 11-29 Design Simulation Using Synopsys HSPICE 11-30 Running HSPICE Simulations 11-30 Viewing Interpreting Tabular Simulation Results 11-31 Viewing Graphical Simulation Results 11-31 Making Design Adjustments Based HSPICE Simulations 11-33 Conclusion 11-35 Referenced Documents 11-36 Document Revision History 11-36
Section In-System Design Debugging
Chapter Quick Design Debugging Using SignalProbe
Introduction 12-1
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On-Chip Debugging Tool Comparison 12-2 Debugging Using SignalProbe Feature 12-4 Reserve SignalProbe Pins 12-4 Perform Full Compilation 12-6 Assign SignalProbe Source 12-6 Registers Pipeline Path SignalProbe 12-7 Perform SignalProbe Compilation 12-9 Analyze Results SignalProbe Compilation 12-10 Generate Programming File 12-11 SignalProbe flows 12-11 SignalProbe Flow with Quartus Incremental Compilation 12-11 SignalProbe Flow without Quartus Incremental Compilation 12-12 Common Questions About SignalProbe Feature 12-14 Following Error Message, "Error: There Enabled SignalProbes Process"? 12-14 Retain SignalProbe ECOs during Re-compilation Design? 12-14 SignalProbe Source Disappear Change Manager? 12-14 What Where Find More Information ECO? 12-15 Migrate Previous SignalProbe Assignments Quartus Software Versions below Versions Higher? 12-15 What Changes SignalProbe Feature between Quartus Software Version Earlier, Version Later? 12-16 Scripting Support 12-17 Make SignalProbe 12-17 Delete SignalProbe 12-17 Enable SignalProbe 12-18 Disable SignalProbe 12-18 Perform SignalProbe Compilation 12-18 Migrating Previous SignalProbe Pins Quartus Software Versions Later .12-18 Script Example 12-18 Using SignalProbe with APEX Device Family 12-19 Adding SignalProbe Sources 12-19 Performing SignalProbe Compilation 12-20 Running SignalProbe with Smart Compilation 12-21 Understanding Results SignalProbe Compilation 12-21 Analyzing SignalProbe Routing Failures 12-23 SignalProbe Scripting Support APEX Devices 12-23 Reserving SignalProbe Pins 12-24 Adding SignalProbe Sources 12-24 Assigning Standards 12-24 Adding Registers Pipelining 12-24 SignalProbe Automatically 12-25 SignalProbe Manually 12-25 Enable Disable SignalProbe Routing 12-25 Running SignalProbe with Smart Compilation 12-26 Allow SignalProbe Modify Fitting Results 12-26
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Conclusion 12-26 Referenced Documents 12-26 Document Revision History 12-27
Chapter Design Debugging Using SignalTap Embedded Logic Analyzer
Introduction 13-1 Hardware Software Requirements 13-3 On-Chip Debugging Tool Comparison 13-4 Design Flow Using SignalTap Logic Analyzer 13-7 SignalTap Logic Analyzer Task Flow 13-8 SignalTap Logic Analyzer Your Design 13-9 Configure SignalTap Logic Analyzer 13-9 Define Triggers 13-9 Compile Design 13-9 Program Target Device(s) 13-9 SignalTap Logic Analyzer 13-10 View, Analyze, Captured Data 13-10 SignalTap Logic Analyzer Your Design 13-10 Creating Enabling SignalTap File 13-10 Creating SignalTap File 13-10 Enabling Disabling SignalTap File Current Project 13-11 Using MegaWizard Plug-In Manager Create Your Embedded Logic Analyzer 13-12 Creating Representation Using MegaWizard Plug-In Manager 13-12 SignalTap Megafunction Ports 13-16 Instantiating SignalTap Logic Analyzer Your 13-16 Embedding Multiple Analyzers FPGA 13-17 Monitoring FPGA Resources Used SignalTap Logic Analyzer 13-17 Configure SignalTap Logic Analyzer 13-18 Assigning Acquisition Clock 13-18 Adding Signals SignalTap File 13-20 Signal Preservation 13-20 Node List Signal Options 13-22 Untappable Signals 13-22 Adding Signals with Plug-In 13-23 Specifying Sample Depth 13-24 Capturing Data Specific Type 13-25 Choosing Buffer Acquisition Mode 13-25 Circular Buffer 13-25 Segmented Buffer 13-26 Managing Multiple SignalTap Files Configurations 13-27 Define Triggers 13-29 Creating Basic Triggers 13-29 Creating Advanced Triggers 13-30 Examples Advanced Triggering Expressions 13-32 Creating Power-Up Trigger 13-33 Enabling Power-Up Trigger 13-33 Managing Configuring Power-Up Run-Time Trigger Conditions 13-34
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Contents
Using Multiple Trigger Levels Specifying Trigger Position Using External Triggers Trigger Trigger Using Trigger Analyzer Trigger Another Analyzer Compile Design Faster Compilations Using SignalTap Incremental Compilation Enable Incremental Compilation your Design Enable SignalTap Incremental Compilation Compiling without Incremental Compilation Preventing Changes Requiring Recompilation Timing Preservation with SignalTap Logic Analyzer Program Target Device(s) Programming Single Device Programming Multiple Devices Debug Multiple Designs SignalTap Logic Analyzer Running with Power-Up Trigger Running with Run-Time Triggers Performing Force Trigger SignalTap Status Messages View, Analyze, Captured Data Viewing Captured Data Creating Mnemonics Patterns Automatic Mnemonics with Plug-In Locating Node Design Saving Captured Data Converting Captured Data Other File Formats Creating SignalTap List File Other Features Using SignalTap MATLAB Function Capture Data Using SignalTap Environment Remote Debugging Using SignalTap Logic Analyzer Equipment Setup Software Setup Remote Software Setup Local SignalTap Setup Local SignalTap Scripting Support SignalTap Command Line Options SignalTap Commands Design Example: Using SignalTap Logic Analyzers SOPC Builder Systems Conclusion Referenced Documents Document Revision History
13-35 13-36 13-36 13-36 13-37 13-37 13-39 13-40 13-40 13-41 13-43 13-43 13-44 13-44 13-45 13-45 13-46 13-48 13-48 13-49 13-50 13-51 13-51 13-52 13-52 13-53 13-54 13-54 13-55 13-55 13-55 13-58 13-58 13-58 13-58 13-60 13-61 13-62 13-62 13-64 13-66 13-66 13-66 13-67
Chapter In-System Debugging Using External Logic Analyzers
Introduction 14-1
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Choosing Logic Analyzer 14-2 Required Components 14-2 FPGA Device Support 14-3 Debugging Your Design Using Logic Analyzer Interface 14-4 Creating Logic Analyzer Interface File 14-4 Creating Logic Analyzer Interface File 14-5 Opening Existing External Analyzer Interface File 14-6 Saving External Analyzer Interface File 14-7 Configuring Logic Analyzer Interface File Core Parameters 14-7 Mapping Logic Analyzer Interface File Pins Available Pins 14-9 Mapping Internal Signals Logic Analyzer Interface Banks 14-9 Using Node Finder 14-10 Enabling Logic Analyzer Interface Before Compiling Your Quartus Project 14-11 Compiling Your Quartus Project 14-12 Programming Your FPGA Using Logic Analyzer Interface 14-13 Using Logic Analyzer Interface with Multiple Devices 14-14 Configuring Banks Logic Analyzer Interface File 14-15 Acquiring Data Your Logic Analyzer 14-15 Advanced Features 14-15 Using Logic Analyzer Interface with Incremental Compilation 14-15 Creating Multiple Logic Analyzer Interface Instances FPGA 14-16 Conclusion 14-17 Document Revision History 14-18
Chapter In-System Updating Memory Constants
Introduction 15-1 Overview 15-1 Device Megafunction Support 15-2 Using In-System Updating Memory Constants with Your Design 15-3 Creating In-System Modifiable Memories Constants 15-3 Running In-System Memory Content Editor 15-4 Instance Manager 15-5 Editing Data Displayed Editor 15-7 Importing Exporting Memory Files 15-7 Viewing Memories Constants Editor 15-7 Scripting Support 15-9 Programming Device Using In-System Memory Content Editor 15-10 Example: Using In-System Memory Content Editor with SignalTap Embedded Logic Analyzer 15-10 Conclusion 15-11 Referenced Documents 15-11 Document Revision History 15-12
Chapter Design Debugging Using In-System Sources Probes
Introduction 16-1 Overview 16-1 Hardware Software Requirements 16-3
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Design Flow Using In-System Sources Probes 16-4 Configuring altsource_probes Megafunction 16-6 Instantiating altsource_probe Megafunction 16-8 Compiling Design 16-8 Running In-System Sources Probes Editor 16-9 Programming Your Device Using JTAG Chain Configuration Window 16-11 Instance Manager 16-12 Sources Probes Editor Window 16-13 Reading Probe Data 16-13 Writing Data 16-13 Data Organization 16-14 Support 16-14 Design Example: Dynamic Reconfiguration 16-18 Conclusion 16-21 Referenced Documents 16-21 Document Revision History 16-21
Section Formal Verification
Chapter Cadence Encounter Conformal Support
Introduction 17-1 Formal Verification Versus Simulation 17-2 Formal Verification: What Need Know 17-2 Formal Verification Design Flow 17-2 Quartus Integrated Synthesis 17-3 Tool Support Quartus Integrated Synthesis 17-3 Synplify 17-3 Tool Support Synplify 17-4 Coding Guidelines Quartus Integrated Synthesis 17-5 Synthesis Directives Attributes 17-5 Verilog Example Read Comments 17-5 VHDL Example Read Comments 17-6 Stuck-at Registers 17-6 ROM, LPM_DIVIDE, Shift Register Inference 17-8 Inference 17-8 Latch Inference 17-8 Combinational Loops 17-9 Finite State Machine Coding Styles 17-9 Generating Post-Fit Netlist Output File Encounter Conformal Setup Files 17-10 Command 17-14 17-14 Quartus Software Generated Files, Formal Verification Scripts, Directories 17-15 Understanding Formal Verification Scripts Encounter Conformal 17-17 Encounter Conformal Commands Within Quartus Software-Generated Scripts
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.17-17 Comparing Designs Using Encounter Conformal 17-20 Black Boxes Encounter Conformal Flow 17-20 Running Encounter Conformal Software 17-21 Running Encounter Conformal Software from 17-21 Running Encounter Conformal Software From System Command Prompt 17-22 Known Issues Limitations 17-23 Conclusion 17-25 Black Models 17-26 Conformal Dofile/Script Example 17-28 Referenced Documents 17-29 Document Revision History 17-30
Chapter Synopsys Formality Support
Introduction 18-1 Formal Verification 18-1 Equivalence Checking 18-1 Formal Verification Support 18-2 Tools Device Support 18-2 Formal Verification Between Post-Synthesis Netlist 18-2 Generating Post-Synthesis Netlist Formal Verification 18-3 FPGA Software Settings 18-3 Generating File Formality Script 18-4 Handling Black Boxes 18-9 Command 18-9 18-10 Quartus Scripts Formality 18-11 Comparing Designs Using Formality Software 18-11 Known Issues Limitations 18-12 Conclusion 18-12 Related Links 18-12 Sample Script 18-13 FPGA Synthesis Script 18-13 Quartus Software-Generated Formal Verification Script 18-14 Referenced Documents 18-15 Document Revision History 18-15
Section VII. Device Programming
Chapter Quartus Programmer
Introduction Programming Flow Programming Configuration Modes JTAG Mode Passive Serial Mode 19-1 19-1 19-4 19-4 19-4
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Active Serial Mode 19-5 In-Socket Programming Mode 19-5 Programmer Overview 19-6 Tools Menu 19-11 Hardware Setup 19-12 Hardware Settings 19-12 JTAG Settings 19-13 Device Programming Configuration 19-14 Single Device Programming Configuration 19-14 Multi-Device Programming Configuration 19-14 Bypassing Altera Device 19-15 Bypassing Non-Altera Device 19-15 Chain Description File 19-17 Design Security Programming 19-17 Optional Programming Files 19-18 Types Programming Configuration Files 19-18 Generating Optional Programming Files 19-20 Create Programming Files 19-20 Convert Programming Files 19-20 Generating Optional Programming Configuration Files During Compilation 19-21 Flash Loaders 19-21 Parallel Flash Loader 19-21 Serial Flash Loader 19-21 Other Programming Tools 19-22 Quartus Stand-Alone Programmer 19-22 jtagconfig Debugging Tool 19-22 Scripting Support 19-22 Conclusion 19-23 Referenced Documents 19-24 Document Revision History 19-24
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Chapter Revision Dates
chapters this book, Quartus Handbook, Volume were revised following dates. Where chapters groups chapters available separately, part numbers listed.
Chapter Quartus Simulator Revised: 2007 Part number: QII53017-7.1.0 Chapter Mentor Graphics ModelSim Support Revised: 2007 Part number: QII53001-7.1.0 Chapter Synopsys Support Revised: 2007 Part number: QII53002-7.1.0 Chapter Cadence NC-Sim Support Revised: 2007 Part number: QII53003-7.1.0 Chapter Simulating Altera Third-Party Simulation Tools Revised: 2007 Part number: QII53014-7.1.0 Chapter Quartus TimeQuest Timing Analyzer Revised: 2007 Part number: QII53018-7.1.0 Chapter Switching Quartus TimeQuest Timing Analyzer Revised: 2007 Part number: QII53019-7.1.0 Chapter Quartus Classic Timing Analyzer Revised: 2007 Part number: QII53004-7.1.0 Chapter Synopsys PrimeTime Support Revised: 2007 Part number: QII53005-7.1.0
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Chapter PowerPlay Power Analysis Revised: 2007 Part number: QII53013-7.1.0 Chapter Signal Integrity Analysis with Third-Party Tools Revised: 2007 Part number: QII53020-7.1.0 Chapter Quick Design Debugging Using SignalProbe Revised: 2007 Part number: QII53008-7.1.0 Chapter Design Debugging Using SignalTap Embedded Logic Analyzer Revised: 2007 Part number: QII53009-7.1.0 Chapter In-System Debugging Using External Logic Analyzers Revised: 2007 Part number: QII53016-7.1.0 Chapter In-System Updating Memory Constants Revised: 2007 Part number: QII53012-7.1.0 Chapter Design Debugging Using In-System Sources Probes Revised: 2007 Part number: QII53021-7.1.0 Chapter Cadence Encounter Conformal Support Revised: 2007 Part number: QII53011-7.1.0 Chapter Synopsys Formality Support Revised: 2007 Part number: QII53015-7.1.0 Chapter Quartus Programmer Revised: 2007 Part number: QII53022-7.1.0
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About this Handbook
This handbook provides comprehensive information about Altera® Quartus® design software, version 7.1.
Contact Altera
most up-to-date information about Altera products, refer following table. Information Type
Technical support Technical training Product literature Altera literature services site Note table:
also contact your local Altera sales office sales representative.
Contact
www.altera.com/mysupport/ www.altera.com/training/ custrain@altera.com www.altera.com/literature/ literature@altera.com ftp.altera.com
Third-Party Software Product Information
Third-party software products described this handbook Altera products, licensed Altera from third parties, subject change without notice. Updates these third-party software products concurrent with Quartus software releases. Altera assumed responsibility selection such third-party software products Quartus software release. extent that software products described this handbook derived from third-party software, third party warrants software, assumes liability regarding software, undertakes furnish support information relating software. EXCEPT EXPRESSLY FORTH APPLICABLE ALTERA PROGRAM LICENSE SUBSCRIPTION AGREEMENT UNDER WHICH THIS SOFTWARE PROVDED YOU, ALTERA THIRD-PARTY LICENSORS DISCLAIM WARRANTIES WITH RESPECT SUCH THIRD-PARTY SOFTWARE CODE DOCUMENTATION SOFTWARE, INCLUDING, WITHOUT LIMITATION, WARRANTIES MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, TITLE, NONINFRINGEMENT. more information, including latest available version specific third-party software products, refer documentation software question.
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Typographic Conventions
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Typographic Conventions
Visual
Bold Type with Initial Capital Letters bold type
This document uses typographic conventions shown below.
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \qdesigns directory, drive, chiptrip.gdf file. Document titles shown italic type with initial capital letters. Example: High-Speed Board Design. Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file.
Italic Type with Initial Capital Letters Italic type
Initial Capital Letters "Subheading Title"
Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles on-line help topics shown quotation marks. Example: "Typographic Conventions." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., resetn. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Courier type
etc.
Numbered steps used list items when sequence items important, such steps listed procedure. Used table cells indicate following: indicates "Yes" "Applicable" statement; indicates "No" "Not Supported" statement; indicates that table cell entry applicable item interest. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. caution calls attention condition possible situation that damage destroy product user's work. warning calls attention condition possible situation that cause injury user. angled arrow indicates should press Enter key. feet direct more information particular topic.
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Section Simulation
design complexity FPGAs continues rise, verification engineers finding increasingly difficult simulate their system-ona-programmable-chip (SOPC) designs timely manner. verification process bottleneck FPGA design flow. perform functional timing simulation your design using Quartus® Simulator. Quartus software also provides wide range features performing simulation designs simulation tools. This section includes following chapters:
Chapter Quartus Simulator Chapter Mentor Graphics ModelSim Support Chapter Synopsys Support Chapter Cadence NC-Sim Support Chapter Simulating Altera Third-Party Simulation Tools information about revision history chapters this section, refer each individual chapter that chapter's revision history.
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Simulation
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Quartus Simulator
QII53017-7.1.0
Introduction
With today's FPGAs becoming faster more complex, designers face challenges validating their designs. Simulation verifies correctness design, reducing board testing debugging time. Altera® offers Simulator part Quartus® software assist designers with design verification. Quartus Simulator comprehensive features that covered following sections:
"Simulation Flow" "Waveform Editor" page "Simulator Settings" page 1-17 "Simulation Report" page 1-25 "Debugging with Quartus Simulator" page 1-29 "Scripting Support" page 1-32
This chapter describes perform different types simulations with Quartus Simulator.
Simulation Flow
perform both functional timing simulations with Quartus Simulator. Both types simulation verify correctness behavior your design. Functional simulations beginning Quartus design flow timing simulations end. Figure shows Quartus Simulator flow.
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Figure 1-1. Simulation Flow
Design Entry .vwf/ .cvwf/ .vcd Convert Testbench
.vwf/.tbl/ .vec/.scf/ .cvwf/ .vcd
Input Stimulus
Test Bench File
.vt/.vht
Analysis Synthesis Netlist Writer Place Route (Fitter) Quartus Simulator Generate Functional Simulation Netlist Timing Analysis Fast Timing Analysis Simulator
Functional Netlist (db)
Netlist
Netlist
Timing Netlist (db)
Netlist
Fast Timing Netlist (db)
Functional Simulation
Timing Simulation
Timing Simulation Using Fast Timing Model Quartus Simulator
Simulation Report File
.rpt
.saf .vcd
Signal Activity File
Simulation Debugging
Requirements Satisfied?
Notes Figure 1-1:
more information Simulators, refer Simulation section volume Quartus Handbook. Signal Activity Files (.saf) Value Change Dump Files (.vcd) PowerPlay Power Analyzer check power resources.
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Simulation Flow
shown Figure 1-1, your design simulation happen functional level, where your design's logical behavior verified timing information used simulation. Timing simulation happen after your design been compiled (synthesized placed routed) after timing data your design's resources. Timing simulation, your design's logical behavior verified with device's worst-case timing models. Timing simulation using Fast Timing Model also type Timing simulation where best-case timing data used. perform functional simulations with Quartus Simulator, must first generate functional simulation netlist. functional netlist file flattened netlist extracted from design files that does contain timing information. timing simulations, must first perform place-and-route static timing analysis generate timing simulation netlist. timing simulation netlist includes timing delays each device atom block routing delays. want third-party simulation tools, generate netlist using Netlist Writer. this netlist with your testbench files third-party simulation tools.
more information about third-party simulators, refer respective Simulation chapter Simulation section volume Quartus Handbook. Quartus Simulator supports Functional, Timing, Timing using Fast Timing Model simulations. following sections describe perform these simulations.
Functional Simulation
functional simulation, perform following steps: Processing menu, click Generate Functional Simulation Netlist. This flattens functional simulation netlist extracted from design files. netlist does contain timing information. Assignments menu, click Settings. Settings dialog appears. Category list, select Simulator Settings. Simulator Settings page appears. Simulation mode list, select Functional.
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Simulation input box, specify vector source. must specify vector file simulation. Click Processing menu, click Start Simulation.
Timing Simulation
timing simulation, perform following steps: Processing menu, click Start Compilation click Compilation button toolbar. This flattens design generates internal netlist with timing delay information annotated. Assignments menu, click Settings. Settings dialog appears. Category list, select Simulator Settings. Simulator Settings page appears. Simulation Mode list, select Timing. Simulation input list, specify vector source. need specify vector file simulation. Click Processing menu, click Start Simulation.
Timing Simulation Using Fast Timing Model Simulation
timing simulation using fast timing model, perform following steps: Processing menu, point Start click Start Analysis Synthesis. Processing menu, point Start click Start Fitter. must perform fast timing analysis before perform timing simulation using fast timing models. Processing menu, point Start click Start Classic Timing Analyzer (Fast Timing Model).
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Waveform Editor
Assignments menu, click Settings. Settings dialog appears. Category list, select Simulator Settings. Simulator Settings page appears. Simulation mode list, select Timing using Fast Timing Model. Simulation input box, specify vector source. need specify vector file simulation. Click Processing menu, click Start Simulation.
Waveform Editor
most common input stimulus Quartus Simulator VWFs. Quartus Waveform Editor generate VWF.
Creating VWFs
create VWF, perform following steps: File menu, click New. dialog appears. Click Other Files tab, select Vector Waveform File. Click blank Waveform Editor window appears (Figure 1-2).
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Figure 1-2. Waveform Editor Window
nodes buses. node bus, Edit menu, click Insert click Insert Node Bus. Insert Node dialog appears (Figure 1-3). nodes buses, well internal signals, listed under Name Waveform Editor window. also open Insert Node dialog double-clicking under Name Waveform Editor.
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Waveform Editor
Figure 1-3. Insert Node Dialog
customize type node want add. have large design with many nodes buses, want Node Finder node selection. Node Finder, click Node Finder. Node Finder dialog appears (Figure 1-4).
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Figure 1-4. Node Finder Dialog
Name node want find List default filters Specify browse hierarchy design find node Customize your filters
nodes buses matching search criteria listed here
selected nodes buses placed here
Node Finder find your nodes simulation among nodes buses your design. Node Finder filter nodes your waveform. Node Finder equipped with multiple default filter options. using correct filter Node Finder, find internal node's name your Vector Waveform File simulation. Your node might appear simulation waveform might ignored during simulation. This happens because node been renamed synthesized away Quartus software. prevent this from happening, Altera recommends using register nodes simulate your design.
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Waveform Editor
Table describes twelve Node Finder default filters.
Table 1-1. Filter Options Filter
Pins: input Pins: output Pins: bidirectional Pins: virtual Pins:
Description
Finds input names your design file(s). Finds output names your design file(s). Finds bidirectional names your design file(s). Finds virtual names. Finds names your design file(s).
Registers: pre-synthesis Finds user-entered register names contained design after design elaboration, before physical synthesis does synthesis optimizations. Registers: post-fitting Finds user-entered register names your design file(s) that survived physical synthesis fitting.
Design Entry (all names) Finds user-entered names your design file(s). Post-Compilation SignalTap pre-synthesis SignalTap post-fitting SignalProbe Finds user-entered compiler-generated names that have location assignments survived fitting. Finds internal device nodes pre-synthesis netlist that analyzed SignalTap® Logic Analyzer. Finds internal device nodes post-fitting netlist that analyzed SignalTap Logic Analyzer. Finds SignalProbedevice nodes post-fitting netlist.
customize your filters Node Finder, perform following steps: Click Customize. Customize Filter dialog appears. configure settings, click New. Custom Filter dialog appears. Filter name box, type name custom filter. Copy settings from filter list, select filter setting. Click customize your filters Customize Filter dialog box.
Look box, view edit current search hierarchy path. type search hierarchy path browse hierarchy path clicking browse button.
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move search hierarchy selecting hierarchical names Select Hierarchy Level dialog box. This ensures that large design with many signals, specify which hierarchy would like node from reduce amount signals displayed. After have configured filter specified correct hierarchy Node Finder dialog box, click List display relevant nodes buses. Select node(s) bus(es) from Nodes Found list click include waveform, click include nodes buses displayed Nodes Found list. Click also nodes Waveform Editor dragging nodes from Project Navigator, Netlist Viewers, Block Diagram, dropping them into Waveform Editor. Create waveform signal. Quartus Waveform Editor toolbar includes some most common waveform settings, making waveform vector drawings easier user friendly. Figure shows options available Waveform Editor toolbar.
Figure 1-5. Waveform Editor Toolbar
Zoom Tool Text Find Unitialized High Impedence Don't Care (DC) Arbitrary Value Snap Grid
Forcing
Weak
Count Value
Selection Tool
Full Screen
Forcing Unknown Replace
Weak Unknown
Invert
Random Value Overwrite Clock Sort
Waveform Editing Tool
Forcing High
Weak High
After edit your waveform, save waveform. File menu, click Save Save dialog appears. Type your file name, specify file type, click Save.
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Waveform Editor
Instead using Node Finder insert your nodes your VWF, also drag-and-drop nodes from Netlist Viewer your Simulation Vector Waveform File. more information Netlist Viewers, refer Analyzing Designs with Quartus Netlist Viewers volume Quartus Handbook.
Count Value
Count Value applies count value increment value specified time interval. Instead manually editing values each node, Count Value feature Waveform Editor toolbar automatically creates counting values buses. This feature enables specify starting value bus, what time interval increment, when stop counting. also configure transition occurrences, while setting count type increment number. When click Count Value button Waveform Editor toolbar, Count Value dialog appears (Figure 1-6). also open Count Value dialog right-clicking selected node, pointing Value, clicking Count Value. Figure 1-6. Count Value Dialog
Clock
Clock feature Waveform Editor toolbar automatically generate clock wave, rather than drawing each clock triggering pulse. generate clock signal with Clock dialog box,
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click Overwrite Clock button Waveform Editor toolbar. Furthermore, determine start time clock signal, whether manually configure period (the offset duty cycle), whether generate clock based specified clock. Figure shows Clock dialog box. Figure 1-7. Clock Dialog
Arbitrary Value
Arbitrary Value allows overwrite node value over selected waveform, waveform interval, across more nodes groups. overwrite node value, perform following steps: Select node click Arbitrary Value button Waveform Editor toolbar (Figure 1-5). Arbitrary Value dialog appears (Figure 1-8). Under Time range, specify start time want overwrite node value. Radix list, select radix type. Specify value want overwritten Numeric named value box. Click
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Waveform Editor
Figure 1-8. Arbitrary Value Dialog
Random Value
Random Value allows generate random node values over selected waveform, waveform interval, across more nodes groups. Figure shows Random Values dialog box. generate random node values every grid interval, every half grid interval, random intervals, fixed intervals. Figure 1-9. Random Values Dialog
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Generating Testbench
export your VHDL Test Bench File (.vht) Verilog Test Bench File (.vt). This useful when want vector waveform different tools. must analysis elaboration before export waveform vector. export waveform vector, have your vector waveform open perform following steps: File menu, click Export. Export dialog appears. Save type list, select VHDL Test Bench File (*.vht) Verilog Test Bench File (*.vt). optionally turn self-checking code file. This option adds additional logic check results output compares original VWF. must open your project Quartus software before export VWF.
more information about using generated test bench other tools, refer respective simulator chapter Simulation section volume Quartus Handbook.
Grid Size
When select portions your waveform, selection area snaps time intervals specified Grid Size dialog box. customize grid size Waveform Editor. change grid size based clock settings setting time period. customize grid size, Edit menu, click Grid Size.
Time Bars
time bars Waveform Editor compare edges between different signals. also time bars jump forward backward next edge transition selected signal, read logic level signals sliding Time your waveform. logic level displayed Value column Waveform Editor. Time Organizer dialog enables create, delete, edit time bar, create master time bar. Only master time allowed waveform file. Time Organizer, Edit menu, point Time click Time Organizer. Under Existing time bars, Absolute time column, indicates master time (Figure 1-10).
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Waveform Editor
Figure 1-10. Time Organizer Dialog
Stretch Compress Waveform Interval
stretch compress waveform interval Waveform Editor, which enables analyze effects waveform. example, check behavior your design high speeds short interval using compress option compress waveform. also this feature delay transition signal stretching waveform. have specify original start time, time waveform want stretch compress. want stretch compress nodes buses, deselect nodes buses stretch compress feature. stretch compress waveform interval, Edit menu, point Value click Stretch Compress Waveform Interval. Stretch Compress Waveform Interval dialog appears. time value" time specified Stretch Compress Waveform Interval dialog cannot larger than "End Time" specified Simulator Settings page Settings dialog (Figure 1-12). Otherwise, Quartus software displays message indicating invalid time value.
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Time
Time setting enables change time VWF. time represents maximum length time VWF. specify time your preferred time unit, have different extension values different nodes buses. With waveform open, specify time performing following steps: Edit menu, click Time. Time dialog appears (Figure 1-11).
Figure 1-11. Time Dialog
Time box, specify time select time unit Time list. Under Default extension options, Extension value list, select value. Under time extension signal, select specific extension values each signal clicking Extension value column.
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Simulator Settings
options time dialog different settings than those under Simulation period Settings dialog box. Simulation period period that Quartus software simulates stimuli. time maximum length time VWF. information simulation period, refer Table page 1-19.
Arrange Group Order
arrange group Least Significant (LSB) Most Significant (MSB) order. arrange order, bottom. arrange order, bottom. arrange group order, perform following steps: Select that want change order. also select multiple buses waveform editor. Edit, point Group Order click either top, Bottom change group order click top, Bottom change group order.
Simulator Settings
enhance your output, reduce debugging time, provide better coverage before running simulation. This section covers different simulation modes supported Quartus Simulator. Additionally, Quartus Simulator offers common setup features like glitch filtering, setup hold violation detection, simulation coverage. setup simulation settings, perform following steps: Assignments menu, click Settings. Settings dialog appears. Category list, select Simulator Settings. Simulator Settings page appears (Figure 1-12).
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Figure 1-12. Simulator Settings Page
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Simulator Settings
Table shows options Simulator Settings page.
Table 1-2. Quartus Simulator Settings (Part Settings Options
Simulation mode
Description
Functional This simulation mode uses pre-synthesis compiler database simulate logical performance project without timing information. This mode enables check functionality design. nodes buses preserved this simulation because functional simulation performed before synthesis, partitioning, fitting. required perform this simulation mode. Timing This simulation mode takes compiled netlist that includes timing information. With this simulation mode, check setup, hold violation, glitches, simulation coverage. remove nodes buses using Quartus Compiler when logic optimized. This simulation mode uses worst case timing model. Timing using Fast Timing Model This simulation mode similar timing simulation this mode uses best-case timing model.
Simulation input
must include vector file Simulation input box. type name file browse button open Select File dialog box. Files type list, select Vector Waveform File (*.vwf), Compressed Vector Waveform File (*.cvwf), Value Change Dump File (*.vcd), Vector Table Output File (*.tbl), Vector Text File (*.vec), Simulation Channel File (.scf), Files (*.*). files contain input vectors output logic levels tabular-format list. generate this file using VWF. However, would like maintain, view, update vectors, VWFs offer better visibility. file formats interchangeable. generate files from VWFs vice versa. create with Waveform Editor. more information Waveform Editor, refer "Waveform Editor" page 1-5. Quartus software also supports MAX+PLUS® simulation vector files, such SCF. CVWF simplified version, non-readable, format format. This file type binary format generally smaller file size. CVWFs Waveform Editor simulation. file ASCII file which contains header information, variable definitions, value changes specified variables, variables, given design. value changes variable given scalar vector format, based nature variable.
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Table 1-2. Quartus Simulator Settings (Part Settings Options
Simulation period
Description
simulation period determines length time that simulator runs stimuli with maximum period being equal time VWF. simulation period configured shorter than time, signals beyond simulation period displayed Unknown (X). Therefore, also shorten simulation period simulation earlier selecting Simulation specifying time selecting time unit. simulation period configured longer than time, simulation will stop time. information time, refer "End Time" page 1-16. Specifies whether enable glitch filtering simulations. select following options: Auto-The Simulator performs glitch filtering when generation enabled Simulation Output Files page Settings dialog box. Always-The Simulator always performs glitch filtering, even generation enabled. Never-The Simulator never performs glitch filtering, even generation enabled.
Glitch filtering options
More Settings
click More Settings, More Simulator Settings dialog appears. following options available under Existing option settings. Cell Delay Model Type Specifies type delay model used cell delays: transport inertial. default transport. Interconnect Delay Model Type Specifies type delay model used interconnect delays: transport inertial. default transport. Preserve fewer signal transition reduce memory requirements This option effective lower performance workstations because turning this option flushes signal transitions from memory disk memory optimization.
Note Table 1-2:
Quartus Simulator flag error message zero-time oscillation happens your design. Zero-time oscillation happens when particular output signal does achieve stable output value particular fixed time, which your design containing combinational logic path loops.
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Simulator Settings
Simulation Verification Options
Figure 1-13 shows simulation verification page. Figure 1-13. Simulation Verification Page
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Table shows options simulation verification page.
Table 1-3. Quartus Simulation Verification (Part Settings Options
Check outputs
Description
Check outputs checks expected outputs against actual outputs simulation report. After turning Check outputs, click Waveform Comparison Settings button. Waveform Comparison Settings dialog appears. Waveform Comparison Settings dialog box, specify waveform comparison time frame comparison options. also tolerance level signals specifying tolerance limit Default comparison timing tolerance box. Maximum comparison mismatches amount mismatches Quartus Simulator allowed accept before stops comparing. also type transition comparison should trigger Waveform Comparison Settings dialog box. assign trigger comparisons based Input signal transition edges, signal transition edges, Selected Signal transition edges. customize waveform comparison matching rules, also click Comparison Rules button. Comparison Rules dialog appears, allowing customize comparison matching rules.
Setup hold time violation detection
This option detects setup hold time violation. Setup time period required synchronous signal stabilize before arrival clock edge. Hold time time required synchronous signal maintain after same clock edge. Setup hold time violation detection option turned warning Messages windows appears setup hold time violation detected during simulation. This option only Timing Timing using Fast Timing Model simulation modes. Conditions happen when more signals toggle simultaneously cause glitches unwanted short pulses. Glitch detection option enables detect glitches specify time interval that defines glitch. logic level transitions occur period shorter than specified time period, resulting glitch detected reported Processing Messages window. turn Glitch detection option, specify acceptable glitch width. Messages window appears when pulse smaller than specified glitch width that detected. Glitch detection option only available Timing Timing using Fast Timing Model simulation modes.
Glitch detection
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Simulator Settings
Table 1-3. Quartus Simulation Verification (Part Settings Options
Simulation coverage reporting
Description
This option reports ratio outputs (coverage) actually simulated number outputs netlist expressed percentage. When turn Simulation coverage reporting option, Report Settings button available. click Report Settings, Report Settings dialog appears. three types coverage reports select from Display complete value coverage report, Display missing 1-value coverage report, Display missing 0-value coverage report.
Disable setup hold time This option enables disable setup hold time violations detection violation detection input input registers bidirectional pins simulated design during Timing Timing using Fast Timing Model simulation. registers bi-directional pins
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Simulation Output Files Options
Figure 1-14 shows simulation output file page. Figure 1-14. Simulation Output Files Page
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Simulation Report
Table shows options simulation output file page.
Table 1-4. Quartus Simulation Output Files Setting Options
Simulation output waveform
Description
Specify simulation output waveform options. Automatically pins simulation output waveforms Automatically pins simulation output waveforms option automatically adds outputs that available design waveform reports. your design large amounts outputs, turning this option ensures outputs monitored during simulation. Overwrite simulation input file with simulation results This option overwrites vector source file with simulation results. This option ignored when Check outputs setting turned This option adds result vector file generally, give more visibility during debugging process. Group channel simulation results This option automatically groups channels output waveform that shown simulation reports. turning this option, output waveforms have node represent each signal.
Signal activity output power analysis output power analysis Notes Table 1-4:
When perform your simulation with Quartus Simulator, generate which used PowerPlay Power Analyzer assist with power analysis. (2), When perform simulation with Quartus Simulator, generate file, which used PowerPlay Power Analyzer assist with power analysis. (2),
backup copy source vector file saved under folder with name <project>.sim_ori. <vector file format type>. Instead using Generate file (*.vcd), also save your output waveform file perform power analysis. more information about PowerPlay Power Analyzer, refer PowerPlay Power Analysis chapter volume Quartus Handbook.
Simulation Report
Comprehensive reports shown after completion each simulation. These reports important ensure designs meet timing logical correctness. These simulation reports also play important role debugging.
Simulation Waveform
Simulation Waveforms part Simulation report. this report, stimuli results simulation displayed.
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export simulation waveform VHDL Test Bench File Verilog Test Bench File other tools. also save simulation Vector Table Output File with Quartus software. When edit Simulation Waveform, Edit Input Vector File dialog appears, asking whether would like edit vector input file with results simulation would like overwrite vector input file with other vector inputs (Figure 1-15). Figure 1-15. Edit Input Vector File
overwrite your simulation input file with simulation results that your input vector file updated with resulting waveform after simulation. more information, refer Overwrite simulation input file with simulation results option Table 1-2. want overwrite simulation input file every simulation run, perform following overwrite simulation input files with simulation results after simulation: Processing Menu, point Simulation Debug click Overwrite Vector Inputs with Simulation Outputs.
Simulating Bidirectional
bidirectional represented waveform channels. channel represents input bidirectional pin, other channel represents output from bidirectional pin. enter input channel into waveform using Node Finder dialog box. output channel automatically created Quartus Simulator named <bidir name> ~result.
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Simulation Report
Logical Memories Report
Quartus software writes contents each memory module after simulation. Therefore, memory cells your design, analyze contents logic memory structures device Logical Memories Report. Logical Memories Report displays individual reports each memory block contains data stored memory cell used simulation. After being simulated, memory module's contents stored Logical Memories section simulation report file. view this section, perform following steps: Processing menu, click Simulation Report. Simulation Report window appears. report window, click next Logical Memories.
Simulation Coverage Reports
Coverage Summary report contains following summary information simulation:
Total toggling coverage percentage Total nodes checked design Total output ports checked Total output ports with complete 1/0-value coverage Total output ports with 1/0-value coverage Total output ports with 1-value coverage Total output ports with 0-value coverage
Complete 1/0-Value Coverage report lists following information:
Node name Output port name Output port type output ports that toggle between during simulation
Missing 0-Value Coverage report Missing 1-Value Coverage report list following information:
Node name Output port name Output port type output ports that toggle designated value
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more information about Simulation Coverage reports, refer Simulation coverage reporting option Table page 1-19. following individual reports their definition: Complete value coverage report Displays nodes buses that toggle between during simulation. Missing 1-value coverage Missing 0-value coverage reports Displays nodes that toggle designated value.
Comparing Waveforms
compare your simulation results against previous simulations using compare option. compare waveforms Simulation Report, turn Check outputs option. more information Check outputs option, refer Table page 1-19. With Check outputs option turned comparable waveforms visible black red. black waveforms represent original output expected output, waveforms represent compared output actual output. Figure 1-16 shows example expected output waveform versus actual output waveform. Figure 1-16. Example Simulation Waveform from Simulation Report When Check Output Turned
Expected Output Waveform Black)
Actual Output Waveform Red)
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Debugging with Quartus Simulator
Debugging with Quartus Simulator
Quartus software includes tools help with simulation debugging. This section covers some debugging tools their use.
Breakpoints
Inserting breakpoints into simulation process enables simulator break desired time desired node condition. monitor activity nodes buses during specified times pinpoint cause mismatched signal levels between expected actual. breakpoints, perform following steps: Processing menu, point Simulation Debug click Breakpoints. Breakpoints dialog appears (Figure 1-17).
Figure 1-17. Breakpoints Dialog
Click create breakpoint. Breakpoint dialog appears. this dialog box, specify name, equation, action breakpoint. also enable disable this breakpoint using Enable Breakpoint check box. Equation text box, click condition. configure logical conditions individual nodes buses, time. After configure equation conditions, select action Quartus Simulator. Action drop down list, select Stop, Warning Message, Error Message, Information Message. This selection defines action once condition met.
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also enter text that appears when Simulator encounters breakpoint. make entry this box, Quartus software displays default message.
Updating Memory Content
your design includes memories, when simulator stops breakpoint, view edit contents memories. view your memories during breakpoint simulation, Processing menu, point Simulation Debug click Embedded Memory.
Last Simulation Vector Outputs
Last Simulation Vector Outputs command opens Output Simulation Waveforms report generated last simulation. this command, Processing menu, point Simulation Debug click Last Simulation Vector Outputs. open current input vectors that defined Simulator Settings dialog with Current Vector Inputs command. this command, Processing menu, point Simulation Debug click Current Vector Inputs. Lastly, overwrite vector source file with simulation outputs which open resulting file.
Conventional Debugging Process
During design phase, tapping internal signals common practice debug simulation errors. Therefore, Quartus software enables signal simulation debug also enables pull internal signal physical I/O. Quartus software also offers SignalTap SignalProbe further assist with debugging.
Accessing Internal Signals Simulation
conventionally debug probing internal signals, which enables preserve internal signals during synthesis. probe internal signal selecting node specifying name, then adding output port schematic with similar name. Figure 1-18 shows example accessing internal signals simulation from schematic diagram.
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Debugging with Quartus Simulator
Figure 1-18. Example Tapping Internal Signal
Both internal signal output port have same name. Accesing internal signal INTA.
timing simulations, simulation netlist based Compilation post-Synthesis post-Fitting netlist. Therefore, some internal nodes buses optimized away during compilation netlist. internal node optimized away, Quartus software shows warning Warning Messages window similar following message:
Warning: Compiler packed, optimized synthesized away node "DataU". Ignored vector source file node.
This internal node ignored Quartus Simulator. would like ports registers, turn ports register node Simulation Output Waveform from Assignment Editor. This feature only available functional simulations.
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Scripting Support
procedures make settings described this chapter script. also some procedures command prompt. detailed information about scripting command options, refer Quartus Command-Line Help browser. Help browser, type following command command prompt: quartus_sh -qhelp Scripting Reference Manual includes same information form.
more information about scripting, refer Scripting chapter volume Quartus Handbook. Refer Quartus Settings File Reference Manual information about settings constraints Quartus software. more information about command-line scripting, refer Command-Line Scripting chapter volume Quartus Handbook. change Functional, Timing, Timing using Fast Timing Model simulation modes with following command: simulation_mode <mode> initialize simulation current design, following command. During initialization, Simulator builds simulation netlist sets simulation time zero. option -ignore_vector_file default, when source vector file exists simulation. Quartus software ignores source vector file during simulation option -ignore_vector_file -end_time option used only when -ignore_vector_file option
initialize_simulation -help] [-long_help] [-check_outputs Off>] [-end_time <end_time>] [-glitch_filtering Off>] [-ignore_vector_file Off>] [-memory_limiter Off>] [-power_vcd_output <target_file>] [-read_settings_files Off>] [-saf_output <target_file>] [-sim_mode <functional timing timing_using_fast_timing_model [-vector_source <vector_source_file>] [-write_settings_files Off>] -simulation_results_format <VWF CVWF VCD> -vector_source <vector source file>
force specified signal group signals specified value, type following command prompt:
force_simulation_value -help] [-long_help] -node <hpath> <value>
turn simulator simulate design specified time, type following command prompt:
run_simulation -help] [-long_help] [-time <time>]
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Conclusion
specify length time simulation runs, runs until simulation complete.
create breakpoint with specified equation action, type following command prompt: create_simulation_breakpoint -help] [-long_help] -action [Give Warning Give Info Give Error] -breakpoint <breakpoint_name> -equation <equation> [-user_message <message_text>]r delete breakpoint with specified name, type following command prompt: delete_simulation_breakpoint -help] [-long_help] -breakpoint <breakpoint_name>
Conclusion
Simulation plays important role ensuring quality product. Quartus software offers various tools assist with simulation helps reduce debugging time with introduction features like Glitch Filtering Breakpoints. This chapter references following documents:
Referenced Documents
Section Simulation section volume Quartus Handbook Scripting chapter volume Quartus Handbook Quartus Settings File Reference Manual
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Document Revision History
Table shows revision history this chapter.
Table 1-5. Document Revision History Date Document Version
2007 v7.1.0
Changes Made
Updated command "Scripting Support" page 1-32. Updated "Breakpoints" page 1-29. Added procedure "Logical Memories Report" page 1-27. Updated sections, added sections deleted sections "Simulator Settings" page 1-17. Updated "Simulation Report" page 1-25. Updated Table page 1-19. Added "Arrange Group Order" page 1-17. Updated "Creating VWFs" page 1-5. Added "Referenced Documents" page 1-33.
Summary Changes
Updated Quartus software version 7.1.
March 2007 v7.0.0 Updated Quartus software revision date only. other changes made chapter. November 2006 v6.1.0 Updated Quartus software version 6.1. Added references Value Change Dump File (.vcd) Added Random Value section Other minor changes Initial release.
Updated Quartus software version 6.1.
2006 v6.0.0
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Mentor Graphics ModelSim Support
QII53001-7.1.0
Introduction
Altera® software subscription includes license ModelSim-Altera software UNIX platform. ModelSim-Altera software used perform functional register transfer level (RTL), post-synthesis, gate-level timing simulations either Verilog VHDL designs that target Altera FPGA. This chapter provides detailed instructions simulate your design ModelSim-Altera version Mentor Graphics® ModelSim® software version. This chapter gives details specific libraries that needed functional simulation gate-level timing simulation. This document describes using ModelSim-Altera software version 6.1g Mentor Graphics ModelSim software version 6.1g. also contains references features available Altera Quartus® software version 7.1. following topics discussed this chapter:
"Background" "Software Compatibility" page "Altera Design Flow with ModelSim ModelSim-Altera Software" page "Functional Simulation" page "Post-Synthesis Simulation" page 2-16 "Gate-Level Timing Simulation" page 2-23 "Simulating Designs that Include Transceivers" page 2-37 "Using NativeLink Feature with ModelSim" page 2-44 "Scripting Support" page 2-50 "Software Licensing Licensing Set-Up" page 2-51
more information about current Quartus software version, refer Altera website www.altera.com. ModelSim-Altera software version 6.1g included with your Altera software subscription licensed Solaris, Linux platforms support either Verilog VHDL hardware description language (HDL) simulation. ModelSim-Altera software supports VHDL Verilog functional RTL, post-synthesis, gate-level timing simulations Altera devices.
Background
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Table describes differences between Mentor Graphics ModelSim SE/PE ModelSim-Altera software versions.
Table 2-1. Comparison ModelSim Software Versions Product Feature
100% VHDL, Verilog, mixed-HDL support Complete debugging environment Optimized direct compile architecture Industry-standard scripting Flexible licensing Verilog support. Interfaces Verilog designs customer code third-party software VHDL support. Interfaces VHDL designs customer code third-party software Standard Delay Format File annotation Advanced debugging features language-neutral licensing Customizable, userexpandable graphical user interface integrated simulation performance analyzer Integrated code coverage analysis SWIFT support Accelerated VITAL Verilog primitives times faster), register transfer level (RTL) acceleration times faster) Platform support Precompiled Libraries Note Table 2-1:
ModelSim-Altera will only allow annotation modules Altera library.
ModelSim
Optional
ModelSim
Optional
ModelSim-Altera
Supports only single-HDL simulation
ModelSim-Altera Edition
Supports only single-HDL simulation
Optional
v(1)
UNIX, Linux
only
UNIX, Linux
only
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Software Compatibility
Software Compatibility
Table shows which ModelSim-Altera software version compatible with Quartus software versions. ModelSim versions provided directly from Mentor Graphics correspond specific Quartus software versions. help with ModelSim-Altera licensing refer "Software Licensing Licensing Set-Up" page 2-51.
Table 2-2. Compatibility Between Software Versions ModelSim-Altera Software
ModelSim-Altera software version 6.1g ModelSim-Altera software version 6.1d ModelSim-Altera software version 6.0e ModelSim-Altera software version 6.0c ModelSim-Altera software version 5.8.e ModelSim-Altera software version Note Table 2-2:
Updated ModelSim-Altera precompiled libraries available download Altera's website each release Quartus service pack.
Quartus Software
Quartus software version 6.1, 7.0, Quartus software version Quartus software version Quartus software version Quartus software version
Altera Design Flow with ModelSim ModelSimAltera Software
This chapter contains following sections:
Functional simulations Post-synthesis simulations Gate-level timing simulations Using NativeLink® feature with ModelSim
Figure illustrates Altera design flow using Mentor Graphics ModelSim software ModelSim-Altera software.
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Figure 2-1. Altera Design Flow with ModelSim-Altera Quartus Software
ALTERA Design Entry
Testbench
.v/.vhd
Functional Simulation
Synthesis
Functional Simulation Library Files
Verilog Output File VHDL Output File
.vo/.vho
Post-Synthesis Simulation
Place-and-Route
Post-Synthesis Simulation Library Files
Verilog Output File VHDL Output File
.vo/.vho
.sdo
Standard Delay Format Output File
Gate-Level Timing Simulation
Gate-Level Simulation Library Files
Note Figure 2-1:
performing functional simulation through NativeLink, must complete analysis elaboration first.
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Functional Simulation
Functional Simulation
functional simulation performed before gate-level simulation post-synthesis simulation. Functional simulation verifies functionality design before synthesis place-and-route. This section provides detailed instructions perform functional simulation ModelSim-Altera software highlights some differences performing similar steps Mentor Graphics ModelSim software versions Verilog VHDL designs.
Functional Simulation Libraries
Pre-compiled libraries available functional simulation with ModelSim-Altera software. These libraries include library altera_mf library. create these libraries simulation with ModelSim SE/PE software, compile library files described following sections.
Simulation Models
simulate designs containing functions, following functional simulation models:
220model.v (for Verilog HDL) 220pack.vhd 220model.vhd (for VHDL) When simulating design that uses VHDL-1987, 220model_87.vhd model file.
Table shows location these simulation model files precompiled libraries Quartus software ModelSim-Altera software.
Table 2-3. Location Simulation Models Files Pre-Compiled Libraries Software
Quartus ModelSim-Altera Notes Table 2-3:
ModelSim SE/PE, compile files provided with Quartus software. ModelSim-Altera, precompiled libraries simulation. <HDL> either Verilog VHDL.
Location
<Quartus installation directory>\eda\sim_lib\ <ModelSim-Altera installation (2),
more information about functions, refer Quartus Help.
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Altera Megafunction Simulation Models
simulate design that contains Altera megafunctions, following simulation models:
altera_mf.v (for Verilog HDL) altera_mf.vhd altera_mf_components.vhd (for VHDL) When simulating design that uses VHDL-1987, altera_mf_87.vhd.
Table shows location these simulation files precompiled libraries Quartus software ModelSim-Altera software.
Table 2-4. Location Altera Megafunction Simulation Models Files Precompiled Libraries Software
Quartus ModelSim-Altera Notes Table 2-4:
ModelSim SE/PE, compile files provided with Quartus software. ModelSim-Altera, precompiled libraries simulation. <HDL> either Verilog VHDL.
Location
<Quartus installation directory>\eda\sim_lib\ <ModelSim-Altera installation (2),
following Altera megafunctions require device atom libraries perform functional simulation third-party simulator:
altclkbuf altclkctrl altdqs altdq altddio_in altddio_out altddio_bidir altufm_none altufm_parallel altufm_spi altmemmult altremote_update
device atom library files located following directory: <Quartus installation directory>/eda/sim_lib
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Functional Simulation
Low-Level Primitive Simulation Models
simulate design that contains low-level Altera primitives with following simulation models:
altera_primitives.v (for Verilog HDL) altera_primitives.vhd (for VHDL)
Table shows location these simulation library files precompiled libraries Quartus software ModelSim-Altera software.
Table 2-5. Location Altera Primitives Model Files Precompiled Libraries Software
Quartus ModelSim-Altera Notes Table 2-5:
ModelSim SE/PE, compile files provided with Quartus software. ModelSim-Altera, precompiled libraries simulation. <HDL> either Verilog VHDL.
Location
<Quartus installation directory>\eda\sim_lib <ModelSim-Altera installation directory>\altera\<HDL>\altera (2),
Simulating VHDL Designs
following instructions perform functional simulation VHDL designs ModelSim software. steps following section assume have already created ModelSim project. ModelSim-Altera software comes with precompiled simulation libraries. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-9.
Create Simulation Libraries
Simulation libraries required simulate design that contains Altera primitive, function, Altera megafunction. These libraries have already been compiled using ModelSim-Altera software. However, using Mentor Graphics ModelSim software version, must create simulation libraries link them your design correctly.
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Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: ModelSim software, File menu, point click Library. Create Library dialog appears. Select library logical mapping Library Name box, type name newly created library. example, library name Altera megafunctions should altera_mf, library name should lpm. Click
Create Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vlib vmap vlib vmap vlib vmap altera_mf altera_mf altera_mf altera altera altera
Compile Simulation Models into Simulation Libraries
following steps required ModelSim-Altera software. Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, point Project click Existing File. Browse <Quartus installation directory>/eda/sim_lib necessary simulation model files your project. altera_mf.vhd model file should compiled into altera_mf library. 220pack.vhd 220model.vhd model files should compiled into library. Workspace window, select simulation model file, View menu, click Properties.
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Functional Simulation
Choose correct library from Compile Library list. Click Compile menu, click Compile selected.
Compile Simulation Models into Simulation Libraries ModelSim Command Prompt Type following commands ModelSim command prompt:
vcom vcom vcom vcom vcom vcom -work -work -work -work -work -work altera_mf <Quartus installation altera_mf <Quartus installation <Quartus installation <Quartus installation altera <Quartus installation altera <Quartus installation
Compile Testbench Design Files into Work Library
Compile testbench design files into work library clicking Compile clicking Compile toolbar icon Compile menu. Compile Testbench Design Files into Work Library Using ModelSim Command Prompt Type following command ModelSim command prompt: vcom -work work <my_test bench.vhd> <my_design_files.vhd>r Resolve compile-time errors before proceeding following section.
Loading Design
load design, perform following steps: Simulate menu, click Start Simulation. Start Simulation dialog appears. Expand work library Start Simulation dialog box. Select top-level design unit (your testbench). Resolution list, select Click
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Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim work.<my_test bench>
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays objects current scope. View menu, point Debug Windows click Wave. Drag signals monitor from Objects window drop them into Wave window. Type following command ModelSim command prompt: <time period> Running Simulation Using ModelSim Command Prompt Type following commands ModelSim command prompt: wave /<signal name> <time period>
Simulating Verilog Designs
following instructions provide step-by-step instructions perform functional simulation Verilog designs ModelSim software. following steps assume have already created ModelSim project. using ModelSim-Altera software, precompiled libraries created when install software. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-12.
Create Simulation Libraries
Simulation libraries needed properly simulate design that contains function Altera megafunction. These libraries have already been compiled using ModelSim-Altera software.
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Functional Simulation
However, using Mentor Graphics ModelSim software version, must create simulation libraries correctly link them your design. Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: File menu, point click Library. Create Library dialog appears. Select library logical mapping Library Name box, type name newly created library. example, library name Altera megafunctions should altera_mf, library name should lpm. Click
Create Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vlib vmap vlib vmap vlib vmap altera_mf altera_mf altera_mf altera altera altera
Compile Simulation Models into Simulation Libraries
following steps required ModelSim-Altera software. Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, point Project click Existing File. Browse <Quartus installation directory>/eda/sim_lib necessary simulation model files your project. Compile altera_mf.v into altera_mf library. Compile 220model.v into library.
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Select simulation model file View menu, click Properties. Choose correct library from Compile Library list. Click Compile menu, click Compile selected.
Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt:
vlog -work altera_mf <Quartus installation vlog -work <Quartus installation vlog -work altera <Quartus installation
Compile Testbench Design Files into Work Library
Compile testbench design files into work library Compile menu clicking Compile clicking Compile toolbar icon Compile menu. Compile Testbench Design Files into Work Library Using ModelSim Command Prompt Type following command ModelSim command prompt: vlog -work work <my_test bench.v> <my_design_files.v>r Resolve compile-time errors before proceeding following section.
Loading Design
Perform following steps load design: Simulate menu, click Start Simulation. Start Simulation dialog appears. Click Libraries tab. Search Libraries box, click Add. Specify location altera_mf simulation libraries.
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Functional Simulation
using ModelSim-Altera version, refer Table page Table page location precompiled simulation libraries. using Mentor Graphics ModelSim software version, browse library that created earlier. Load Design dialog box, click Design expand work library. Select top-level design unit (your testbench). Resolution list, select Click
Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim altera_mf work.<my_test bench>
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays objects current scope. View menu, point Debug Windows click Wave. Drag signals monitor from Objects window drop them into Wave window. Type following command ModelSim command prompt: <time period> Running Simulation Using ModelSim Command Prompt Type following commands ModelSim command prompt: wave /<signal name> <time period>
Verilog Functional Simulation with Altera Memory Blocks
Both ModelSim software products support simulating Altera memory megafunctions initialized with Hexadecimal (Intel-Format) File (.hex) initialization files (.rif).
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Although synthesis able read Memory Initialization File (.mif), this memory file supported with third-party tools must converted either Hexadecimal (Intel-Format) File Initialization File. Table summarizes different types memory initialization file formats that supported with each language.
Table 2-6. Simulation Support Memory Initialization Files File
Hexadecimal (Intel-Format) File Memory Initialization File Initialization File Notes Table 2-6:
memories library files from Quartus software version earlier, must library containing convert_hex2ver function. Requires USE_RIF macro defined, described later this section.
Verilog
VHDL
simulate your design converting your Memory Initialization File into either Hexadecimal (Intel-Format) File Initialization File, perform following steps: Convert Memory Initialization File Hexadecimal (Intel-Format) File Initialization File Quartus software. Converting Memory Initialization File Hexadecimal (Intel-Format) File Open Memory Initialization File. File menu, click Save Save dialog appears. Save type list, select Hexadecimal (Intel-Format) File (*.hex). Click
Convert Memory Initialization File Initialization File Open Memory Initialization File File menu, click Export. Export dialog appears. Save type list, select Initialization File (*.rif).
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Functional Simulation
Click
Alternatively, convert Memory Initialization File Initialization File using mif2rif.exe utility located <Quartus installation>/bin directory. mif2rif <mif_file> <rif_file> Modify file generated MegaWizard® Plug-In Manager. Altera memory custom megafunction variation file includes lpm_file parameter memories such LPM_ROM, init_file Altera specific memories such altsyncram, point initialization file. text editor, open custom megafunction variation file edit lpm_file init_file point Hexadecimal (Intel-Format) File Initialization File, shown following example: lpm_ram_dp_component.lpm_file "<path HEX/RIF>" Compile functional library files with compiler directives. Hexadecimal (Intel-Format) File, compiler directives required. Initialization File, must define USE_RIF macro when compiling model library files. example, should enter following when compiling altera_mf library when Initialization File memory initialization files used: vlog -work altera_mf altera_mf.v +define+USE_RIF=1 Quartus software versions earlier, must define NO_PLI macro instead USE_RIF. NO_PLI macro forward compatible with Quartus software.
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Post-Synthesis Simulation
post-synthesis simulation verifies functionality design after synthesis been performed. create post-synthesis netlist Quartus software this netlist perform post-synthesis simulation ModelSim. Once post-synthesis version design verified, next step place-and-route design target device using Quartus Fitter.
Generating Post-Synthesis Simulation Netlist
following steps describe process generating post-synthesis simulation netlist Quartus software: Perform Analysis Synthesis. Processing menu, point Start click Start Analysis Synthesis (you also perform this after step Turn Generate Netlist Functional Simulation Only option performing following steps: Assignments menu, click Tool Settings. Settings dialog appears. Category list, select Simulation. Simulation page appears. Tool name list: using ModelSim-Altera software, select ModelSim-Altera. using Mentor Graphics ModelSim software, select ModelSim.
Under Netlist Writer options, Format output netlist list, select VHDL Verilog. also modify where want post-synthesis netlist generated editing browsing directory Output directory box. Click More Settings. More Tools Simulation Settings dialog appears. Existing options settings list, click Generate Netlist Functional Simulation Only select from Setting list under Option. Click Settings dialog box, click
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Post-Synthesis Simulation
Netlist Writer. Processing menu, point Start click Start Netlist Writer. During Netlist Writer stage, Quartus software produces Verilog Output File (.vo) VHDL Output File (.vho) that used post-synthesis simulations ModelSim software. This netlist file mapped architecture-specific primitives. timing information included this stage. resulting netlist located output directory specified Settings dialog box, which defaults <project directory>/simulation/modelsim directory.
Simulating VHDL Designs
following instructions help perform post-synthesis simulation VHDL design ModelSim software. following steps assume have already created ModelSim project. using ModelSim-Altera software, precompiled libraries created when install software. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-9.
Create Simulation Libraries
Simulation libraries required simulate design that mapped post-synthesis primitives. using Mentor Graphics ModelSim software version, must create simulation libraries correctly link them your design. This process required with ModelSim-Altera version because pre-compiled libraries installed with software.
Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: File menu, click Library. Create Library dialog appears. Select Library logical linking Library Name box, type name newly created library.
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Click
Create Simulation Libraries Using ModelSim Command Prompt Type following commands create simulation libraries: vlib <device family name> vmap <device family name> <device family name> more information about library names, refer Table page 2-28. Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, point Project click Existing File. Browse <Quartus installation directory>/eda/sim_lib directory necessary gate-level simulation files your project. Select simulation model file View menu, click Properties. Compile Library list, select correct library. Click Compile menu, click Compile selected.
Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vcom -work <device family name> <Quartus installation directory> /eda/sim_lib/<device family name>_atoms.vhd vcom -work <device family name> <Quartus installation directory> /eda/sim_lib/<device family name>_components.vhd
Compile Testbench VHDL Output File into Work Library
compile testbench VHDL Output Files into work library, Compile menu, click Compile click Compile toolbar icon Compile menu.
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Post-Synthesis Simulation
Compile Testbench VHDL Output File into Work Library Using ModelSim Command Prompt Type following command ModelSim command prompt: vcom -work work <my_test bench.vhd> <my_vhdl_output_file.vho>r Resolve compilation errors before proceeding following section.
Loading Design
Perform following steps load design: Simulate menu, click Simulate. Click Design tab. Library list, select work library. Simulate dialog box, expand work library select top-level design unit (your testbench). Click
Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim work.<my test bench> 1psr time scale resolution when simulating Altera FPGA designs.
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays ob
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