QII55003-7.1.0 Core Overview Scatter-Gather direct memory ac

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Scatter-Gather Controller Core
QII55003-7.1.0
Core Overview
Scatter-Gather direct memory access (SG-DMA) controller core implements high-speed data transfer between devices. SG-DMA core used transfer data from:
memory memory data stream memory memory data stream.
SG-DMA controller core transfers merges non-contiguous memory continuous address space. also transfers contiguous memory non-contiguous memory. core operates reading series descriptors that specify data transferred. applications requiring more than channel, multiple instantiations core provide required throughput. Each SG-DMA controller series descriptors specifying data transfers. single software module controls channels. SG-DMA controller core SOPC Builder-ready integrates easily into SOPC Builder-generated system. Nios® processor, device drivers provided system library allowing software access core using ANSI Standard Library stdio.h routines.
Example Systems
Figure shows SG-DMA controller core block diagram sub-system printed circuit board. SG-DMA core FPGA reads streaming data from internal streaming component writes data external memory. Nios processor provides overall system control. descriptor table, containing linked list descriptors specifying data transfers executed, located FPGA external memory. Locating this table external memory will free resources FPGA; however, external descriptor table will increase overhead involved when descriptor processor reads updates table. SG-DMA core internal FIFO store descriptors read from memory which allows perform descriptor read, execute write back operations parallel, hiding descriptor read latency.
Altera Corporation 2007
Quartus Handbook, Volume
Figure 5-1. Scatter-Gather Controller Core with Streaming Peripheral External Memory
Printed Circuit Board SOPC Builder System Scatter Gather Controller Core Descriptor Processor
Write
Cntl Status Regs
system Interconnect fabric
system interconnect fabric
Memory Nios Cntl
Descriptor Table
Streaming Component
DDR2 Memory
Avalon-MM Master Port
Avalon-MM Slave Port
Avalon-ST Sink Port
Figure shows different SG-DMA controller core. Figure 5-2, SG-DMA core transfers data between internal external memory. host processor memory system bus, typically either PCI-Express Serial RapidIOTM.
Altera Corporation 2007
Scatter-Gather Controller Core
Figure 5-2. Scatter-Gather Controller Core with Internal External Memory
Printed Circuit Board SOPC Builder System Scatter Gather Controller Core Descriptor Processor Rd/Wr
Internal Memory
Cntl Status Regs
system interconnect fabric
Avalon-MM Bridge
processor
Host Processor
Main Memory
Descriptor Table
Avalon-MM Master Port Avalon-MM Slave Port Breakout
Figures illustrate systems using SG-DMA controller core omit some internals core itself. Figure page illustrates SG-DMA controller core internals.
Resource Usage Performance
Resource utilization core 600-1400 LEs, depending upon width datapath, parameterization core, type data transfer. Table provides resource utilization SG-DMA
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Quartus Handbook, Volume
controller core used memory memory transfer. core highly parameterized resource utilization will vary with configuration specified.
Table 5-1. SG-DMA Estimated Resource Usage Datapath
8-bit datapath 32-bit datapath 256-bit datapath
Cyclone®
1100 1400
Stratix® (Approx. Stratix (Approx. ALUTs) LEs)
1200 1000
core operating frequency varies with device size datapath. Table provides example expected performance SG-DMA cores instantiated several different device families.
Table 5-2. SG-DMA Performance Estimates Device
Cyclone Cyclone Stratix II/Stratix Stratix
Datapath
bits bits bits bits
Fmax
Throughput
Gbps 10.2 Gbps 16.0 Gbps 19.2 Gbps
Comparison SG-DMA Controller Core Controller Core
SG-DMA controller core provides significant performance enhancement over previously available controller core which could only perform single transfer time. With older controller core, performed separate reads each entry descriptor table then executed separate writes program controller perform transfer. Transfers non-contiguous memory could linked; consequently, overhead substantial small transfers, degrading overall system performance. contrast, SG-DMA controller core reads series descriptors from memory that describe required transactions performs transfers without additional intervention from CPU.
Altera Corporation 2007
Scatter-Gather Controller Core
Functional Description
SG-DMA controller core comprises three major blocks: descriptor processor, read block write block. (See Figure page 5-7.) These blocks combined create three different configurations:
memory memory memory stream stream memory
memory-to-memory configuration, core includes three blocks. core configured memory-to-stream transactions, only descriptor processor read blocks required. core configured stream-to-memory transactions, only descriptor processor write blocks required. memory-to-memory configuration, internal FIFO holds data being transferred between read write blocks. other configurations, external FIFO might required depending upon throughput components being connected. designs requiring external FIFO on-chip FIFO memory available SOPC Builder used. following sections describe three configurations SG-DMA controller core behavior internal modules each configuration.
Memory-to-Memory Configuration
Figure illustrates, memory-to-memory configuration includes five Avalon-MM ports. descriptor processor block uses read write Avalon-MM master ports access update descriptors. read block Avalon-MM master read port read data from memory; Avalon-ST port pass data write block. write block Avalon-ST port receive data from read block Avalon-MM master write port write data memory. Software accesses Avalon-MM slave port read write control status registers. memory-to-memory configuration, descriptor processor reads descriptors from descriptor table pushes appropriate commands onto input FIFOs read write blocks. also receives status token from read write block after each descriptor been processed. status token contains information about status transfer, including number bytes transferred. descriptor processor then writes this information back appropriate entry descriptor table.
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Quartus Handbook, Volume
memory-to-memory configuration, internal data FIFO stores data being transferred between read write blocks provide buffering flow control. execute read transfer between memories, following steps executed: Software writes descriptor into memory. Software writes location first descriptor address SG-DMA controller hardware initiates transfer setting SG-DMA control register. descriptor processor reads descriptors from memory writes them into command FIFO which feeds commands both read write blocks. read block gets source address from command FIFO reads data fill FIFO stream port. read block continues reading until specified number bytes have been transferred. data FIFO ever fills, read block pauses until FIFO accept more data. write block gets destination address from command FIFO. write block continues execute writes until specified number bytes have been transferred. then sends status update controller. data FIFO ever empties, write block pauses until FIFO more data write. descriptor processor updates appropriate entry descriptor table.
Figure illustrates possible configuration memory-tomemory SG-DMA controller with internal Nios processor descriptor table.
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Scatter-Gather Controller Core
Figure 5-3. Scatter-Gather Controller Core Memory-toMemory Configuration
SOPC Builder System Scatter Gather Controller Core
Write
Descriptor Processor
Status Status
Data FIFO
Cntl Status Regs
Read
system interconnect fabric
Nios Processor
Memory
Descriptor Table
Memory Controller offchip memory
Avalon-MM Master Port Avalon-MM Slave Port Avalon-ST Source Port Avalon-ST Sink Port
Memory-to-Stream Configuration
memory-to-stream configuration includes descriptor processor read block. Figure illustrates, this configuration includes four Avalon-MM ports Avalon-ST port. descriptor processor block includes read write Avalon-MM master ports
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Quartus Handbook, Volume
access update descriptors. read block Avalon-MM master read port read data from memory Avalon-ST port write data streaming component. Avalon-MM slave port used read write control status registers. Figure page illustrates SG-DMA controller memoryto-stream configuration. this example, Nios processor descriptor table inside FPGA. Data from external DDR2 memory read SG-DMA controller written internal streaming peripheral. read block returns status descriptor processor upon completion each descriptor.
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Scatter-Gather Controller Core
Figure 5-4. Scatter-Gather Controller Memory-to-Stream Configuration
SOPC Builder System
Scatter Gather Controller Core Descriptor Processor Status Read
Cntl Status Regs
system interconnect fabric
system interconnect fabric
Memory Controller
Memory
Descriptor Table
Nios Processor
Streaming Component
DDR2 Memory
Avalon-MM Master Port Avalon-MM Slave Port Avalon-ST Source Port Avalon-ST Sink Port
transfer operation includes following steps: Software writes descriptor into memory. Software writes location first descriptor address SG-DMA controller hardware initiates transfer setting SG-DMA control register.
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descriptor processor reads descriptors from memory writes them into input command FIFO read block. read block reads from source address pushes data stream port. read block continues reads until specified number bytes have been transferred. then sends status update descriptor processor. descriptor processor updates appropriate entry descriptor table.
Stream-to-Memory Configuration
stream-to-memory configuration includes descriptor processor write block. write block returns status descriptor processor upon completion each descriptor. This configuration similar memory-to-stream configuration except that data flows from streaming component memory device Figure illustrates. this example, On-Chip FIFO Memory component used provide buffer between streaming component write. transfer operation includes following steps: Software writes descriptor into memory. Software writes location first descriptor address SG-DMA controller hardware initiates transfer writing SG-DMA control register. descriptor processor reads descriptors from memory writes them into write block. write block reads from stream port writes data Avalon master port. write block continues reads until specified number bytes have been transferred. then sends status update descriptor processor. descriptor processor updates appropriate entry descriptor table.
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Scatter-Gather Controller Core
Figure 5-5. Scatter-Gather Controller Stream-to-Memory Configuration
SOPC Builder System
Scatter Gather Controller Core Descriptor Processor Status Write
Cntl Status Regs
system interconnect fabric
system interconnect fabric
Memory Controller
Memory
Descriptor Table
Nios Processor
On-Chip FIFO Memory
offchip memory
Streaming Component
Avalon-MM Master Port Avalon-MM Slave Port Avalon-ST Source Port Avalon-ST Sink Port
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Possible Sources Errors
SG-DMA core parameterizable error width. Error signals wired directly Avalon-ST source sink which SG-DMA core connected. Table lists error signals when core operating memory stream configuration connected transmit FIFO interface Altera Triple-Speed Ethernet MegaCore®.
Table 5-3. Avalon-ST Transmit Channel Error Types Signal Type
TSE_transmit_error[0]
Description
Transmit Frame Error. Asserted indicate that transmitted frame should viewed invalid Ethernet MAC. frame then transferred onto GMII interface with error code during frame transfer.
Table lists error signals when core operating streamto-memory configuration connected transmit FIFO interface Altera Triple-Speed Ethernet MegaCore.
Table 5-4. Avalon-ST Receive Channel Error Types Signal Type
TSE_receive_error[0] TSE_receive_error[1] TSE_receive_error[2] TSE_receive_error[3] TSE_receive_error[4] TSE_receive_error[5]
Description
Receive Frame Error. This signal indicates that error occurred. logical receive errors through Invalid Length Error. Asserted when received frame invalid length defined IEEE 802.3 standard. Error. Asserted when frame been received with CRC-32 error. Receive Frame Truncated. Asserted when received frame been truncated receive FIFO overflow Received Frame corrupted error. (The asserted error receive GMII interface.) Collision Error. Asserted when frame received with collision
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Scatter-Gather Controller Core
Detailed Description Each Block
following sections provide detailed description each functional block.
Descriptor Processor Block
descriptor processor reads descriptors from memory using Avalon-MM descriptor read master port pushes commands onto command FIFOs read write blocks. command includes following fields specify transfers:
source address destination address read size write size bytes transfer increment read address after each transfer increment write address after each transfer generate packet
Read Block
read block reads commands from input command FIFO. each command, reads data from source address Avalon-MM port. memory-to-memory configuration, pushes data into data FIFO. memory-to-stream configuration, immediately writes data Avalon-ST source port. read block will begin Avalon-MM read unless data FIFO enough space store data read. This restriction requires external FIFO least deep maximum supported read size.
Write Block
write block reads commands from input command FIFO. each command, writes data received Avalon-ST sink port destination address. memory-to-memory stream-tomemory configurations, reads data from Avalon-ST port writes Avalon-MM port.
Device Support Tools
SG-DMA controller core supports ArriaGX, Stratix® III, Stratix Stratix Stratix, Cyclone® III, Cyclone Cyclone Hardcopy® device families.
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Instantiating Core SOPC Builder
Designers SG-DMA controller core's SOPC Builder configuration wizard specify core configuration. following sections describe available options configuration wizard.
Transfer Mode
This list allows select between Memory Memory, Memory Stream Stream Memory configurations. more information about these configurations, "Memory-to-Memory Configuration" page 5-5, "Memory-to-Stream Configuration" page 5-7, "Streamto-Memory Configuration" page 5-10.
Allow Unaligned Transfers
Allow unaligned transfers data transfers data widths that power will aligned word boundaries. Unaligned transfers require extra logic that negatively impact system performance.
Data Error Widths
Data width list allows select data width bits Avalon-MM read write ports. Source error width Sink error width lists allow select widths error signals Avalon-ST source sink ports.
FIFO Depth
Data transfer FIFO depth list sets depth three descriptor FIFOs:
Descriptor Processor block FIFO read block FIFO, write block FIFO.
Data transfer FIFO depth list also sets depth internal data FIFO used memory-to-memory configuration. These FIFOs illustrated Figure page 5-7. read block will begin Avalon-MM read unless data FIFO enough space store data read. This restriction requires FIFO least deep maximum supported read size.
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Scatter-Gather Controller Core
Hardware Simulation Considerations Software Programming Model
Signals hardware simulation will automatically generated will show part Nios simulation accessible from Nios IDE. menu, point click Nios Modelsim.
following sections describe software programming model SG-DMA controller core.
System Library Support
Altera-provided driver implements device driver that integrates into system library Nios systems. users should access SG-DMA controller core familiar ANSI standard library.
Software Files
SG-DMA controller provides following software files. These files provide low-level access hardware drivers that integrate into Nios system library. Application developers should modify these files.
altera_avalon_sgdma_regs.h defines core's register map, providing symbolic constants access low-level hardware altera_avalon_sgdma.h provides definitions Altera Avalon SG-DMA buffer control status flags. altera_avalon_sgdma.c provides function definitions code that implements SG-DMA controller core. defines core's descriptor, providing symbolic constants access low-level hardware.
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Programming with SG-DMA Controller
This section describes software constructs programming SG-DMA Controller.
Table 5-5. SG-DMA Controller Functions Function Name
Description
Sets begins non-blocking transfer more descriptors descriptor chain. Sends fully formed descriptor, list descriptors, SG-DMA Controller transfer. This function will block both before transfer controller busy until requested transfer completed. Constructs single SG-DMA descriptor specified memory Avalon-MM Avalon-MM transfer. Constructs single SG-DMA descriptor specified memory Avalon-ST Avalon-MM transfer. Constructs single SG-DMA descriptor specified memory Avalon-MM Avalon-ST transfer. Reads status register descriptor. Associates user-specific routine with SG-DMA interrupt handler. Starts engine. Stops engine. Retrieves pointer SG-DMA controller with given name.
_desc() mem_desc() eam_desc() alt_avalon_sgdma_check_ descriptor_status() alt_avalon_sgdma_start() alt_avalon_sgdma_stop() alt_avalon_sgdma_open()
Software Control
host processor programs SG-DMA writing control register. host processor reads SG-DMA status register determine current status.
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Table shows offsets control status registers.
Table 5-6. SG-DMA Control Status Slave Register Offset
base base base
Register Name
status control
next_descriptor_pointer
Software writes control register specify behavior SG-DMA controller. This register determines conditions under which SG-DMA controller will generate interrupt. also includes control bits used start stop processing descriptors. Table provides bit-map control register.
Table 5-7. SG-DMA Control Register (Part
Name
IE_ERROR IE_EOP_ENCOUNTERED IE_DESCRIPTOR_COMPLETED IE_CHAIN_COMPLETED IE_GLOBAL
Rd/Wr/Clr
Description
Assert interrupt when (ERROR Assert interrupt when (EOP_ENCOUNTERED Assert interrupt when (DESCRIPTOR_COMPLETED Assert interrupt when (CHAIN COMPLETED =1). Global signal enable interrupts. SG-DMA processes descriptors queue long SG-DMA will process next descriptor queue when Setting starts descriptor processor which initiates transactions. Clearing will stop processing descriptor processing already begun. Stops after current descriptor ERROR detected. Enables interrupts when
STOP_DMA_ER IE_MAX_DESC_ PROCESSED MAX_DESC_ PROCESSED SW_RESET
MAX_DESC_PROCESSED reached.
Specifies number descriptors process before invoking interrupt. Resets SG-DMA hardware stops operations immediately.
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Table 5-7. SG-DMA Control Register (Part
Note Table 5-7:
Available interrupt coalescing selected synthesis options.
Name
Rd/Wr/Clr
reserved
Description
Table provides bit-map status register.
Table 5-8. SG-DMA Status Register
Notes Table 5-8:
This must cleared after read performed. Write clear this bit. This updated hardware after each transfer completes. remains until software writes clear. This continuously updated hardware.
Name
ERROR EOP_ENCOUNTERED DESCRIPTOR_COMPLETED CHAIN_COMPLETED BUSY
Rd/Wr/Clr
(1)(2) (1)(2) (1)(2) (1)(3))
Description
Avalon-ST error encountered during transfer. Transfer terminated Avalon-ST EOP. descriptor processed completion. Unable process next descriptor because Owned Indicates that descriptors being processed, linked list descriptors completed.
reserved
Next Descriptor Pointer
Software writes address first descriptor this register part system initialization sequence. When SG-DMA updates this register with location next descriptor fetched. stop execution SG-DMA core, software clears bit. When SG-DMA hardware will complete data transfers current descriptor then stop processing. Software then modify remaining linked-list restart SG-DMA hardware. While BUSY next descriptor pointer updated hardware. next descriptor pointer only reliably read software when BUSY
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Descriptors
descriptors specify information required perform data transfers, including: source address, destination address number bytes transferred. descriptors stored table which written software. This table stored FPGA memory external memory device linked list. descriptors aligned 32-bit boundary. Table shows layout descriptor entry.
Table 5-9. Descriptor Layout Field Names Offset
base base base base base base base base
SOURCE RESERVED DESTINATION RESERVED NEXT_DESC_PTR RESERVED WRITE_SIZE DESC_CONTROL READ_SIZE DESC_STATUS BYTES_TO_TRANSFER ACTUAL_BYTES_TRANSFERRED
Table 5-10 describes function various fields.
Table 5-10. Descriptor Field Descriptions (Part Field Name
SOURCE
Rd/Wr/Clr
Description
Specifies address data read. This address input source Avalon Streaming (Avalon-ST) interface. Specifies address which data should written. This address write data Avalon-ST interface. Specifies next descriptor linked list. Specifies number bytes transfer. BYTES_TO _TRANSFER transaction will terminated EOP. Specifies read size bytes read from Avalon devices (memory). Specifies write size bytes write Avalon Devices (memory).
DESTINATION
NEXT_DESC_PTR BYTES_TO_ TRANSFER READ_SIZE WRITE_SIZE
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Table 5-10. Descriptor Field Descriptions (Part Field Name
ACTUAL_BYTES_ TRANSFERRED DESC_CONTROL DESC_STATUS
Rd/Wr/Clr
Description
Specifies number bytes that successfully transferred hardware. Table 5-12 description each bit. Table 5-11 description each bit.
descriptor processor reads DESC_CONTROL fields determine proceed with transaction. Table 5-11 provides bit-map theses fields.
Table 5-11. Desc_Control Field Bits
Field Name
Generate_EOP Read_Fixed_Address
Rd/Wr/Clr
Description
When set, Read should generate final word. Avalon-MM ports, when Read does increment memory address. When read address increments after each read. When used Memory-to-Stream mode, read engine generates startofpacket signal first word.
Write_Fixed_Address
Used only Avalon-MM ports. When Write does increment memory address. When write address increments after each write. Read drives this value onto Avalon-ST channel port each word transaction. Write replaces this value with Avalon-ST channel number sink port. This determines whether hardware software write access descriptor SG-DMA control status register. When OWNED_BY_HW=1 hardware update this pointer. When OWNED_BY_HW=0, software update this pointer.
Avalon-ST_Channel_Number
Owned_by_HW
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After completing transaction, descriptor processor updates DESC_STATUS fields indicate transaction proceeded. error conditions these fields record only occur Avalon-ST interface. Table 5-12 provides bit-map DESC_STATUS fields.
Table 5-12. Descriptor Desc_Status
Name
E_CRC E_PARITY E_OVERFLOW E_SYNC E_UEOP E_MEOP E_MSOP Terminated_by_
Rd/Wr/Clr
Description
When set, indicates that error occurred Avalon-ST interface When set, indicates that parity error occurred Avalon-ST interface When set, indicates that overflow occurred Avalon-ST interface When set, indicates that out-of-sync error occurred Avalon-ST interface When set, indicates that unexpected error occurred Avalon-ST interface When set, indicates that missing error occurred Avalon-ST interface When set, indicates that missing error occurred Avalon-ST interface When set, indicates that write transaction terminated
Macros access registers defined altera_avalon_sgdma_regs.h. example, this file includes macros access status register, including following macros:
#define #define #define #define #define #define #define IOADDR_ _IO_CALC_ADDRESS_DYNAMIC(base, IORD(base, data) IOWR(base, data) (0x1) (0x2)
complete list predefined macros utilities access SG-DMA Controller hardware, see:
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Timeouts
SG-DMA controller does implement internal counters detect stalls. Software instantiate timer component this functionality required.
SG-DMA Controller
This section describes application programming interface (API) SG-DMA controller core.
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Prototype: Thread-safe: Available from ISR: Include: Parameters:
*dev, alt_sgdma_descriptor *desc)
Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
*dev-a pointer SG-DMA device structure. *desc-a pointer single, constructed descriptor. descriptor must have "next"
descriptor field initialized either non-ready descriptor, next descriptor chain.
Returns: Description:
Returns success. Other return codes defined errno.h. begin non-blocking transfer more descriptors descriptor chain. SG-DMA controller busy time this call, routine will immediately return -EBUSY; application then decide proceed without being blocked. callback routine been previously registered with this particular SG-DMA controller, transfer will issue interrupt error, EOP, chain completion. Otherwise, interrupt registered responsibility application developer check handle errors completion.
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Prototype: Thread-safe: Available from ISR: Include: Parameters:
alt_u8 *dev, alt_sgdma_descriptor *desc)
recommended. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
*dev-a pointer SG-DMA device structure. *desc-a pointer single, constructed descriptor. descriptor must have "next"
descriptor field initialized either non-ready descriptor, next descriptor chain.
Returns: Description:
Returns contents status register. Sends fully formed descriptor list descriptors SG-DMA controller transfer. This function blocks both before transfer, SG-DMA controller busy, until requested transfer completed. error detected during transfer, abandoned controller's status register contents returned caller. Additional error information available status bits each descriptor that SG-DMA processed. responsibility user application search through descriptor list descriptors gather specific error information.
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Prototype:
void *desc, alt_sgdma_descriptor *next, alt_u32 *read_addr, alt_u32 *write_addr, alt_u16 length, read_fixed, write_fixed)
Yes. Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
Thread-safe: Available from ISR: Include: Parameters:
*desc-a pointer descriptor being constructed. *next-a pointer "next" descriptor. This does need complete
functional descriptor, must properly allocated. *read_addr-the first read address SG-DMA transfer. *write_addr-the first write address SG-DMA transfer. length-the number bytes transfer. read_fixed-if non-zero, SG-DMA will read from fixed address. write_fixed-if non-zero, SG-DMA will write fixed address.
Returns: Description:
void
This function constructs single SG-DMA descriptor memory specified alt_avalon_sgdma_descriptor *desc Avalon-MM Avalon-MM transfer. function sets OWNED_BY_HW descriptor's control field, marking completed descriptor ready run. descriptor processed when SG-DMA controller receives descriptor SG-DMA control register asserted. next field descriptor being constructed address *next. OWNED_BY_HW descriptor *next explicitly cleared. Once SG-DMA completes processing *desc, will process descriptor *next until OWNED_BY_HW set. create descriptor chain, repeatedly call this function using previous call's *next pointer *desc parameter. responsible properly allocating memory creation both descriptor under construction well next descriptor chain. Descriptors must memory device mastered SG-DMA controller's chain read chain write Avalon master ports. Care must taken ensure both *desc *next point areas memory mastered controller.
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Prototype:
void riptor *desc, alt_sgdma_descriptor *next, alt_u32 *write_addr, alt_u16 length_or_eop, write_fixed)
Yes. Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
Thread-safe: Available from ISR: Include: Parameters:
*desc-a pointer descriptor being constructed. *next-a pointer "next" descriptor. This does need complete
functional descriptor, must properly allocated. *write_addr-the first write address SG-DMA transfer. length_or_eop-the number bytes transfer. zero (0x0), transfer will continue until signal received from Avalon-ST interface. write_fixed-if non-zero, SG-DMA will write fixed address.
Returns: Description:
void This function constructs single SG-DMA descriptor memory specified alt_avalon_sgdma_descriptor *desc Avalon-ST Avalon-MM transfer. source (read) data transfer comes from Avalon-ST interface connected SG-DMA controller's streaming read port. function sets OWNED_BY_HW descriptor's control field, marking completed descriptor ready run. descriptor processed when SG-DMA controller receives descriptor SG-DMA control register asserted. next field descriptor being constructed address *next. OWNED_BY_HW descriptor *next explicitly cleared. Once SG-DMA completes processing *desc, will process descriptor *next until OWNED_BY_HW set. create descriptor chain, repeatedly call this function using previous call's *next pointer *desc parameter. responsible properly allocating memory creation both descriptor under construction well next descriptor chain. Descriptors must memory device mastered SG-DMA controller's chain read chain write Avalon master ports. Care must taken ensure both *desc *next point areas memory mastered controller.
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Prototype:
void riptor *desc, alt_sgdma_descriptor *next, alt_u32 *read_addr, alt_u16 length, read_fixed, generate_sop, generate_eop, alt_u8 atlantic_channel)
Yes. Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
Thread-safe: Available from ISR: Include: Parameters:
*desc-a pointer descriptor being constructed. *next-a pointer "next" descriptor. This does need complete
functional descriptor, must properly allocated. *read_addr-the first read address SG-DMA transfer. length-the number bytes transfer. read_fixed-if non-zero, SG-DMA will read from fixed address. generate_sop-if non-zero, SG-DMA will generate start-of-packet (SOP) Avalon Streaming interface when commencing transfer. generate_eop-if non-zero, SG-DMA will generate end-of-packet (EOP) Avalon Streaming interface when completing transfer. atlantic_channel-an 8-bit channel identification number that will passed Avalon-ST interface.
Returns: Description:
void
This function constructs single SG-DMA descriptor memory specified alt_avalon_sgdma-descriptor *desc Avalon-MM Avalon-ST transfer. destination (write) data transfer goes Avalon-ST interface connected SG-DMA controller's streaming write port. function sets OWNED_BY_HW descriptor's control field, marking completed descriptor ready run. descriptor processed when SG-DMA controller receives descriptor SG-DMA control register asserted. next field descriptor being constructed address *next. OWNED_BY_HW descriptor *next explicitly cleared. Once SG-DMA completes processing *desc, will process descriptor *next until OWNED_BY_HW set. create descriptor chain, repeatedly call this function using previous call's *next pointer *desc parameter. responsible properly allocating memory creation both descriptor under construction well next descriptor chain. Descriptors must memory device mastered SG-DMA controller's chain read chain write Avalon master ports. Care must taken ensure both *desc *next point areas memory mastered controller.
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Prototype:
*desc)
Yes. Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
Thread-safe: Available from ISR: Include: Parameters: Returns: Description:
*desc-a pointer constructed descriptor examine.
Returns descriptor error-free, owned hardware, previously requested transfer completed normally. Other return codes defined errno.h. Checks descriptor previously owned hardware errors reported previous transfer. routine reports: errors reported SG-DMA controller, buffer use.
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Prototype:
void *dev, alt_avalon_sgdma_callback callback, alt_u16 chain_control, void *context)
Yes. Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
Thread-safe: Available from ISR: Include: Parameters:
*dev-a pointer SG-DMA device structure. callback-a pointer callback routine execute interrupt level. chain_control-the SG-DMA control register contents. *context-a pointer used pass context-specific information ISR. context point ISR-specific information. void
Associates user-specific routine with SG-DMA interrupt handler. callback registered, non-blocking transfers will enable interrupts that will cause callback executed. callback runs part interrupt service routine, great care must taken follow guidelines acceptable interrupt service routine behavior described Nios Software Developer's Handbook. disable callbacks after registering one, call this routine with callback argument.
Returns: Description:
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alt_avalon_sgdma_start()
Prototype: Thread-safe: Available from ISR: Include: Parameters: Returns: Description:
void *dev)
Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
*dev-a pointer SG-DMA device structure. void
Starts engine process descriptor pointed controller's next descriptor pointer subsequent descriptors chain.
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alt_avalon_sgdma_stop()
alt_avalon_sgdma_stop()
Prototype: Thread-safe: Available from ISR: Include: Parameters: Returns: Description:
void *dev)
Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
*dev-a pointer SG-DMA device structure. void
Stops engine following completion current buffer descriptor.
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alt_avalon_sgdma_open()
Prototype: Thread-safe: Available from ISR: Include: Parameters: Returns: Description:
alt_sgdma_dev* alt_avalon_sgdma_open(const char* name)
Yes. <altera_avalon_sgdma.h>, <altera_avalon_sgdma_regs.h>
name-the name SG-DMA device open.
pointer SG-DMA device structure associated with supplied name, NULL corresponding SG-DMA device structure found.
Retrieves pointer hardware SG-DMA device structure.
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Altera Corporation 2007
alt_avalon_sgdma_stop()
Document Revision History
Table 5-13 shows revision history this chapter.
Table 5-13. Document Revision History Date Document Version
2007 v7.1.0 Initial release.
Changes Made
Summary Changes
Altera Corporation 2007
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Quartus Handbook, Volume
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Altera Corporation 2007

QII55003-7.1.0 Core Overview Scatter-Gather direct memory ac

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