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Mentor Graphics ModelSim Support
QII53001-7.1.0
Altera® software subscription includes license ModelSim-Altera software UNIX platform. ModelSim-Altera software used perform functional register transfer level (RTL), post-synthesis, gate-level timing simulations either Verilog VHDL designs that target Altera FPGA. This chapter provides detailed instructions simulate your design ModelSim-Altera version Mentor Graphics® ModelSim® software version. This chapter gives details specific libraries that needed functional simulation gate-level timing simulation. This document describes using ModelSim-Altera software version 6.1g Mentor Graphics ModelSim software version 6.1g. also contains references features available Altera Quartus® software version 7.1. following topics discussed this chapter:
"Background" "Software Compatibility" page "Altera Design Flow with ModelSim ModelSim-Altera Software" page "Functional Simulation" page "Post-Synthesis Simulation" page 2-16 "Gate-Level Timing Simulation" page 2-23 "Simulating Designs that Include Transceivers" page 2-37 "Using NativeLink Feature with ModelSim" page 2-44 "Scripting Support" page 2-50 "Software Licensing Licensing Set-Up" page 2-51
more information about current Quartus software version, refer Altera website www.altera.com. ModelSim-Altera software version 6.1g included with your Altera software subscription licensed Solaris, Linux platforms support either Verilog VHDL hardware description language (HDL) simulation. ModelSim-Altera software supports VHDL Verilog functional RTL, post-synthesis, gate-level timing simulations Altera devices.
Background
Altera Corporation 2007
Preliminary
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Table describes differences between Mentor Graphics ModelSim SE/PE ModelSim-Altera software versions.
Table 2-1. Comparison ModelSim Software Versions Product Feature
100% VHDL, Verilog, mixed-HDL support Complete debugging environment Optimized direct compile architecture Industry-standard scripting Flexible licensing Verilog support. Interfaces Verilog designs customer code third-party software VHDL support. Interfaces VHDL designs customer code third-party software Standard Delay Format File annotation Advanced debugging features language-neutral licensing Customizable, userexpandable graphical user interface integrated simulation performance analyzer Integrated code coverage analysis SWIFT support Accelerated VITAL Verilog primitives times faster), register transfer level (RTL) acceleration times faster) Platform support Precompiled Libraries Note Table 2-1:
ModelSim-Altera will only allow annotation modules Altera library.
ModelSim
Optional
ModelSim
Optional
ModelSim-Altera
Supports only single-HDL simulation
ModelSim-Altera Edition
Supports only single-HDL simulation
Optional
v(1)
UNIX, Linux
only
UNIX, Linux
only
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Software Compatibility
Software Compatibility
Table shows which ModelSim-Altera software version compatible with Quartus software versions. ModelSim versions provided directly from Mentor Graphics correspond specific Quartus software versions. help with ModelSim-Altera licensing refer "Software Licensing Licensing Set-Up" page 2-51.
Table 2-2. Compatibility Between Software Versions ModelSim-Altera Software
ModelSim-Altera software version 6.1g ModelSim-Altera software version 6.1d ModelSim-Altera software version 6.0e ModelSim-Altera software version 6.0c ModelSim-Altera software version 5.8.e ModelSim-Altera software version Note Table 2-2:
Updated ModelSim-Altera precompiled libraries available download Altera's website each release Quartus service pack.
Quartus Software
Quartus software version 6.1, 7.0, Quartus software version Quartus software version Quartus software version Quartus software version
Altera Design Flow with ModelSim ModelSimAltera Software
This chapter contains following sections:
Functional simulations Post-synthesis simulations Gate-level timing simulations Using NativeLink® feature with ModelSim
Figure illustrates Altera design flow using Mentor Graphics ModelSim software ModelSim-Altera software.
Altera Corporation 2007
Preliminary
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Figure 2-1. Altera Design Flow with ModelSim-Altera Quartus Software
ALTERA Design Entry
Testbench
.v/.vhd
Functional Simulation
Synthesis
Functional Simulation Library Files
Verilog Output File VHDL Output File
.vo/.vho
Post-Synthesis Simulation
Place-and-Route
Post-Synthesis Simulation Library Files
Verilog Output File VHDL Output File
.vo/.vho
.sdo
Standard Delay Format Output File
Gate-Level Timing Simulation
Gate-Level Simulation Library Files
Note Figure 2-1:
performing functional simulation through NativeLink, must complete analysis elaboration first.
Preliminary
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Functional Simulation
Functional Simulation
functional simulation performed before gate-level simulation post-synthesis simulation. Functional simulation verifies functionality design before synthesis place-and-route. This section provides detailed instructions perform functional simulation ModelSim-Altera software highlights some differences performing similar steps Mentor Graphics ModelSim software versions Verilog VHDL designs.
Functional Simulation Libraries
Pre-compiled libraries available functional simulation with ModelSim-Altera software. These libraries include library altera_mf library. create these libraries simulation with ModelSim SE/PE software, compile library files described following sections.
Simulation Models
simulate designs containing functions, following functional simulation models:
220model.v (for Verilog HDL) 220pack.vhd 220model.vhd (for VHDL) When simulating design that uses VHDL-1987, 220model_87.vhd model file.
Table shows location these simulation model files precompiled libraries Quartus software ModelSim-Altera software.
Table 2-3. Location Simulation Models Files Pre-Compiled Libraries Software
Quartus ModelSim-Altera Notes Table 2-3:
ModelSim SE/PE, compile files provided with Quartus software. ModelSim-Altera, precompiled libraries simulation. <HDL> either Verilog VHDL.
Location
<Quartus installation directory>\eda\sim_lib\ <ModelSim-Altera installation (2),
more information about functions, refer Quartus Help.
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Altera Megafunction Simulation Models
simulate design that contains Altera megafunctions, following simulation models:
altera_mf.v (for Verilog HDL) altera_mf.vhd altera_mf_components.vhd (for VHDL) When simulating design that uses VHDL-1987, altera_mf_87.vhd.
Table shows location these simulation files precompiled libraries Quartus software ModelSim-Altera software.
Table 2-4. Location Altera Megafunction Simulation Models Files Precompiled Libraries Software
Quartus ModelSim-Altera Notes Table 2-4:
ModelSim SE/PE, compile files provided with Quartus software. ModelSim-Altera, precompiled libraries simulation. <HDL> either Verilog VHDL.
Location
<Quartus installation directory>\eda\sim_lib\ <ModelSim-Altera installation (2),
following Altera megafunctions require device atom libraries perform functional simulation third-party simulator:
altclkbuf altclkctrl altdqs altdq altddio_in altddio_out altddio_bidir altufm_none altufm_parallel altufm_spi altmemmult altremote_update
device atom library files located following directory: <Quartus installation directory>/eda/sim_lib
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Functional Simulation
Low-Level Primitive Simulation Models
simulate design that contains low-level Altera primitives with following simulation models:
altera_primitives.v (for Verilog HDL) altera_primitives.vhd (for VHDL)
Table shows location these simulation library files precompiled libraries Quartus software ModelSim-Altera software.
Table 2-5. Location Altera Primitives Model Files Precompiled Libraries Software
Quartus ModelSim-Altera Notes Table 2-5:
ModelSim SE/PE, compile files provided with Quartus software. ModelSim-Altera, precompiled libraries simulation. <HDL> either Verilog VHDL.
Location
<Quartus installation directory>\eda\sim_lib <ModelSim-Altera installation directory>\altera\<HDL>\altera (2),
Simulating VHDL Designs
following instructions perform functional simulation VHDL designs ModelSim software. steps following section assume have already created ModelSim project. ModelSim-Altera software comes with precompiled simulation libraries. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-9.
Create Simulation Libraries
Simulation libraries required simulate design that contains Altera primitive, function, Altera megafunction. These libraries have already been compiled using ModelSim-Altera software. However, using Mentor Graphics ModelSim software version, must create simulation libraries link them your design correctly.
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Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: ModelSim software, File menu, point click Library. Create Library dialog appears. Select library logical mapping Library Name box, type name newly created library. example, library name Altera megafunctions should altera_mf, library name should lpm. Click
Create Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vlib vmap vlib vmap vlib vmap altera_mf altera_mf altera_mf altera altera altera
Compile Simulation Models into Simulation Libraries
following steps required ModelSim-Altera software. Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, point Project click Existing File. Browse <Quartus installation directory>/eda/sim_lib necessary simulation model files your project. altera_mf.vhd model file should compiled into altera_mf library. 220pack.vhd 220model.vhd model files should compiled into library. Workspace window, select simulation model file, View menu, click Properties.
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Functional Simulation
Choose correct library from Compile Library list. Click Compile menu, click Compile selected.
Compile Simulation Models into Simulation Libraries ModelSim Command Prompt Type following commands ModelSim command prompt:
vcom vcom vcom vcom vcom vcom -work -work -work -work -work -work altera_mf <Quartus installation altera_mf <Quartus installation <Quartus installation <Quartus installation altera <Quartus installation altera <Quartus installation
Compile Testbench Design Files into Work Library
Compile testbench design files into work library clicking Compile clicking Compile toolbar icon Compile menu. Compile Testbench Design Files into Work Library Using ModelSim Command Prompt Type following command ModelSim command prompt: vcom -work work <my_test bench.vhd> <my_design_files.vhd>r Resolve compile-time errors before proceeding following section.
Loading Design
load design, perform following steps: Simulate menu, click Start Simulation. Start Simulation dialog appears. Expand work library Start Simulation dialog box. Select top-level design unit (your testbench). Resolution list, select Click
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Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim work.<my_test bench>
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays objects current scope. View menu, point Debug Windows click Wave. Drag signals monitor from Objects window drop them into Wave window. Type following command ModelSim command prompt: <time period> Running Simulation Using ModelSim Command Prompt Type following commands ModelSim command prompt: wave /<signal name> <time period>
Simulating Verilog Designs
following instructions provide step-by-step instructions perform functional simulation Verilog designs ModelSim software. following steps assume have already created ModelSim project. using ModelSim-Altera software, precompiled libraries created when install software. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-12.
Create Simulation Libraries
Simulation libraries needed properly simulate design that contains function Altera megafunction. These libraries have already been compiled using ModelSim-Altera software.
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Functional Simulation
However, using Mentor Graphics ModelSim software version, must create simulation libraries correctly link them your design. Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: File menu, point click Library. Create Library dialog appears. Select library logical mapping Library Name box, type name newly created library. example, library name Altera megafunctions should altera_mf, library name should lpm. Click
Create Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vlib vmap vlib vmap vlib vmap altera_mf altera_mf altera_mf altera altera altera
Compile Simulation Models into Simulation Libraries
following steps required ModelSim-Altera software. Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, point Project click Existing File. Browse <Quartus installation directory>/eda/sim_lib necessary simulation model files your project. Compile altera_mf.v into altera_mf library. Compile 220model.v into library.
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Select simulation model file View menu, click Properties. Choose correct library from Compile Library list. Click Compile menu, click Compile selected.
Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt:
vlog -work altera_mf <Quartus installation vlog -work <Quartus installation vlog -work altera <Quartus installation
Compile Testbench Design Files into Work Library
Compile testbench design files into work library Compile menu clicking Compile clicking Compile toolbar icon Compile menu. Compile Testbench Design Files into Work Library Using ModelSim Command Prompt Type following command ModelSim command prompt: vlog -work work <my_test bench.v> <my_design_files.v>r Resolve compile-time errors before proceeding following section.
Loading Design
Perform following steps load design: Simulate menu, click Start Simulation. Start Simulation dialog appears. Click Libraries tab. Search Libraries box, click Add. Specify location altera_mf simulation libraries.
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Functional Simulation
using ModelSim-Altera version, refer Table page Table page location precompiled simulation libraries. using Mentor Graphics ModelSim software version, browse library that created earlier. Load Design dialog box, click Design expand work library. Select top-level design unit (your testbench). Resolution list, select Click
Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim altera_mf work.<my_test bench>
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays objects current scope. View menu, point Debug Windows click Wave. Drag signals monitor from Objects window drop them into Wave window. Type following command ModelSim command prompt: <time period> Running Simulation Using ModelSim Command Prompt Type following commands ModelSim command prompt: wave /<signal name> <time period>
Verilog Functional Simulation with Altera Memory Blocks
Both ModelSim software products support simulating Altera memory megafunctions initialized with Hexadecimal (Intel-Format) File (.hex) initialization files (.rif).
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Although synthesis able read Memory Initialization File (.mif), this memory file supported with third-party tools must converted either Hexadecimal (Intel-Format) File Initialization File. Table summarizes different types memory initialization file formats that supported with each language.
Table 2-6. Simulation Support Memory Initialization Files File
Hexadecimal (Intel-Format) File Memory Initialization File Initialization File Notes Table 2-6:
memories library files from Quartus software version earlier, must library containing convert_hex2ver function. Requires USE_RIF macro defined, described later this section.
Verilog
VHDL
simulate your design converting your Memory Initialization File into either Hexadecimal (Intel-Format) File Initialization File, perform following steps: Convert Memory Initialization File Hexadecimal (Intel-Format) File Initialization File Quartus software. Converting Memory Initialization File Hexadecimal (Intel-Format) File Open Memory Initialization File. File menu, click Save Save dialog appears. Save type list, select Hexadecimal (Intel-Format) File (*.hex). Click
Convert Memory Initialization File Initialization File Open Memory Initialization File File menu, click Export. Export dialog appears. Save type list, select Initialization File (*.rif).
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Functional Simulation
Click
Alternatively, convert Memory Initialization File Initialization File using mif2rif.exe utility located <Quartus installation>/bin directory. mif2rif <mif_file> <rif_file> Modify file generated MegaWizard® Plug-In Manager. Altera memory custom megafunction variation file includes lpm_file parameter memories such LPM_ROM, init_file Altera specific memories such altsyncram, point initialization file. text editor, open custom megafunction variation file edit lpm_file init_file point Hexadecimal (Intel-Format) File Initialization File, shown following example: lpm_ram_dp_component.lpm_file "<path HEX/RIF>" Compile functional library files with compiler directives. Hexadecimal (Intel-Format) File, compiler directives required. Initialization File, must define USE_RIF macro when compiling model library files. example, should enter following when compiling altera_mf library when Initialization File memory initialization files used: vlog -work altera_mf altera_mf.v +define+USE_RIF=1 Quartus software versions earlier, must define NO_PLI macro instead USE_RIF. NO_PLI macro forward compatible with Quartus software.
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Post-Synthesis Simulation
post-synthesis simulation verifies functionality design after synthesis been performed. create post-synthesis netlist Quartus software this netlist perform post-synthesis simulation ModelSim. Once post-synthesis version design verified, next step place-and-route design target device using Quartus Fitter.
Generating Post-Synthesis Simulation Netlist
following steps describe process generating post-synthesis simulation netlist Quartus software: Perform Analysis Synthesis. Processing menu, point Start click Start Analysis Synthesis (you also perform this after step Turn Generate Netlist Functional Simulation Only option performing following steps: Assignments menu, click Tool Settings. Settings dialog appears. Category list, select Simulation. Simulation page appears. Tool name list: using ModelSim-Altera software, select ModelSim-Altera. using Mentor Graphics ModelSim software, select ModelSim.
Under Netlist Writer options, Format output netlist list, select VHDL Verilog. also modify where want post-synthesis netlist generated editing browsing directory Output directory box. Click More Settings. More Tools Simulation Settings dialog appears. Existing options settings list, click Generate Netlist Functional Simulation Only select from Setting list under Option. Click Settings dialog box, click
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Post-Synthesis Simulation
Netlist Writer. Processing menu, point Start click Start Netlist Writer. During Netlist Writer stage, Quartus software produces Verilog Output File (.vo) VHDL Output File (.vho) that used post-synthesis simulations ModelSim software. This netlist file mapped architecture-specific primitives. timing information included this stage. resulting netlist located output directory specified Settings dialog box, which defaults <project directory>/simulation/modelsim directory.
Simulating VHDL Designs
following instructions help perform post-synthesis simulation VHDL design ModelSim software. following steps assume have already created ModelSim project. using ModelSim-Altera software, precompiled libraries created when install software. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-9.
Create Simulation Libraries
Simulation libraries required simulate design that mapped post-synthesis primitives. using Mentor Graphics ModelSim software version, must create simulation libraries correctly link them your design. This process required with ModelSim-Altera version because pre-compiled libraries installed with software.
Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: File menu, click Library. Create Library dialog appears. Select Library logical linking Library Name box, type name newly created library.
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Click
Create Simulation Libraries Using ModelSim Command Prompt Type following commands create simulation libraries: vlib <device family name> vmap <device family name> <device family name> more information about library names, refer Table page 2-28. Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, point Project click Existing File. Browse <Quartus installation directory>/eda/sim_lib directory necessary gate-level simulation files your project. Select simulation model file View menu, click Properties. Compile Library list, select correct library. Click Compile menu, click Compile selected.
Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vcom -work <device family name> <Quartus installation directory> /eda/sim_lib/<device family name>_atoms.vhd vcom -work <device family name> <Quartus installation directory> /eda/sim_lib/<device family name>_components.vhd
Compile Testbench VHDL Output File into Work Library
compile testbench VHDL Output Files into work library, Compile menu, click Compile click Compile toolbar icon Compile menu.
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Post-Synthesis Simulation
Compile Testbench VHDL Output File into Work Library Using ModelSim Command Prompt Type following command ModelSim command prompt: vcom -work work <my_test bench.vhd> <my_vhdl_output_file.vho>r Resolve compilation errors before proceeding following section.
Loading Design
Perform following steps load design: Simulate menu, click Simulate. Click Design tab. Library list, select work library. Simulate dialog box, expand work library select top-level design unit (your testbench). Click
Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim work.<my test bench> 1psr time scale resolution when simulating Altera FPGA designs.
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays objects current scope. View menu, point Debug Windows click Wave. Drag signals monitor from Objects window drop them into Wave window. Type following command ModelSim command prompt: <time period>
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Running Simulation Using ModelSim Command Prompt Type following commands ModelSim command prompt: wave /<signal name> <time period>
Simulating Verilog Designs
following sections provide step-by-step instructions performing post-synthesis simulation Verilog designs ModelSim software.
Create Simulation Libraries
following steps assume have already created ModelSim project. using ModelSim-Altera software, precompiled libraries created when install software. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-9.
Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: ModelSim software, File menu, point click Library. Create Library dialog appears. Select library logical mapping name libraries should altera_mf (for Altera megafunctions) (for MegaWizard Plug-in Manager-generated entities). Library Name box, type name newly created library. Click
Create Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vlib <device family name> vmap <device family name> <device family name> more information about library names, refer Table page 2-28.
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Post-Synthesis Simulation
Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, click Project, then select Existing File. Browse <Quartus installation directory>/eda/sim_lib directory necessary simulation model files your project. Select simulation model file View menu, click Properties. Specify correct library Compile Library box.
Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt Type following command ModelSim command prompt: vlog -work <device family name> <Quartus installation directory> /eda/sim_lib/<device family name>_atoms.v
Compile Testbench Verilog Output File into Work Library
compile testbench Verilog Output Files into work library, Compile menu, click Compile click Compile toolbar icon Compile menu. Compile Testbench Verilog Output File into Work Library Using ModelSim Command Prompt Type following command ModelSim command prompt: vlog -work work <my_test bench.v> <my_verilog_output_file.vo> Resolve compilation errors before proceeding following section.
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Loading Design
Perform following steps load design: Simulate menu, click Start Simulation. Start Simulation dialog appears. Click Libraries tab. Search Libraries box, click Add. Specify location device family simulation libraries. Load Design dialog box, click Design expand work library. Select top-level design unit (your testbench). Resolution list, select Click
Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim <gate-level simulation library> work.<my_test bench> time scale resolution when simulating Altera FPGA designs.
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays objects current scope. View menu, point Debug Windows click Wave. Drag signals monitor from Objects window drop them into Wave window. Type following command ModelSim command prompt: <time period>
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Gate-Level Timing Simulation
Running Simulation Using ModelSim Command Prompt Type following commands ModelSim command prompt: wave /<signal name> <time period>
Gate-Level Timing Simulation
Gate-level timing simulation post place-and-route simulation verify operation design after worst-case timing delays have been calculated. This section provides detailed instructions perform gate-level timing simulation ModelSim-Altera software highlights differences performing similar steps Mentor Graphics ModelSim software versions VHDL Verilog designs.
Generating Gate-Level Timing Simulation Netlist
perform gate-level timing simulation, ModelSim-Altera software requires information about design placed into device-specific architectural blocks. Quartus software provides this information form Verilog Output File Verilog designs VHDL Output File VHDL designs. accompanying timing information stored Standard Delay Format Output File (.sdo), which annotates delay elements found Verilog Output File VHDL Output File. following steps describe process generating gate-level timing simulation netlist Quartus software: Perform full compilation. Processing menu, click Start Compilation. Assignments menu, click Tool Settings. Settings dialog appears. Category list, click icon expand Tool Settings select Simulation. Simulation page appears. Tool name list:
using ModelSim-Altera software, select ModelSim-Altera. using Mentor Graphics ModelSim software, select ModelSim.
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Under Netlist Writer options, Format output netlist list, select VHDL Verilog. also modify where want post-synthesis netlist generated editing browsing directory Output directory box. Click Settings dialog box, click Netlist Writer. Processing menu, point Start click Start Netlist Writer. During Netlist Writer stage, Quartus software produces Verilog Output File (.vo), VHDL Output File (.vho), used gate-level timing simulations ModelSim software. This netlist file mapped architecture-specific primitives. timing information netlist included SDO. resulting netlist located output directory specified Settings dialog box, which defaults <project directory>/simulation/modelsim directory.
Generating Different Timing Model
enable Quartus Classic Quartus TimeQuest Timing Analyzer when generating file, slow-corner (worst case) timing models used default. generate file using different timing model, must Quartus Classic Quartus TimeQuest Timing Analyzer with different timing model before start Netlist writer. Quartus Classic Timing Analyzer with best-case model, Processing menu, point Start click Start Classic Timing Analyzer (Fast Timing Model). After timing analysis complete, Compilation Report appears. also type following command command prompt: quartus_tan <project_name> -fast_model=on Quartus TimeQuest Timing Analyzer with best-case model, -fast_model option after create timing netlist. following command enables fast timing models: create_timing_netlist -fast_model also type following command command prompt: quartus_sta <project_name> -fast_model=on
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Gate-Level Timing Simulation
more information about generating timing model, refer Quartus Classic Timing Analyzer Quartus TimeQuest Timing Analyzer chapter volume Quartus Handbook. After Classic TimeQuest Timing Analyzer, perform steps through "Generating Gate-Level Timing Simulation Netlist" page 2-23 generate file. fast corner timing models, _fast post added VHO, file (for example, my_project_fast.vo, my_project_fast.vho, my_project_fast.sdo). Operating Condition Example: Generate Timing Models Stratix Devices Stratix Cyclone devices, specify different temperature voltage parameters generate timing models. Table shows available operation conditions (model, voltage, temperature) Stratix Cyclone devices.
Table 2-7. Available Operating Condition Stratix Cyclone Devices Device Family
Stratix
Model
Slow Slow Fast
Voltage
1100 1100 1100 1200 1200 1200
Temperature
Cyclone
Slow Slow Fast
generate files three different operating conditions Stratix design, perform following steps: Generate first slow corner model operating conditions: slow, 1100 Type following command command prompt:
quartus_sta <project name> -model=slow -voltage=1100 -temperature=85 Generate fast corner model operating conditions: fast, 1100 Type following command command prompt:
quartus_sta <project name> -model=fast -voltage=1100 -temperature=0
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Generate ModelSim simulation output files corners specified above. output files generated modelsim_two_corner_files directory. Type following command command prompt:
quartus_eda <project name> -simulation -tool=modelsim -format=verilog Generate second slow corner model operating conditions: slow, 1100 Type following command command prompt:
quartus_sta <project name> -model=slow -voltage=1100 -temperature=0 generate ModelSim simulation output files second slow corner. output files generated modelsim_one_slow_corner_files directory.
quartus_eda <project name> -simulation -tool=modelsim -format=verilog summarize, steps above generate following files three operating conditions: First slow corner (slow, 1100 file- name>.vo file- name>_v.sdo Fast corner (fast, 1100 file- name>.vo file- name>_v_fast.sdo Second slow corner (slow, 1100 file- name>.vo file- name>_v.sdo modelsim_one_slow_corner_files directory also have files fast corner. These files ignored since they were already generated modelsim_two_corner_files directory.
Perform Timing Simulation Using Post-synthesis Netlist
Instead using gate-level netlist, also perform timing simulation with post-synthesis netlist. generate without running fitter. this case, file includes timing values only device cells. Interconnect delays included because fitting (placement routing) been performed.
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Gate-Level Timing Simulation
generate post-synthesis netlist file, type following command command prompt: quartus_map <project name> <revision name> quartus_tan <project name> <revision name> -post_map -zero_ic_delays quartus_eda <project name> <revision name> -simulation -tool=<3rd party tool> -format=<HDL language> more information -format -tool options, type following command command prompt: quartus_eda -help=<options>
Gate-Level Simulation Libraries
Table provides description ModelSim-Altera precompiled device libraries.
Table 2-8. ModelSim-Altera Precompiled Device Libraries (Part Library
arriagx_hssi Arria®
Description
Precompiled library device designs using Gigabit Transceiver Block (alt2gxb megafunction). This precompiled library required both functional timing simulations. Precompiled library Stratix® device designs. Precompiled library Stratix device designs. Precompiled library Stratix device designs. Precompiled library Stratix device designs using Gigabit Transceiver Block (alt2gxb megafunction). This precompiled library required both functional timing simulations. Precompiled library Stratix device designs. Precompiled library Stratix device designs. Precompiled library Stratix device designs using Gigabit Transceiver Block. This precompiled library should used post-fit (timing) simulations. Precompiled library Stratix device designs that include altgxb megafunction. This precompiled library should used functional simulations. Precompiled library Cyclone® device designs. Precompiled library Cyclone device designs. Precompiled library MAX® device designs. Precompiled library 7000 3000 device designs. Precompiled library APEXII device designs. Precompiled library APEX device designs.
stratixiii stratixii stratixiigx stratixiigx_hssi
stratix stratixgx stratixgx_gxb altgxb cycloneii cyclone maxii apexii apex20k
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Table 2-8. ModelSim-Altera Precompiled Device Libraries (Part Library
apex20ke mercury flex10ke flex6000
Description
Precompiled library APEX 20KC, APEX 20KE, Excaliburdevice designs. Precompiled library Mercurydevice designs. Precompiled library FLEX® 10KE ACEX® device designs. Precompiled library FLEX 6000 device designs.
Table shows location timing simulation libraries ModelSim-Altera software Verilog HDL.
Table 2-9. Location Timing Simulation Libraries ModelSim-Altera Verilog Library
arriagx_ver arriagx_hssi_ver stratixii_ver stratixiigx_ver stratixiigx_hssi_ver stratixiii_ver stratix_ver stratixgx_ver stratixgx_gxb_ cycloneiii_ver cycloneii_ver cyclone_ver maxii_ver max_ver apexii_ver apex20k_ver apex20ke_ver mercury_ver flex10ke_ver flex6000_ver Note Table 2-9:
stratixiigx_hssi precompiled library required functional timing simulations.
Verilog
<ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation directory>\altera\verilog\max\ <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation
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Table 2-10 shows location timing simulation libraries ModelSim-Altera software VHDL.
Table 2-10. Location Timing Simulation Library Files ModelSim-Altera VHDL Library
arriagx arriagx_hssi stratixii stratixiigx stratixiigx_hssi stratixiii stratix stratixgx stratixgx_gxb cycloneiii cycloneii cyclone maxii apexii apex20ke apex20k flex10ke flex6000 mercury Note Table 2-10:
stratixiigx_hssi precompiled library required functional timing simulations.
VHDL
<ModelSim-Altera installation directory>\altera\vhdl\arriagx\ <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation directory>\altera\vhdl\stratix\ <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation directory>\altera\vhdl\cyclone\ <ModelSim-Altera installation directory>\altera\vhdl\maxii\ <ModelSim-Altera installation directory>\altera\vhdl\max\ <ModelSim-Altera installation directory>\altera\vhdl\apexii\ <ModelSim-Altera installation <ModelSim-Altera installation directory>\altera\vhdl\apex20k\ <ModelSim-Altera installation <ModelSim-Altera installation <ModelSim-Altera installation directory>\altera\vhdl\mercury\
using Mentor Graphics ModelSim software version your timing simulation, libraries available Quartus software <Quartus installation directory>\eda\sim_lib\ directory. Mentor Graphics ModelSim software users must files provided with Quartus software.
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Simulating VHDL Designs
following section provides step-by-step instructions performing gate-level timing simulation VHDL designs. following steps assume have already created ModelSim project. additional information, refer "Altera Design Flow with ModelSim ModelSimAltera Software" page 2-3. using ModelSim-Altera software, precompiled libraries created when install software. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-9.
Create Simulation Libraries
using Mentor Graphics ModelSim software version, create gate-level simulation libraries correctly link them your design. Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: ModelSim software, File menu, point click Library. Create Library dialog appears. Select library logical mapping
name libraries should altera_mf (for Altera megafunctions) (for MegaWizard Plug-In Manager-generated entities).
Library Name box, type name newly created library. library name must those listed Table 2-10 page 2-29. Click
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Create Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vlib <device family name> vmap <device family name> <device family name> more information about library names, refer Table page 2-28. Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, point Project click Existing File. Browse <Quartus installation directory>/eda/sim_lib directory, necessary gate-level simulation files your project. Select simulation model file, View menu, click Properties. Compile Library list, select correct library. Click Compile menu, click Compile selected.
Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vcom -work <device family name> <Quartus installation directory> /eda/sim_lib/<device family name>_atoms.vhd vcom -work <device family name> <Quartus installation directory> /eda/sim_lib/<device family name>_components.vhd
Compile Testbench VHDL Output File into Work Library
Compile testbench VHDL Output Files into work library Compile menu clicking Compile clicking Compile toolbar icon Compile menu.
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Compile Testbench VHDL Output File into Work Library Using ModelSim Command Prompt Type following command ModelSim command prompt: vcom -work work <my_test bench.vhd> <my_vhdl_output_file.vho> Resolve compilation errors before proceeding following section.
Loading Design
Perform following steps load design: Simulate menu, click Start Simulation. Click tab, click Add. Entry dialog box, click Browse select Standard Delay Format Output File (.sdo). Apply Region dialog box, type instance path which should applied. example, using testbench exported into Quartus software from Vector Waveform File, instance path should /i1.
have choose from Delay list because Quartus Netlist Writer generates using same value triplet (minimum, typical, maximum timing values). value derived from either fast (minimum) timing model worst case (maximum) timing model, depending which timing model used last timing analysis. standard compilation flow, Quartus software writes using timing values from worst case (maximum) timing model.
Click Click Design tab. Resolution list, select Library list, select work library. Start Simulation dialog box, expand work library. Select top-level design unit (your testbench).
Click
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Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim -sdftyp <instance path design>=<path SDO> work. <my_test bench>
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays objects current scope. View menu, point Debug Windows click Wave. Drag signals monitor from Objects window drop them into Wave window. Type following command ModelSim command prompt: <time period> Running Simulation Using ModelSim Command Prompt Type following commands ModelSim command prompt: wave /<signal name> <time period>
Simulating Verilog Designs
following sections provide step-by-step instructions performing gate-level timing simulation Verilog designs ModelSim-Altera software. using ModelSim-Altera software, pre-compiled libraries created when install software. Creating simulation libraries compiling simulation models steps required. proceed directly "Compile Testbench Design Files into Work Library" page 2-9.
Create Simulation Libraries
using Mentor Graphics ModelSim software version, must create simulation libraries correctly link them your design.
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following steps assume have already created ModelSim project. additional information, refer "Altera Design Flow with ModelSim ModelSim-Altera Software" page 2-3. Create Simulation Libraries Using ModelSim Perform following steps create simulation libraries: ModelSim software, File menu, point click Library. Create Library dialog appears. Select library logical mapping
names libraries should altera_mf (for Altera megafunctions) (for MegaWizard Plug-In Manager-generated entities).
Library Name box, type name newly created library. Click
Create Simulation Libraries Using ModelSim Command Prompt Type following commands ModelSim command prompt: vlib <library name> vmap <library name> <device family name> more information about library names, refer Table page 2-28. Compile Simulation Models into Simulation Libraries Using ModelSim Perform following steps compile simulation models into simulation libraries: File menu, point Project click Existing File. Browse <Quartus installation directory>/eda/sim_lib, necessary simulation model files your project. Select simulation model file, View menu, click Properties. Compile Library list, select correct library.
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Gate-Level Timing Simulation
Click Compile menu, click Compile selected.
Compile Simulation Models into Simulation Libraries Using ModelSim Command Prompt Type following command ModelSim command prompt: vlog -work <device family name> <Quartus installation directory> name>_atoms.v /eda/sim_lib/<device family
Compile Testbench Verilog Output File into Work Library
Compile testbench Verilog Output File into work library Compile menu clicking Compile clicking Compile toolbar icon Compile menu. Compile Testbench Verilog Output File into Work Libraries Using ModelSim Command Prompt Type following command ModelSim command prompt: vlog -work work <my_test bench.v> <my_verilog_output_file.vo> Resolve compilation errors before proceeding following section.
Loading Design
Perform following steps load design: Simulate menu, click Start Simulation. Start Simulation dialog appears. Click Libraries tab. Search Libraries box, click Add. Specify location altera_mf simulation libraries. using ModelSim-Altera version, refer Table page Table page location precompiled simulation libraries. using Mentor Graphics ModelSim software version, browse library that created earlier. Load Design dialog box, click Design expand work library.
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Select top-level design unit (your testbench). Resolution list, select Click
When simulating Verilog HDL, does have manually specified because Quartus generated Verilog Output File, there $sdf_annotate task that ModelSim uses look into current directory from which VSIM uses look SDO. your same directory from which VSIM, either copy into your current directory comment $sdf_annotate line Verilog Output File manually specify Load Design dialog box. Loading Design Using ModelSim Command Prompt Type following command ModelSim command prompt: vsim <location gate level simulation library> -work.<my_test bench>
Running Simulation
Perform following steps simulation: View menu, point Debug Windows click Objects. This command displays objects current scope. View menu, point Debug Windows click Wave. Drag signals monitor from Objects window drop them into Wave window. Type following command ModelSim command prompt: <time period> Running Simulation Using ModelSim Command Prompt Type following commands ModelSim command prompt: wave /<signal name> <time period>
design examples gate-level timing simulation VHDL Verilog language, refer
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Simulating Designs that Include Transceivers
Simulating Designs that Include Transceivers
your design includes Stratix Stratix transceiver, must compile additional library files perform functional timing simulations.
Stratix Functional Simulation
perform functional simulation your design that instantiates altgxb megafunction which enables gigabit transceiver block Stratix devices, compile stratixgx_mf model file into altgxb library. stratixiigx_mf model file references sgate libraries. using ModelSim PE/SE, must create these libraries perform simulation.
Example: Performing Functional Simulation Stratix Verilog
using ModelSim-Altera, compiling libraries necessary. simulate design directly typing following command: vsim lpm_ver altera_mf_ver sgate_ver altgxb work.<my design> using ModelSim SE/PE, must compile necessary libraries before simulation designs. Type following commands ModelSim command prompt compile simulate design: vlib vlib vlib vlib vlib vlog vlog vlog vlog vsim work altera_mf sgate altgxb -work 220model.v -work altera_mf altera_mf.v -work sgate sgate.v -work altgxb stratixgx_mf.v sgate-L altgxb work.<my design>
Example: Performing Functional Simulation Stratix VHDL
using ModelSim-Altera, compiling libraries necessary simulate design directly typing following command: vsim sgate altgxb work.<my design>
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using ModelSim SE/PE, must compile necessary libraries before simulation designs. Type following commands ModelSim command prompt compile simulate design: vcom vcom vcom vcom vsim -work altera_mf altera_mf_components.vhd altera_mf.vhd -work 220pack.vhd 220model.vhd -work sgate sgate_pack.vhd sgate.vhd -work altgxb stratixgx_mf.vhd stratixgx_mf_components.vhd altera_mf sgate altgxb work.<my design>
Stratix Post-Fit (Timing) Simulation
Perform post-fit timing simulation your design that includes Stratix transceiver compiling stratixgx_atoms stratixgx_hssi_atoms model files into stratixgx stratixgx_gxb libraries, respectively. stratixgx_hssi_atoms model file references sgate libraries. using ModelSim PE/SE, must create these libraries perform simulation.
Example: Performing Timing Simulation Stratix Verilog
using ModelSim-Altera, compiling libraries necessary. simulate design directly typing following command: vsim lpm_ver altera_mf_ver sgate_ver stratixgx_ver stratixgx_gxb work.<my design> +transport_int_delays +transport_path_delays using ModelSim SE/PE, must compile necessary libraries before simulate designs. Type following commands ModelSim command prompt compile simulate design: vlog -work 220model.v vlog -work altera_mf altera_mf.v vlog -work sgate sgate.v vlog -work stratixgx stratixgx_atoms.v vlog -work stratixgx_gxb stratixgx_hssi_atoms.v vsim altera_mf sgate stratixgx stratixgx_gxb work.<my design> +transport_int_delays +transport_path_delays
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Simulating Designs that Include Transceivers
This example assumes using ModelSim PE/SE. using ModelSim-Altera, type following command simulate your design:
vsim lpm_ver altera_mf_ver sgate_ver stratixgx_ver stratixgx_gxb work.<my design> +transport_int_delays +transport_path_delays
Example: Performing Timing Simulation Stratix VHDL
using ModelSim-Altera, compiling libraries necessary. simulate design directly typing following command: vsim altera_mf sgate stratixgx stratixgx_gxb work. design> using ModelSim SE/PE, must compile necessary libraries before simulate designs. Type following commands ModelSim command prompt compile simulate design: vcom -work 220pack.vhd 220model.vhd vcom -work altera_mf altera_mf_components.vhd altera_mf.vhd vcom -work sgate sgate_pack.vhd sgate.vhd vcom -work stratixgx stratixgx_atoms.vhd stratixgx_components.vhd vcom -work stratixgx_gxb stratixgx_hssi_atoms.vhd stratixgx_hssi_components.vhd vsim altera_mf sgate stratixgx stratixgx_gxb work. design> +transport_int_delays +transport_path_delays This example assumes using ModelSim PE/SE. using ModelSim-Altera, type following command simulate your design:
vsim altera_mf sgate stratixgx stratixgx_gxb work. design>
Stratix Functional Simulation
perform functional simulation your design that instantiates alt2gxb megafunction, which enables gigabit transceiver block Stratix devices, compile stratixiigx_hssi model file into stratixiigx_hssi library. stratixiigx_hssi_atoms model file references sgate libraries. using ModelSim PE/SE, must create these libraries perform simulation.
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Generate functional simulation netlist turning Generate Simulation Model Simulation Library alt2gxb MegaWizard Plug-In Manager (Figure 2-2). <alt2gxb entity name>.vho <alt2gxb module name>.vo generated current project directory. Quartus II-generated alt2gxb functional simulation library file references stratixiigx_hssi wysiwyg atoms.
Figure 2-2. alt2gxb MegaWizard
Example: Performing Functional Simulation Stratix Verilog
using ModelSim-Altera, compiling libraries necessary simulate design directly typing following command:
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Simulating Designs that Include Transceivers
vsim lpm_ver altera_mf_ver sgate_ver stratixgx_hssi_ver work.<my design> using ModelSim SE/PE, must compile necessary libraries before simulate designs. Type following commands ModelSim command prompt compile simulate design: vlog vlog vlog vlog vlog vsim -work 220model.v -work altera_mf altera_mf.v -work sgate sgate.v -work stratixiigx_hssi stratixiigx_hssi_atoms.v -work work <alt2gxb module name>.vo altera_mf sgate stratixgx_hssi work.<my design>
Example: Performing Functional Simulation Stratix VHDL
using ModelSim-Altera, compiling libraries necessary. simulate design directly typing following command: vsim altera_mf sgate stratixgx_hssi work.<my design> using ModelSim SE/PE, must compile necessary libraries before simulate designs. Type following commands ModelSim command prompt compile simulate design: vcom -work 220pack.vhd 220model.vhd vcom -work altera_mf altera_mf_components.vhd altera_mf.vhd vcom -work sgate sgate_pack.vhd sgate.vhd vcom -work stratixiigx_hssi stratixiigx_hssi_components.vhd stratixiigx_hssi_atoms.vhd vcom -work work <alt2gxb entity name>.vho vsim altera_mf sgate stratixgx_hssi work.<my design>
Stratix Post-Fit (Timing) Simulation
perform post-fit timing simulation your design that includes Stratix transceiver, compile stratixiigx_atoms stratixiigx_hssi_atoms into stratixiigx stratixiigx_hssi libraries, respectively. stratixiigx_hssi_atoms model file references sgate libraries. using ModelSim PE/SE, must create these libraries perform simulation.
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Example: Performing Timing Simulation Stratix Verilog
using ModelSim-Altera, compiling libraries necessary simulate design directly typing following command: vsim altera_mf sgate stratixiigx stratixiigx_hssi work.<my design> +transport_int_delays +transport_path_delays using ModelSim SE/PE, must compile necessary libraries before simulate designs. Type following commands ModelSim command prompt compile simulate design: vlog -work 220model.v vlog -work altera_mf altera_mf.v vlog -work sgate sgate.v vlog -work stratixiigx stratixiigx_atoms.v vlog -work stratixiigx_hssi stratixiigx_hssi_atoms.v vsim altera_mf sgate stratixiigx stratixiigx_hssi work.<my design> +transport_int_delays +transport_path_delays
Example: Performing Timing Simulation Stratix VHDL
using ModelSim-Altera, compiling libraries necessary. simulate design directly typing following command: vsim altera_mf sgate stratixiigx stratixiigx_hssi work.<mydesign> +transport_int_delays +transport_path_delays using ModelSim SE/PE, must compile necessary libraries before simulate designs. Type following commands ModelSim command prompt compile simulate design: vcom -work 220pack.vhd 220model.vhd vcom -work altera_mf altera_mf_components.vhd altera_mf.vhd vcom -work sgate sgate_pack.vhd sgate.vhd vcom -work stratixiigx stratixiigx_atoms.vhd stratixiigx_components.vhd vcom -work stratixiigx_hssi stratixiigx_hssi_components.vhd stratixiigx_hssi_atoms.vhd vsim altera_mf sgate stratixiigx stratixiigx_hssi work.<my design> +transport_int_delays +transport_path_delays
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Simulating Designs that Include Transceivers
This example assumes using ModelSim PE/SE. using ModelSim-Altera, need compile libraries type following command:
vsim altera_mf sgate stratixiigx stratixiigx_hssi work.<my design> +transport_int_delays +transport_path_delays
Transport Delays
default, ModelSim software filters pulses that shorter than propagation delay between primitives. Turning transport delay options ModelSim software prevents simulation tool from filtering these pulses. following options ensure that signal pulses seen simulation results.
+transport_path_delays
this option when pulses your simulation shorter than delay within gate-level primitive.
+transport_int_delays
this option when pulses your simulation shorter than interconnect delay between gate-level primitives. +transport_path_delays +transport_int_delays options also used default NativeLink feature gate-level timing simulation.
more information about either these options, refer ModelSim Altera Command Reference installed with ModelSim software. following ModelSim software command describes command-line syntax perform gate-level timing simulation with device family library:
vsim stratixii -sdftyp /i1=filtref_vhd.sdo work.filtref_vhd_vec_tst +transport_int_delays +transport_path_delays
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Using NativeLink Feature with ModelSim
NativeLink feature Quartus software facilitates seamless transfer information between Quartus software tools allows ModelSim within Quartus software.
Setting NativeLink
ModelSim automatically from Quartus software using NativeLink feature, must specify path your simulation tool performing following steps: Tools menu, click Options. Options dialog appears. Category list, select Tool Options. Double-click entry under Location executable beside name your Tool. Type browse directory containing executables your tool. ModelSim-Altera ModelSim SE/PE, executable files stored win32aloem win32 directories, respectively. c:\<ModelSim-Altera installation path>\win32aloem c:\<ModelSim installation path>\win32 Click
also specify path simulator's executables using set_user_option command: set_user_option -name EDA_TOOL_PATH_MODELSIM <path executables> set_user_option -name EDA_TOOL_PATH_MODELSIM_ALTERA <path executables>
Performing Simulation Using NativeLink
functional simulation with ModelSim software Quartus software, perform following steps: Assignments menu, click Tool Settings. Settings dialog appears. Category list, select Simulation. Simulation page appears (Figure 2-3).
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Using NativeLink Feature with ModelSim
Figure 2-3. Simulation Page Settings Dialog
Tool name list, select following choices:
ModelSim ModelSim-Altera
your design written entirely Verilog VHDL, NativeLink feature automatically chooses correct language Altera simulation libraries. your design written with mixed languages, NativeLink feature uses default language specified Format output netlist list. change default
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language when there mixed language design, under Netlist Writer options, Format output netlist list, select VHDL Verilog. Table 2-11 shows design languages output netlists simulation models.
Table 2-11. NativeLink Design Languages Design File
Verilog VHDL Mixed Mixed
Format Output Netlist
Verilog VHDL
Simulation Models Used
Verilog VHDL Verilog VHDL
mixed language simulation, choose same language that used generate your megafunctions ensure correct parameter passing between megafunctions Altera libraries. example, your altsyncram megafunction generated VHDL, choose VHDL format output netlist. When creating mixed language designs, important aware following: Simulation tools allow seamless passing parameters when VHDL entity instantiated Verilog designs. ModelSim ModelSim-Altera software allow Verilog User Defined Primitives (UDPs) instantiated VHDL designs.
have testbench files macro scripts, enter information under NativeLink settings. more information about setting testbench with NativeLink, refer "Setting Testbench" page 2-48.
Click
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Using NativeLink Feature with ModelSim
Processing menu, point Start click Start Analysis Elaboration perform analysis elaboration. This command collects your file name information builds your design hierarchy preparation simulation. Tools menu, point Simulation Tool click Simulation automatically ModelSim, compile necessary design files, complete simulation.
Performing Gate-Level Simulation Using NativeLink
gate-level timing simulation with ModelSim software Quartus software, perform following steps: Assignments menu, click Tool Settings. Settings dialog appears. Category list, select Simulation. Simulation page appears (Figure page 2-45). Tool name list, select following:
ModelSim ModelSim-Altera
Under Netlist Writer options, Format output netlist list, choose VHDL Verilog. also modify where want post-synthesis netlist generated editing browsing directory Output directory box. gate-level simulation after each full compilation, turn Gate Level Simulation automatically after compilation. have testbench files macro scripts, enter information under NativeLink settings. Click Processing menu, point Start click Start Netlist Writer generate simulation netlist your design. Tools menu, point Simulation Tool click Gate Level Simulation automatically ModelSim, compile necessary design files, complete simulation.
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ModelSim Macro File (*.do) generated directory while running NativeLink. perform simulation with file directly from ModelSim when rerun simulation without using NativeLink. perform simulation directly without NativeLink, type following command ModelSim console: <generated_do_file>.do.
Setting Testbench
NativeLink compile your design files testbench files, simulation tool automatically perform simulation. NativeLink simulation, perform following steps: Assignments menu, click Settings. Settings dialog appears. Category list, click icon expand Tool Settings select Simulation. Simulation page appears. Under NativeLink settings, select None, Compile test bench, Script compile test bench (Table 2-12).
Table 2-12. NativeLink Settings Settings
None Compile test bench
Description
Compile simulation models design files. NativeLink compiles simulation models, design files, testbench files, starts simulation.
Script compile test bench NativeLink compiles simulation models design files. script provide sourced after design files compile. this option when want create your script compile your testbench perform simulation.
select Compile test bench, select your test bench setup from Compile test bench list. different testbench setups specify different test scenarios. there testbench setups entered, create testbench setup performing following steps: Click Test Benches. Test Benches dialog appears. Click New. Test Bench Settings dialog appears. Test Bench name box, type testbench setup name that identifies different test bench setups.
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Using NativeLink Feature with ModelSim
Test bench entity box, type top-level testbench entity name. example, Quartus generated VHDL testbench, type <Vector Waveform File name>_vhd_vec_tst. Instance box, type full instance path level your FPGA design. example, Quartus generated VHDL testbench, type Under Simulation period, select simulation until vector stimuli used specify time simulation. Under Test bench files, browse your testbench files File name box. Down button reorder your files. script used NativeLink compiles files order from bottom. also specify library name version compile testbench file. Native link compiles testbench library name using specified version.
Click Test Benches dialog box, click
Under NativeLink settings, turn script setup simulation browse your script. Your script executed simulation after loading design using vsim command. choose Script compile test bench, browse your script click
Creating Testbench
Quartus software, create Verilog VHDL testbench from Vector Waveform File. generated testbench includes behavior input stimulus applies your instantiated top-level FPGA design. File menu, click Open. Open dialog appears. Click Files type arrow select Waveform/Vector Files. Select your Vector Waveform File. Click Open.
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File menu, click Export. Export dialog appears. Click Save type arrow select VHDL Test Bench File (*.vht) Verilog Test Bench File (*.vt). turn self-checking code file check your simulation results against your Vector Waveform File. Click Export. Your VHDL Verilog testbench file generated your project directory.
Scripting Support
procedures create settings described this chapter script. also some procedures command line prompt.
more information about scripting, refer Scripting chapter volume Quartus Handbook. more information about command line scripting, refer Command-Line Scripting chapter volume Quartus Handbook. detailed information about scripting command options, refer Qhelp command line help browser. Type this command start Qhelp help browser: quartus_sh -qhelpr
Generating Post-Synthesis Simulation Netlist ModelSim
Quartus software generate post-synthesis simulation netlist with commands with command command-line prompt. following example assumes that selecting ModelSim (Verilog output from Quartus software).
Commands
following commands output format Verilog HDL, simulation tool ModelSim Verilog HDL, generate functional netlist: set_global_assignment-name EDA_SIMULATION_TOOL "ModelSim (Verilog)"r set_global_assignment-name EDA_GENERATE_FUNCTIONAL_NETLIST
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Software Licensing Licensing Set-Up
Command Prompt
following command generate simulation output file ModelSim simulator. Specify VHDL Verilog format: quartus_eda <project name> -simulation=on -format=<format> -tool=ModelSim -functional
Generating Gate-Level Timing Simulation Netlist ModelSim
Quartus software generate gate-level timing simulation netlist with commands with command command prompt.
Commands
following commands:
set_global_assignment set_global_assignment set_global_assignment set_global_assignment -name -name -name -name EDA_SIMULATION_TOOL EDA_SIMULATION_TOOL EDA_SIMULATION_TOOL EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" "ModelSim-Altera (VHDL)" "ModelSim (Verilog)" "ModelSim (VHDL)"
Command Line
Generate simulation output file ModelSim simulator specifying VHDL Verilog format typing following command command prompt: quartus_eda <project name> -simulation=on -format=<format> -tool=ModelSim
Software Licensing Licensing Set-Up
License ModelSim-Altera software with parallel port software guard (T-guard), guard, FIXEDPC license, network FLOATNET FLOATPC license. Each Altera software subscription includes license either VHDL Verilog HDL. Network licenses with multiple users have their licenses split between VHDL Verilog ratio. software guard supported versions earlier than Mentor Graphics ModelSim software 5.8d.
Obtain license ModelSim-Altera software from Altera website www.altera.com. licensing information Mentor Graphics ModelSim software directly from Mentor Graphics. Refer Figure set-up process.
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ModelSim-Altera versions prior 5.5b, PCLS utility included with software license.
Figure 2-4. ModelSim-Altera Licensing Process
Initial Installation
ModelSim-Altera Properly Licensed?
LM_LICENSE_FILE Variable
Finish
LM_LICENSE_FILE Variable
Altera recommends setting LM_LICENSE_FILE environment variable location license file.
Conclusion
Using ModelSim-Altera simulation software within Altera FPGA design flow enables Altera software users easily accurately perform functional simulations, post-synthesis simulations, gate-level simulations their designs. Proper verification designs functional, post-synthesis, post place-and-route stages using ModelSim-Altera software helps ensure design functionality success and, ultimately, quick time-to-market. This chapter references following documents:
Referenced Documents
Quartus Classic Timing Analyzer chapter volume Quartus Handbook Quartus TimeQuest Timing Analyzer chapter volume Quartus Handbook Scripting chapter volume Quartus Handbook
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Document Revision History
Document Revision History
Table 2-13 shows revision history this chapter.
Table 2-13. Document Revision History Date Document Version
2007 v7.1.0
Changes Made
Updated "Functional Simulation" page 2-5. Updated "Gate-Level Timing Simulation" page 2-23. Added "Perform Timing Simulation Using Post-synthesis Netlist" page 2-26. Updated examples "Simulating Designs that Include Transceivers" page 2-37. Updated procedures "Setting Testbench" page 2-48. Added "Referenced Documents" page 2-52. Updated Quartus software revision date only.
Summary Changes
Updated Quartus software version 7.1.
March 2007 v7.0.0 November 2006 v6.1.0 2006 v6.0.0
Updated Quartus software version 6.1.
Added ModelSim-Altera Edition Table 2-1. Added Stratix library support Table 2-8, 2-9, 2-10. Other minor changes chapter.
Updated Quartus software version 6.0.0: Added section setting ModelSim Simulation Tool Updated Tools Settings GUI. Updated Synopsys Design Constraints File information. Updated device information. Added Quartus II-Generated Testbench information Updated megafunction information. Updated Quartus software version 5.1.
October 2005 v5.1.0 2005 v5.0.0 December 2004 v3.0 June 2004 v2.0 February 2004 v1.0
Updates tables, figures. Updated information. functionality Quartus software 5.0. Reorganized chapter, updated information. Updates tables, figures. functionality Quartus software 4.2. Updates tables, figures. functionality Quartus software 4.1.
Initial release.
Altera Corporation 2007
2-53 Preliminary
Quartus Handbook, Volume
2-54 Preliminary
Altera Corporation 2007

QII53001-7.1.0 Altera® software subscription includes license Mod

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