QII52014-7.1.0 With today's large, high-pin-count high-speed FPGA

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QII52014-7.1.0 With today's large, high-pin-count high-speed FPGA

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QII52014-7.1.0
With today's large, high-pin-count high-speed FPGA devices, good printed circuit board (PCB) design practices more essential than ever ensure correct operation your system. Typically, design takes place concurrently with design programming FPGA. Signal assignments initially made FPGA ASIC designer, board designer correctly transfer these assignments symbols used their system circuit schematics board layout. board design progresses, reassignments requested required optimize layout. These reassignments must turn relayed FPGA designer that assignments processed through FPGA using updated place-and-route. Cadence provides tools support this type design flow. This chapter addresses Quartus® software interacts with Cadence Allegro Design Entry software Allegro Design Entry (Component Information System) software (also known OrCAD Capture CIS) provide complete FPGA-to-board integration design workflow. This chapter provides information about following topics:
Cadence tool description, history, comparison general design flow between Quartus software Cadence Allegro Design Entry software Cadence Allegro Design Entry software Generating schematic symbols from your FPGA design Cadence Allegro Design Entry software Updating Design Entry symbols when signal assignment changes made Quartus software Creating schematic symbols Cadence Allegro Design Entry software from your FPGA design Updating symbols Cadence Allegro Design Entry software when signal assignment changes made Quartus software Using Altera®-provided device libraries Cadence Allegro Design Entry software
This chapter intended primarily board design layout engineers want begin FPGA board integration process while FPGA still design phase. addition, part librarians benefit from learning take output from Quartus software create library parts symbols.
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Preliminary
Quartus Handbook, Volume
instructions this chapter require following software:
Quartus software version later Cadence Allegro Design Entry Cadence Allegro Design Entry software version 15.2 later using OrCAD Capture software, must have version 10.3 later (CIS optional) Because Cadence Allegro Design Entry software based OrCAD Capture, these programs very similar. this reason, this chapter refers Allegro Design Entry software directions; however, these directions also apply OrCAD Capture unless otherwise noted.
obtain license Cadence tools described this chapter, product information, support, training, refer Cadence website, www.cadence.com. information about OrCAD Capture option, refer OrCAD website, www.orcad.com. Cadence OrCAD support training, refer Design Automation website, www.ema-eda.com. design tools described this chapter have similar functionality, there differences their well where access product information. Table lists products described this chapter provides information about changes, product information, support.
Product Comparison
Table 7-1. Cadence OrCAD Product Comparison Cadence Allegro Design Entry
Former Name Concept Expert More commonly known former name, Cadence renamed board design tools 2004 under Allegro name. Cadence Allegro series, formerly known Expert Vendor Design Flow Series, high-end, high-speed design.
Cadence Allegro Design Entry
Capture Studio Based directly OrCAD Capture CIS, this tool still developed OrCAD sold marketed Cadence. provides support training. Cadence Allegro series, formerly known Studio Series, small- medium-level design. www.cadence.com www.ema-eda.com www.orcad.com
OrCAD Capture
basis Design Entry still developed OrCAD continued existing OrCAD customers. provides support training OrCAD products.
History
Information www.ema-eda.com Support
www.cadence.com
www.ema-eda.com www.orcad.com
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FPGA-to-PCB Design Flow
FPGA-to-PCB Design Flow
examples this section, create design flow integrating Altera FPGA design from Quartus software through circuit schematic Allegro Design Entry software (Figure 7-1) Allegro Design Entry software (Figure 7-2).
Figure 7-1. Design Flow with Allegro Design Entry Software
Start FPGA Design Quartus Software Create Change Assignments Start Design (Allegro Design Entry HDL) Project Manager Create Open Project Part Developer Assignment Analysis Full Compilation Import Update Assignments
Create Update FPGA Symbol .pin
Edit Fracture Symbol Design Entry Instantiate Symbol Schematic
Forward Board Layout Tool Board Layout Tool Layout Route FPGA
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Figure 7-2. Design Flow with Allegro Design Entry Software
Start FPGA Design Quartus Software Create Change Assignments Start Design (Allegro Design Entry CIS) Design Entry Create Open Project
Generate Update Part Assignment Analysis Full Compilation
Edit Fracture Symbol
Instantiate Symbol Schematic .pin
Forward Board Layout Tool Board Layout Tool Layout Route FPGA
basic steps complete design flow integrate Altera FPGA design starting Quartus software through circuit schematic Design Entry Design Entry follows:
Start Quartus software. Quartus software, compile your design generate Pin-Out (.pin) file transfer assignments Cadence tool. using Cadence Allegro Design Entry software your schematic design: Open existing project create project Allegro Project Manager. Construct symbol update existing symbol using Allegro Librarian Part Developer. With Part Developer, edit your symbol fracture into smaller parts, desired. Instantiate symbol your Design Entry software schematic transfer design your board layout tool.
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Setting Quartus Software
using Cadence Allegro Design Entry software your schematic design, perform following steps: Generate part within existing Allegro Design Entry project, referencing Pin-Out file output from Quartus software. update existing symbol with Pin-Out file. Split symbol into smaller parts desired. Instantiate symbol your Design Entry schematic transfer design your board layout tool.
Figures show possible design flows, depending your tool choice. Cadence Librarian Expert license required Librarian Part Developer create FPGA symbols. update symbols with changes made FPGA design point using these tools.
Setting Quartus Software
transfer signal assignments from Quartus software Cadence design tools generating Quartus project Pin-Out file. Pin-Out file output file generated Quartus Fitter that contains assignment information. Quartus Planner Assignment Editor change assignments contained Pin-Out file. This file cannot used import assignment changes into Quartus software. only transfer assignments with Cadence design tools. Pin-Out file lists used unused pins your selected Altera device. also provides following basic information fields each assigned device:
signal name usage number Signal direction standard Voltage bank User Fitter-assigned
information about using Quartus Planner create change assignment details, refer Management chapter volume Quartus Handbook.
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Generating Pin-Out Files
Quartus software automatically generates Pin-Out file when your FPGA design fully compiled when start Assignment Analysis. start Assignment Analysis, Processing menu, point Start click Start Assignment Analysis. file output Quartus Fitter. file generated placed your Quartus design directory with name <project name>.pin. Cadence design tools generate change this file.
more information about signal assignment transfer files that Quartus software import export, refer Management chapter volume Quartus Handbook. Cadence Allegro Design Entry software Cadence's high-end schematic capture tool (part Cadence series design flow). this software create flat circuit schematics types design. Cadence Allegro Design Entry software also create hierarchical schematics facilitate design reuse team-based design. With Cadence Allegro Design Entry software, design flow from FPGA-to-board one-way, using only Pin-Out file generated Quartus software. Signal assignment changes only made Quartus software reflected updated symbols Design Entry project. Routing assignment changes made board layout tool Design Entry symbol cannot back-annotated Quartus software.
FPGA-to-Board Integration with Cadence Allegro Design Entry Software
Figure shows design flow with Cadence Allegro Design Entry software.
more information about Cadence Allegro Design Entry software Part Developer, including licensing, support, usage, training, product updates, refer Help software refer Cadence page www.cadence.com.
Symbol Creation
addition circuit simulation, circuit board schematic creation first tasks required design PCB. Schematics required understand works, generate netlist that passed board layout tool board design routing. Allegro Librarian Part Developer provides ability create schematic symbols based FPGA designs exported from Quartus software.
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FPGA-to-Board Integration with Cadence Allegro Design Entry Software
Create symbols Design Entry with Allegro Librarian Part Developer available Allegro Project Manager. Part Developer recommended method importing FPGA designs into Cadence Allegro Design Entry software. must have Librarian Expert license from Cadence Part Developer. Part Developer provides graphical interface with many options creating, editing, fracturing, updating symbols. Part Developer, must create edit symbols manually Symbol Schematic View Cadence Allegro Design Entry software. have Librarian Expert license, still automatically create FPGA symbols using programmable (PIC) design flow found Allegro Project Manager. more information about using design flow, refer Help Cadence design tools, Cadence website www.cadence.com.
Before create symbol from FPGA design, must open create Design Entry design project. this with Allegro Project Manager, main interface Cadence tools. open existing design Allegro Project Manager, File menu, click Open select main design file your project (found your Allegro Design Entry project directory called <project directory>.cpm). create project, File menu, point click Design. Project Wizard appears. wizard name your project, file location, define associated part libraries.
Allegro Librarian Part Developer
Create, fracture, edit schematic symbols your FPGA designs Altera devices using Part Developer. Most FPGA devices physically large with hundreds pins, requiring large schematic symbols that single schematic page. Symbols designed Part Developer split fractured into number functional blocks called slots, allowing multiple smaller part fractures exist same schematic page across multiple pages. Figure highlights Part Developer fits into design flow.
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Figure 7-3. Part Developer Design Flow
Part Developer Import Update Assignments
.pin
Create Update FPGA Symbol
Edit Fracture Symbol
Design Entry Instantiate Synbol Schematic
Forward Board Layout Tool Board Layout Tool Layout Route FPGA
Notes Figure 7-3:
Refer Figure full design flow flowchart details. Grayed steps part FPGA Symbol creation update process.
Part Developer from Project Manager (Figure 7-4). start Part Developer Project Manager, Flows menu, click Library Management. Click Part Developer start tool.
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FPGA-to-Board Integration with Cadence Allegro Design Entry Software
Figure 7-4. Invoking Part Developer from Project Manager
Import Export Wizard Once Part Developer, Import Export Wizard import your assignments from Quartus software. access Wizard, perform following steps: File menu, click Import Export. Import Export Wizard appears (Figure 7-5).
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Figure 7-5. Import Export Wizard
Select Import FPGA. Click Next. Select Source page appears (Figure 7-6).
Figure 7-6. Select Source Page
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FPGA-to-Board Integration with Cadence Allegro Design Entry Software
Vendor list, select Altera. Tool list, select quartusII. specify Pin-Out file File field, select Pin-Out file your Quartus project directory. Click Simulation Options want select simulation input files. Click Next. Select Destination page shown (Figure 7-7).
Figure 7-7. Select Destination Page
create component library, click Generate Custom Component. base your symbol existing component, click standard component.
want this previously created generic symbols FPGA device. place your signal assignments from Quartus software this symbol reuse symbol base time have FPGA design.
Library list, select existing library. select from cells contained selected library. Each cell represents symbol versions part fractures that particular part. Cell list, select existing cell base your part. Destination Library list, select destination library component. Click Next. preview your import data shown (Figure 7-8).
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Figure 7-8. Preview Import Data Window
Review assignments importing into Part Developer based data Pin-Out file. location each included information this window, inputs placed left side created symbol, outputs right, power pins top, ground pins bottom. Make desired changes. When have completed your changes, click Finish create symbol. Part Developer main screen shown. Part Developer point your Librarian Expert license file, error message displays bottom message text window Part Developer when select Import Export command. point your Librarian Expert license, File menu, click Change Product select correct product license.
more information about licensing obtaining licensing support, contact Cadence refer their website www.cadence.com. Edit Fracture Symbol After save your symbol Part Developer software, edit symbol graphics, fracture symbol into multiple slots, change package symbol properties. These actions available from Part Developer main window.
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FPGA-to-Board Integration with Cadence Allegro Design Entry Software
Part Developer Symbol Editor contains many graphical tools edit graphics particular symbol. Select symbol cell hierarchy edit symbol graphics. Symbol Pins shown. Edit preview graphic symbol Symbol Pins tab. Fracturing Part Developer package into separate symbol slots especially useful FPGA designs. single symbol most FPGA packages large single schematic page. Splitting part into separate slots allows organize parts symbol function, creating cleaner circuit schematics. example, could create slot symbol, second slot JTAG symbol, third slot power/ground symbol. Figure shows part fractured into separate slots. Figure 7-9. Splitting Symbol into Multiple Slots Notes (1),
d[7.0] yn_out[7.0]
VCCIO1
VCCIO2
VCCIO3
filtref
clkx2 newt reset follow yvalid
DCLK DATA0 NCONFIG MSEL0 MSEL1
filtref
VCCA_PLL1 VCCA_PLL2 GNDA_PLL1 GNDA_PLL2 GNDG_PLL1 GNDG_PLL2
CONF_DONE NSTATUS ASDO NCSO filtref NCEO
Version
Version
Version
Notes Figure 7-9:
Figure represents Cyclone device with JTAG passive serial (PS) mode configuration option settings. Symbols created other devices other configuration modes have different sets configuration pins, fractured similar manner. Symbol fractures referred different ways each tools described this chapter. Refer Table specific tool naming conventions. power/ground slot shows only representation power ground pins. actuality, device contains high number power ground pins.
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VCCIO4
VCCINT
Quartus Handbook, Volume
While Part Developer software refers symbol fractures slots, other tools described this chapter different names refer symbol fractures. Table lists symbol fracture naming conventions each tools addressed this chapter.
Table 7-2. Symbol Fracture Naming Allegro Librarian Part Developer Software
During symbol generation During symbol schematic instantiation Slots
Allegro Design Entry Software
Versions
Allegro Design Entry Software
Sections Parts
fracture part into separate slots, modify slot locations pins parts that already fractured Part Developer, perform following steps: Start Cadence Allegro Design Project Manager. Flows menu, click Library Management. Library Management design flow shown. Click Part Developer. Part Developer launches. Click name package want change cell hierarchy. Package appears. Click Functions/Slots. creating slots want change slot location some pins, proceed step creating slots, click Add. dialog appears, allowing extra symbol slots. number extra slots want existing symbol, total number desired slots part. Click Click Distribute Pins. slot where each should reside. checkboxes each column move pins from slot another. standard cut, copy, paste keyboard commands selected groups checkboxes move multiple pins from slot another. Click After distributing pins, click Package click Generate Symbol(s). Generate Symbols dialog appears. Select whether create symbol modify existing symbol each slot. Click
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FPGA-to-Board Integration with Cadence Allegro Design Entry Software
newly generated modified slot symbols display separate symbols cell hierarchy. Each these symbols edited individually. Part Developer lets remap assignments Package main Part Developer window. signals remapped different pins Part Developer, changes reflected only regenerated symbols your schematics. cannot transfer assignment changes Quartus software from Part Developer, which creates potential mismatch schematic symbols assignments FPGA design. assignment changes necessary, make changes Quartus Planner instead Part Developer, update symbol described following sections.
more information about creating, editing, organizing component symbols with Allegro Librarian Part Developer, refer Part Developer Help. Update FPGA Symbol design process continues, need make changes logic design Quartus software, placing signals different pins after design recompiled, Quartus Planner make changes manually. board designer request such changes improve board routing layout. These types changes must carried forward circuit schematic board layout tools ensure signals connected correct pins FPGA. Updating Pin-Out file Quartus software facilitates this flow. Figure 7-10 shows this part design flow.
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Figure 7-10. Updating FPGA Symbol Design Flow
Part Developer Import Update Assignments
.pin
Create Update FPGA Symbol
Edit Fracture Symbol
Design Entry Instantiate Symbol Schematic
Forward Board Layout Tool Board Layout Tool Layout Route FPGA
Notes Figure 7-10:
Refer Figure full design flow flowchart details. Grayed steps part FPGA Symbol update process.
Once Pin-Out file been updated, perform following steps update symbol using Allegro Librarian Part Developer: File menu, click Import Export. Import Export Wizard appears. list actions perform, select Import FPGA. Click Next. Select Source Page shown. Select updated source FPGA assignment information. Vendor list, select Altera. Tool list, select quartusII. File field, click browse specify updated Pin-Out file your Quartus project directory. Click Next. Select Destination window shown. Select source component destination cell updated symbol. create component based updated assignment data, select Generate Custom Component. This replaces cell listed under Specify Library Cell name header with new, non-fractured cell. symbol edits fractures
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lost. preserve these edits selecting standard component select existing library cell. Select destination library component click Next. Preview Import Data page shown. Make additional changes your symbol. Click Next. list messages displays summarizing what changes will made cell. accept changes update cell, click Finish. main Part Developer window shown. edit, fracture, generate updated symbols usual from this window. Part Developer point your Librarian Expert license file, error message displays bottom message text window Part Developer when select Import Export command. point your Librarian Expert license, File menu, click Change Product, select correct product license. more information about licensing obtaining licensing support, contact Cadence refer their website www.cadence.com.
Instantiating Symbol Cadence Allegro Design Entry Software
Once symbol saved Part Developer, instantiate symbol your Design Entry schematic. Allegro Project Manager, switch board design flow. Flows menu, click Board Design. Click Design Entry start Design Entry software. newly created symbol your schematic, right-click main schematic window choose Component, Component menu, click Add. Component dialog appears. Select symbol library location, select name cell created from list cells.
symbol "attached" your cursor placement schematic. fractured symbol into slots, right-click symbol choose Version select slots placement schematic.
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more information about Cadence Allegro Design Entry software, including licensing, support, usage, training, product updates, refer Help software Cadence website www.cadence.com. Cadence Allegro Design Entry software Cadence's mid-level schematic capture tool (part Cadence series design flow based OrCAD Capture CIS). this software create flat circuit schematics types design. also create hierarchical schematics facilitate design reuse team-based design using this software. With Cadence Allegro Design Entry software, design flow from FPGA-to-board unidirectional using only Pin-Out file generated Quartus software. Signal assignment changes only made Quartus software reflected updated symbols Design Entry schematic project. Routing assignment changes made board layout tool Design Entry symbol cannot back-annotated Quartus software. Figure 7-11 shows design flow with Cadence Allegro Design Entry software.
FPGA-to-Board Integration with Allegro Design Entry
Figure 7-11. Design Flow with Cadence Allegro Design Entry Software
Start FPGA Design Quartus Software Create Change Assignments Start Design (Allegro Design Entry CIS) Design Entry Create Open Project
Generate Update Part Assignment Analysis Full Compilation
Edit Fracture Symbol
Instantiate Symbol Schematic .pin
Forward Board Layout Tool Board Layout Tool Layout Route FPGA
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FPGA-to-Board Integration with Allegro Design Entry
more information about Cadence Allegro Design Entry software, including licensing, support, usage, training, product updates, refer Help software, Cadence website www.cadence.com, Design Automation website www.ema-eda.com.
Allegro Design Entry Project Creation
Cadence Allegro Design Entry software built-in support creating schematic symbols using assignment information imported from Quartus software. have already created project Cadence Allegro Design Entry software, perform following steps create project: File menu, point click Project. Project Wizard starts. When create project, select Board Wizard, Programmable Logic Wizard, blank schematic. Select Board Wizard create project where select which part libraries use, select blank schematic. Programmable Logic Wizard used only build FPGA logic design Cadence Allegro Design Entry software, which unnecessary when using Quartus software. other special configuration your project required. Your project created specified location initially consists files: OrCAD Capture Project (.opj) file Schematic Design (.dsn) file.
Generate Part
After create project open existing project Allegro Design Entry software, generate schematic symbol based your Quartus FPGA design. also update existing symbol your Pin-Out file been updated Quartus software. Cadence Allegro Design Entry software stores component symbols OrCAD Library (.olb) files. When symbol placed library attached project, immediately available instantiation project schematic.
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symbols existing library create library specifically symbols generated from your FPGA designs. create library, perform following steps: File menu, point click Library Cadence Allegro Design Entry software create default library named library1.olb. This library appears Library folder Project Manager window Cadence Allegro Design Entry software. Right-click library choose Save specify desired name location library. library file created until save library.
create symbol represent your FPGA design your schematic. generate schematic symbol, perform following steps: Start Cadence Allegro Design Entry software. Tools menu, click Generate Part. Generate Part dialog appears (Figure 7-12).
Figure 7-12. Generate Part Dialog
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FPGA-to-Board Integration with Allegro Design Entry
Netlist/source file type field, click Browse specify Pin-Out file from your Quartus design. Netlist/source file type list, select Altera File. Enter part name. Specify Destination part library symbol. select existing library part, library created with default name that matches name your Design Entry project. Select Create part creating brand symbol this design. Select Update pins existing part library updated your Pin-Out file Quartus software want transfer assignment changes existing symbol. Select other desired options Implementation type <none>. symbol primitive library part based only Pin-Out file does need special implementation. Click Review Undo warning click complete symbol generation.
symbol generated placed selected library library found Outputs folder design Project Manager window (Figure 7-13). Double-click name symbol graphical representation edit manually using tools available Cadence Allegro Design Entry software. Figure 7-13. Project Manager Window
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more information about creating editing symbols Allegro Design Entry software, refer Help software.
Split Part
Once symbol saved project's library, fracture symbol into multiple parts called sections. Fracturing part into separate sections especially useful FPGA designs. single symbol most FPGA packages large single schematic page. Splitting part into separate sections allows organize parts symbol function, creating cleaner circuit schematics. example, could create slot symbol, second slot JTAG symbol, third slot power/ground symbol. Figure 7-14 shows part fractured into separate sections. Figure 7-14. Splitting Symbol into Multiple Sections Notes (1),
d[7.0] yn_out[7.0]
VCCIO1
VCCIO2
VCCIO3
filtref
clkx2 newt reset follow yvalid
DCLK DATA0 NCONFIG MSEL0 MSEL1
filtref
VCCA_PLL1 VCCA_PLL2 GNDA_PLL1 GNDA_PLL2 GNDG_PLL1 GNDG_PLL2
CONF_DONE NSTATUS ASDO NCSO filtref NCEO
Version
Version
Version
Notes Figure 7-14:
Figure 7-14 represents Cyclone device with JTAG passive serial (PS) mode configuration option settings. Symbols created other devices other configuration modes have different sets configuration pins, fractured similar manner. Symbol fractures referred different ways each tools described this chapter. Refer Table specific tool naming conventions. power/ground section shows only representation power ground pins. actuality, device contains high number power ground pins.
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VCCIO4
VCCINT
FPGA-to-Board Integration with Allegro Design Entry
While symbol generation Design Entry software refers symbol fractures sections, other tools described this chapter different names refer symbol fractures. Refer Table page 7-14 symbol fracture naming conventions each tools addressed this chapter.
split part into sections, select part library Project Manager window Design Entry CIS. Tools menu, click Split Part right-click part choose Split Part. Split Part Section Input Spreadsheet shown (Figure 7-15). Figure 7-15. Split Part Section Input Spreadsheet
Each spreadsheet represents symbol. spreadsheet column labeled Section indicates section symbol which each assigned. default, pins symbol located section Change values this column assign pins different, sections symbol. also specify side section which will reside changing values Location column. When finished, click Split. symbol appears same library original with name <original part name>_Split1.
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View edit each section individually. view sections part, double-click part. Part Symbol Editor window shown. first section part displayed editing. View menu, click Package view thumbnails part sections. Double-click thumbnail edit that section symbol.
more information about splitting parts into sections editing symbol sections Cadence Allegro Design Entry software, refer Help software.
Instantiate Symbol Design Entry Schematic
After symbol saved library your Design Entry project, instantiate page your schematic. Open schematic page Project Manager window Cadence Allegro Design Entry software. schematic page, newly created symbol your schematic, Place menu, click Part. Place Part dialog appears (Figure 7-16). Figure 7-16. Place Part Dialog
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Select symbol library location newly created part name. select part that split into sections, select section place from Part pop-up menu. Click symbol attached your cursor placement schematic. Click schematic page place symbol.
more information about using Cadence Allegro Design Entry software, refer Help software.
Altera Libraries Design Entry
Altera provides downloadable OrCAD Library Files many device packages. these libraries your Design Entry project update symbols with assignments contained Pin-Out file generated Quartus software. This allows downloaded library symbols base creating custom schematic symbols with your assignments that edit fracture desired. This increase productivity reducing amount time takes create edit symbol. Altera-provided libraries with your Design Entry project, perform following steps: Download library your target device from Download Center page found through Support page Altera website www.altera.com. Make copy appropriate OrCAD Library file that original symbols altered. Place copy convenient location such your Design Entry project directory. Project Manager window Cadence Allegro Design Entry software, click once Library folder select Edit menu, click Project right-click Library folder choose File select copy downloaded OrCAD Library file your project. library added list part libraries your project. Tools menu, click Generate Part. Generate Part dialog appears (Figure 7-17).
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Figure 7-17. Generate Part Dialog
Netlist/source file type field, click Browse specify Pin-Out file your Quartus design. From Netlist/source file type list, select Altera File. part name, enter name target device same appears downloaded library file. example, using device from CYCLONE06.OLB library, part name match devices this library such ep1c6f256. rename symbol later Project Manager window after part updated. Destination part library copy downloaded library added project. Select Update pins existing part library. Click then click Yes.
symbol updated with your assignments. Double-click symbol Project Manager window view edit symbol. View menu, click Package want view edit other sections
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Conclusion
symbol. symbol downloaded library already fractured into sections, some larger packages are, edit each section cannot further fracture part. Generate part without using downloaded part library require additional sections.
more information about creating, editing, fracturing symbols Cadence Allegro Design Entry software, refer Help software. Transferring complex, high-pin-count FPGA design prototyping manufacturing daunting process that lead errors netlist design, especially when different engineers working different parts project. design workflow available when Quartus software used with tools from Cadence assists FPGA designer board designer preventing such errors focusing attention design. This chapter references Management chapter volume Quartus Handbook.
Conclusion
Referenced Document
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Document Revision History
Table shows revision history this chapter.
Table 7-3. Document Revision History Date Document Version
2007 v7.1.0 March 2007 v7.0.0 November 2006 v6.1.0 2006 v6.0.0 November 2005 v5.1.1 October 2005 v5.1.0
Changes Made
Added "Referenced Document" page 7-27. Updated revision publish date only. Added revision history document. chapter v5.1. Minor updates Quartus software version 6.0.0. Realigned figures 6-14. Initial release.
Summary Changes
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