QII51004-7.1.0 This chapter includes Quartus® Support HardCopy® H
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Quartus Support HardCopy Series Devices
QII51004-7.1.0
This chapter includes Quartus® Support HardCopy® HardCopy Stratix® devices. This chapter divided into following sections:
"HardCopy Device Support" page "HardCopy Stratix Device Support" page 4-35
HardCopy Device Support
Altera® HardCopy devices feature 1.2-V, process technology, provide structured ASIC alternative increasingly expensive multi-million gate ASIC designs. HardCopy design methodology offers fast time-to-market schedule, providing ASIC designers with solution long ASIC development cycles. Using Quartus software, leverage Stratix FPGA prototype seamlessly migrate your design HardCopy device production. This document discusses following topics:
"HardCopy Development Flow" page "HardCopy Device Resource Guide" page "HardCopy Recommended Settings Quartus Software" page 4-12 "HardCopy Utilities Menu" page 4-26
more information about HardCopy HardCopy Stratix, HardCopy APEXdevices, refer respective device data sheets HardCopy Series Handbook.
HardCopy Design Benefits
Designing with HardCopy structured ASICs offers substantial benefits over other structured ASIC offerings:
Prototyping using Stratix FPGA functional verification system development reduces total project development time Seamless migration from Stratix FPGA prototype HardCopy device reduces time market risk Unified design methodology Stratix FPGA design HardCopy design reduces need ASIC development software
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up-front development cost HardCopy devices reduces financial risk your project
Quartus Features HardCopy Planning
With Quartus software design HardCopy device using Stratix device prototype. Quartus software contains following expanded features HardCopy device planning:
HardCopy Companion Device Assignment-Identifies compatible HardCopy devices migration with Stratix device currently selected.
This feature constrains pins your Stratix FPGA prototype making compatible with your HardCopy device. also constrains correct resources available HardCopy device making sure that your Stratix FPGA design does become incompatible. addition, still required compile design targeting HardCopy device ensure that design fits, routes, meets timing.
HardCopy Utilities-The HardCopy Utilities functions create overwrites HardCopy companion revisions, change revisions use, compare revisions equivalency. HardCopy Advisor-The HardCopy Advisor helps follow necessary steps successfully submit HardCopy design Altera's HardCopy Design Center.
HardCopy Advisor similar Resource Optimization Advisor Timing Optimization Advisor. HardCopy Advisor provides guidelines follow during development, reporting tasks completed well tasks that remain completed during development.
HardCopy Floorplan-The Quartus software show preliminary floorplan view your HardCopy design's Fitter placement results. HardCopy Design Archiving-The Quartus software archives HardCopy design project's files needed handoff design HardCopy Design Center.
This feature similar Quartus software HardCopy Files Wizard used HardCopy Stratix HardCopy APEX families.
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HardCopy Development Flow
HardCopy Device Preliminary Timing-The Quartus software performs timing analysis HardCopy devices based preliminary timing models Fitter placements. Final timing results HardCopy devices provided HardCopy Design Center. HardCopy Handoff Report-The Quartus software generates handoff report containing information about HardCopy design used HardCopy Design Center design review process. Formal Verification-Cadence Encounter Conformal software perform formal verification between source design files post-compile gate level netlist from HardCopy design.
HardCopy Development Flow
Quartus software, have methods designing your Stratix FPGA HardCopy companion device together Quartus project.
Design HardCopy device first, create Stratix FPGA companion device second build your prototype in-system verification Design Stratix FPGA first create HardCopy companion device second
Both these flows illustrated high level Figure 4-1. added features HardCopy Utilities menu assist completing your HardCopy design submission Altera's HardCopy Design Center back-end implementation.
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Figure 4-1. HardCopy Flow Quartus Software
Prepare Design
Design Stratix First
Design Stratix Second
Select Stratix Device HardCopy Companion Device
Design Stratix First?
Select HardCopy Device Stratix Companion Device
Complete Stratix Device First Flow In-System Verification Stratix FPGA Design Compare Stratix HardCopy Design Revisions
Complete HardCopy Device First Flow
Generate HardCopy Archive
Handoff Design Archive Back-End Migration
Notes Figure 4-1:
Refer Figure page expanded description this process. Refer Figure page expanded description this process.
Designing Stratix FPGA First
HardCopy development flow beginning with Stratix FPGA prototype very similar traditional Stratix FPGA design flow, requires additional tasks performed migrate design HardCopy companion device. design your HardCopy device using Stratix FPGA prototype, complete following tasks:
Specify HardCopy device migration Compile Stratix FPGA design Create compile HardCopy companion revision Compare HardCopy companion revision compilation Stratix device compilation
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HardCopy Development Flow
Figure provides overview highlighting development process designing with Stratix FPGA first creating HardCopy companion device second. Figure 4-2. Designing Stratix Device First Flow
Stratix Prototype Device Development Phase Prepare Stratix Design
Select HardCopy Companion Device
Review HardCopy Advisor
Apply Design Constraints In-System Verification
Compile Stratix Design
Violations?
Violations
Create Overwrite HardCopy Companion Revision HardCopy Companion Device Development Phase Compile HardCopy Companion Revision
Select Larger HardCopy Companion Device?
Fits HardCopy Device?
Compare Stratix HardCopy Revisions
Violations? Design Submission Back-End Implementation Phase Generate Handoff Report
Archive Project Handoff
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Prototype your HardCopy design selecting then compiling Stratix device Quartus software. After compile Stratix design successfully, view HardCopy Device Resource Guide Quartus software Fitter report evaluate which HardCopy devices meet your design's resource requirements. When satisfied with compilation results choice Stratix HardCopy devices, Assignments menu, click Settings. Category list, select Device. Device page, select HardCopy companion device. After select your HardCopy companion device, following:
Review HardCopy Advisor required recommended tasks perform Enable Design Assistant during compilation timing location assignments Compile your Stratix design Create your HardCopy companion revision Compile your design HardCopy companion device HardCopy Utilities compare HardCopy companion device compilation with Stratix FPGA revision Generate HardCopy Handoff Report using HardCopy Utilities Generate HardCopy Handoff Archive using HardCopy Utilities Arrange submission your HardCopy handoff archive Altera's HardCopy Design Center back-end implementation
more information about overall design flow using Quartus software, refer Introduction Quartus manual Altera website www.altera.com.
Designing HardCopy Device First
HardCopy family presents option designing unavailable previous HardCopy families. design your HardCopy device first create your Stratix FPGA prototype second Quartus software. This allows your potential maximum performance HardCopy device immediately during development, create slower performing FPGA prototype design in-system verification. This design process similar traditional HardCopy design flow where build FPGA first, instead, merely change starting device family. remaining tasks complete your design both Stratix HardCopy devices roughly follow
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HardCopy Development Flow
same process (Figure 4-3). HardCopy Advisor adjusts list tasks based which device family start with, Stratix HardCopy help complete process seamlessly. Figure 4-3. Designing HardCopy Device First Flow
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HardCopy Device Resource Guide
HardCopy Device Resource Guide compares resources required successfully compile design with resources available various HardCopy devices. report rates each HardCopy device each device resource well fits design. Quartus software generates HardCopy Device Resource Guide designs successfully compiled Stratix devices. This guide found Fitter folder Compilation Report. Figure shows example HardCopy Device Resource Guide. Refer Table explanation color codes Figure 4-4.
Figure 4-4. HardCopy Device Resource Guide
this report determine which HardCopy device potential candidate migration your Stratix design. HardCopy device package must compatible with Stratix device package. logic
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HardCopy Device Resource Guide
resource usage greater than 100% ratio greater than category indicates that design does that particular HardCopy device.
Table 4-1. HardCopy Device Resource Guide Color Legend Color Package Resource
design migrate Hardcopy package design been fitted with target device migration enabled HardCopy Companion Device dialog box.
Device Resources
resource quantity within range HardCopy device design likely migrate other resources also fit. still required compile HardCopy revision make sure design able route migrate other resources.
Green (High)
design migrate Hardcopy package. However, design been fitted with target device migration enabled HardCopy Companion Device dialog box.
resource quantity within range HardCopy device. However, resource risk exceeding range HardCopy package. your target HardCopy device falls this category, compile your design targeting HardCopy device soon possible check design fits able route migrate other resources. need migrate larger device.
Orange (Medium)
(None)
design cannot migrate Hardcopy package.
resource quantity exceeds range HardCopy device. design cannot migrate this HardCopy device.
Note Table 4-1:
package resource constrained Stratix FPGA which design compiled. Only vertical migration devices within same package able migrate HardCopy devices.
HardCopy architecture consists array fine-grained HCells, which used build logic equivalent Stratix adaptive logic modules (ALMs) digital signal processing (DSP) blocks. blocks HardCopy devices match functionality Stratix blocks, though timing these blocks different than FPGA blocks because they constructed HCell Macros. M-RAM memory blocks HardCopy devices equivalent Stratix memory blocks. Preliminary timing reports HardCopy device available Quartus software. Final timing results HardCopy device provided HardCopy Design Center after back-end migration complete.
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more information about HardCopy device resources, refer Introduction HardCopy Devices Description, Architecture Features chapters HardCopy Device Family Data Sheet HardCopy Series Handbook. report example Figure shows resource comparisons design compiled Stratix EP2S130F1020 device. Based report, HC230F1020 device 1,020-pin FineLine BGA® package appropriate HardCopy device migrate HC230F1020 device specified migration target during compilation, package migration compatibility rated orange, Medium. migration compatibilities other HardCopy devices rated red, None, because package types incompatible with Stratix device. 1,020-pin FBGA HC240 device rated because only compatible with Stratix EP2S180F1020 device. Figure shows report after (unchanged) design recompiled with HardCopy HC230F1020 device specified migration target. HC230F1020 device package migration compatibility rated green, High.
Figure 4-5. HardCopy Device Resource Guide with Target Migration Enabled
HardCopy Companion Device Selection
Quartus software, select HardCopy companion device help structure your design migration from Stratix device HardCopy device. make your HardCopy companion device selection, Assignments menu, click Settings. Settings dialog Category list, select Device (Figure 4-6) select your companion device from Available devices list. Selecting HardCopy Companion device with your Stratix prototype constrains memory blocks, blocks, assignments, that your Stratix HardCopy devices migration-compatible. assignments constrained Stratix design revision that HardCopy device selected
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HardCopy Companion Device Selection
pin-compatible. Quartus software also constrains Stratix design revision does M512 memory blocks exceed number M-RAM blocks HardCopy companion device. Figure 4-6. Quartus Settings Dialog
also specify your HardCopy companion device using following tool command language (Tcl) command: set_global_assignment -name\ <HardCopy Device Part Number> example, select HC230F1020 device your HardCopy companion device EP2S130F1020C4 Stratix FPGA, command set_global_assignment -name\ HC230F1020C
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HardCopy Recommended Settings Quartus Software
HardCopy development flow involves additional planning preparation Quartus software compared standard FPGA design. This because developing your design implemented devices: prototype your design Stratix prototype FPGA, companion revision HardCopy device production. need additional settings constraints make Stratix design compatible with HardCopy device and, some cases, must remove certain settings design. This section explains additional settings constraints necessary your design successful both Stratix FPGA HardCopy structured ASIC devices.
Limit HardCopy Device Resources
Assignments menu, click Settings view Settings dialog box. Category list, select Device. Family list, select Stratix Under Companion device, Limit HardCopy device resources turned default (Figure 4-7). This maintains compatibility between Stratix HardCopy devices ensuring your design does resources Stratix device that available selected HardCopy device. require additional memory blocks blocks debugging purposes using SignalTap® temporarily turn this setting compile verify your design your test environment. However, your final Stratix HardCopy designs submitted Altera back-end migration must compiled with this setting turned
Figure 4-7. Limit HardCopy Device Resources Check
Enable Design Assistant During Compile
must Quartus Design Assistant check HardCopy series designs design rule violations before submitting designs Altera HardCopy Design Center. Additionally, must critical high-level errors. Altera recommends turning Design Assistant automatically during each compile, that during development, violations must fix.
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HardCopy Recommended Settings Quartus Software
more information about Design Assistant rules uses, refer Design Guidelines HardCopy Series Devices chapter HardCopy Series Handbook. enable Design Assistant during compilation, Assignment menu, click Settings. Category list, select Design Assistant turn Design Assistant during compilation (Figure 4-8) entering following command Console: set_global_assignment -name ENABLE_DRC_SETTINGS Figure 4-8. Enabling Design Assistant
Timing Settings
Beginning Quartus Software version 7.1, TimeQuest recommended timing analysis tool designs. Classic Timing Analyzer longer supported HardCopy Design Center will accept designs which Classic Timing Analyzer timing closure. still using Classic Timing Analyzer, Altera strongly recommends that switch TimeQuest.
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more information switch TimeQuest, refer Switching TimeQuest Timing Analyzer chapter Quartus Handbook, volume Altera website www.altera.com.
When specify TimeQuest analyzer timing analysis tool, TimeQuest analyzer guides Fitter analyzes timing results after compilation.
TimeQuest
TimeQuest Timing Analyzer powerful ASIC-style timing analysis tool that validates timing your design using industry-standard constraint, analysis, reporting methodology. TimeQuest Timing Analyzer's command-line interface constrain, analyze, report results timing paths your design. Before running TimeQuest Timing Analyzer, must specify initial timing constraints that describe clock characteristics, timing exceptions, signal transition arrival required times. specify timing constraints Synopsys Design Constraints (SDC) file format using command-line interface. Quartus Fitter optimizes placement logic meet your constraints. During timing analysis, TimeQuest Timing Analyzer analyzes timing paths design, calculates propagation delay along each path, checks timing constraint violations, reports timing results slack Report pane Console pane. TimeQuest Timing Analyzer reports timing violations, customize reporting view precise timing information about specific paths, then constrain those paths correct violations. When your design free timing violations, confident that logic will operate intended target device. TimeQuest Timing Analyzer complete static timing analysis tool that sign-off tool Altera FPGAs structured ASICs.
Setting TimeQuest Timing Analyzer
want TimeQuest timing analysis, from Assignments Quartus software, click Timing Analysis Settings, pop-up window, click TimeQuest Timing Analyzer during compilation tab.
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HardCopy Recommended Settings Quartus Software
following command TimeQuest your timing analysis engine: set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER launch TimeQuest analyzer following modes:
Directly from Quartus software Stand-alone mode Command-line mode
order perform thorough Static Timing Analysis, would need specify timing requirements. most important timing requirements clocks generated clocks, input output delays, false paths multi-cycle paths, minimum maximum delays. TimeQuest, clock latency, recovery removal analysis enabled default.
more information about TimeQuest, refer Quartus TimeQuest Timing Analyzer chapter volume Quartus Handbook Altera website www.altera.com.
Constraints Clock Effect Characteristics
create_clock, create_generated_clock commands create ideal clocks account board effects. order account clock effect characteristics, following commands:
set_clock_latency set_clock_uncertainty more information about these commands, refer Quartus TimeQuest Timing Analyzer chapter volume Quartus Handbook.
Beginning Quartus version 7.1, command derive_clock_uncertainty automatically derive clock uncertainties. This command useful when sure what clock uncertainties might calculated clock uncertainty values based buffer, static phase errors (SPE) jitter PLL's, clock networks, core noises.
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derive_clock_uncertainty command applies inter-clock, intra-clock, interface uncertainties. This command automatically calculates applies setup hold clock uncertainties each clock-to-clock transfer found your design. order interface uncertainty, must create virtual clock, then assign delays input/output ports using set_input_delay set_output_delay commands that virtual clock. These uncertainties applied addition those specified using set_clock_uncertainty command. However, clock uncertainty assignment source destination pair already defined, will ignored. this case, either -overwrite command overwrite previous clock uncertainty command manually remove them using remove_clock_uncertainty command.
syntax derive_clock_uncertainty follows: derive_clock_uncertainty -help] [-long_help] [-dtw] [-overwrite] where arguments listed Table 4-2:
Table 4-2. Arguments derive_clock_uncertainty Option
-help -long_help -dtw -overwrite Short help Long help with examples possible return values Creates PLLJ_PLLSPE_INFO.txt file Overwrites previously performed clock uncertainty assignments
Description
When option used, PLLJ_PLLSPE_INFO.txt file generated. This file lists name PLLs, well their jitter values design. This text file used HCII_DTW_CU_Calculator. When this option used, clock uncertainties calculated.
more information derive_clock_uncertainty command, refer Quartus TimeQuest Timing Analyzer chapter volume Quartus Handbook.
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HardCopy Recommended Settings Quartus Software
Altera strongly recommends that derive_clock_uncertainty command HardCopy revision. HardCopy Design Center will accepting designs that have clock uncertainty constraint either using derive_clock_uncertainty command HardCopy Clock Uncertainty Calculator, then using set_clock_uncertainty command.
more information HardCopy Clock Uncertainty Calculator, refer HardCopy Clock Uncertainty User Guide available Altera website www.altera.com.
Quartus Software Features Supported HardCopy Designs
Quartus software supports optimization features HardCopy prototype development, including:
Physical Synthesis Optimization LogicLock Regions PowerPlay Power Analyzer Incremental Compilation (Synthesis Fitter) Maximum Fan-Out Assignments
Physical Synthesis Optimization
enable Physical Synthesis Optimizations Stratix FPGA revision design, Assignments menu, click Settings. Settings dialog box, Category list, select Fitter Settings. These optimizations migrated into HardCopy companion revision placement timing closure. When designing with HardCopy device first, physical synthesis optimizations enabled HardCopy device, these post-fit optimizations migrated Stratix FPGA revision.
LogicLockRegions
LogicLock Regions Stratix FPGA supported designs migrating HardCopy However, LogicLock Regions passed into HardCopy Companion Revision. LogicLock HardCopy design must create LogicLock Regions HardCopy companion revision. addition, LogicLock Regions HardCopy devices have their properties Auto Size. However, Floating LogicLock regions supported. HardCopy LogicLock Regions must manually sized placed floorplan. When LogicLock Regions created HardCopy device, they start with width height dimensions (1,1), origin coordinates placement X1_Y1 lower left corner
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floorplan. must adjust size location LogicLock Regions created HardCopy device before compiling design.
information about using LogicLock Regions, refer Quartus Analyzing Optimizing Design Floorplan chapter volume Quartus Handbook.
PowerPlay Power Analyzer
perform power estimation analysis your HardCopy Stratix devices using PowerPlay Early Power Estimator. PowerPlay Power Analyzer more accurate estimation your device's power consumption. PowerPlay Early Power Estimator available Quartus software version later. PowerPlay Power Analyzer supports HardCopy devices version later Quartus software.
more information about using PowerPlay Power Analyzer, refer Quartus PowerPlay Power Analysis chapter volume Quartus Handbook Altera website www.altera.com.
Incremental Compilation
Quartus Incremental Compilation Stratix FPGA supported when migrating design HardCopy device. Incremental compilation supported Stratix First design flow HardCopy First design flow. take advantage Quartus Incremental Compilation, organize your design into logical physical partitions synthesis fitting place-and-route). Incremental compilation preserves compilation results performance unchanged partitions your design. This feature dramatically reduces your design iteration time focusing compilations only changed design partitions. compilation results then merged with previous compilation results from unchanged design partitions. also target optimization techniques, such physical synthesis, specific partitions while leaving other partitions untouched. addition, aware following guidelines:
User partitions synthesis results migrated companion device. LogicLock regions suggested user partitions, migrated automatically.
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HardCopy Recommended Settings Quartus Software
first compilation after migration companion device requires full compilation (all partitions compiled), subsequent compilations incremental changes source required. example, phase changes implemented incrementally blocks partitioned. entire design must migrated between Stratix HardCopy companion devices. Quartus software does support migration partitions between companion devices. Bottom-up Quartus Incremental Compilation supported HardCopy devices. Physical Synthesis individual partitions within originating device only. resulting optimizations preserved migration companion device.
information about using Quartus Incremental Compilation, refer Quartus Incremental Compilation Hierarchical Team-Based Design chapter volume Quartus Handbook.
Maximum Fanout Assignments
This feature supported beginning Quartus 6.1. order meet timing, necessary limit number fanouts your design. limit maximum fanout given using this feature. example, following command enable maximum fanout setting: set_instance_assignment -name MAX_FANOUT <number> <net name>
example, want limit maximum fanout called "m3122_combout_1" command follows: set_instance_assignment -name MAX_FANOUT -to\ m3122_combout_1
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Performing ECOs with Quartus Engineering Change Management with Chip Planner
designs grow larger larger density, need analyze design performance, routing congestion, logic placement, executing Engineering Change Orders (ECOs) becomes critical. addition design analysis, various bottom-up top-down flows implement manage design. This becomes difficult manage since ECOs often implemented last minute changes your design.
With Altera Chip Planner tool, shorten design cycle time significantly. When changes made your design ECOs, have perform full compilation Quartus software. Instead, would make changes directly post place-and-route netlist, generate programming file, test revised design performing gate-level simulation timing analysis, proceed verify system using Stratix FPGA prototype). Once been verified Stratix FPGA, switch HardCopy revision, apply same ECOs, timing analyzer assembler, perform revision compare then HardCopy Netlist Writer design submission. There three scenarios from migration point view:
There changes which one-to-one (that same change implemented each architecture-Stratix FPGA HardCopy II). There changes that must implemented differently architectures achieve same result. There some changes that cannot implemented both architectures.
following sections outline methods migrating each these types changes.
Migrating One-to-One Changes
One-to-one changes implemented using identical commands both architectures. general, such changes include those that affect only cells cells. Some examples one-to-one changes changes such creating, deleting moving pins, changing properties, changing connectivity (provided source destination connectivity changes I/Os PLLs). These implemented identically both architectures. such changes exported Tcl, direct reapplication generated script (with minor text edit) companion revision should implement appropriate changes follows:
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Performing ECOs with Quartus Engineering Change Management with Chip Planner
Export changes from Change Manager Tcl. Open generated script, change line "project_open <project> -revision <revision>" refer appropriate companion revision. Apply script companion revision.
partial list examples this type follows:
creation, deletion, moves property changes (for example, standards, delay chain settings, etc.) property changes Connectivity changes between non-LCELL_COMB atoms (for example, I/O, I/O, etc.)
Migrating Changes that Must Implemented Differently
Some changes must implemented differently architectures. Changes affecting logic design fall into this category. Examples LUTMASK changes, LC_COMB/HSADDER creation deletion, connectivity changes covered previous section. Another example this would have different settings Stratix HardCopy revisions.
more information about different settings Stratix HardCopy Devices, refer AN432: Using Different Settings Between Stratix HardCopy Devices. Table summarizes suggested implementation various changes.
Table 4-3. Implementation Suggestions Various Changes (Part Change Type
LUTMASK changes
Suggested Implementation
Because single Stratix atom require multiple HardCopy atoms implement, necessary change multiple HardCopy atoms implement change, including adding modifying connectivity using Stratix LC_COMB extended mode (7-LUT) using SHARE chain, must create multiple atoms implement same logic functions HardCopy Additionally, placement LC_COMB cell meaning companion revision underlying resources different.
Make/Delete LC_COMB
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Table 4-3. Implementation Suggestions Various Changes (Part Change Type
Make/Delete LC_FF
Suggested Implementation
basic creation deletion same both architectures. However, with LC_COMB creation deletion, location LC_FF HardCopy revision meaning Stratix revision vice versa. Because Stratix LCELL_COMB atom have broken into several HardCopy LCELL_COMB atoms, source destination ports connectivity changes need analyzed properly implement change companion revision.
Editing Logic Connectivity
Changes that Cannot Migrated
small changes cannot implemented other architecture because they make sense other architecture. best example this occurs when moving logic design; because logic fabric different between architectures, locations Stratix make sense HardCopy vice versa.
Overall Migration Flow
This section outlines migration flow suggested procedure implementing changes both revisions ensure successful Revision Compare such that design submitted HardCopy Design Center.
Preparing Revisions
general procedure migrating changes between devices same, whether going from Stratix HardCopy vice versa. major steps follows: Compile design initial device. Migrate design from initial device target device companion revision. Compile companion revision. Perform Revision Compare operation. revisions should pass Revision Compare.
testing identifies problems requiring changes, equivalent changes applied both Stratix HardCopy revisions, described next section.
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Overall Migration Flow
Applying Changes
general flow applying equivalent changes companion revisions follows: Make changes revision using Chip Planner tools (Chip Planner, Resource Property Editor, Change Manager), then verify export these changes. procedure doing this follows: Make changes using Chip Planner tool. Perform netlist check using Check Save Netlist Changes command. Verify correctness using timing analysis, simulation, prototyping (Stratix only). more changes required, repeat steps a-b. Export change records from Change Manager scripts, .csv .txt file formats. This exported file used assist making equivalent changes companion revision. Open companion revision Quartus software.
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Using exported file, manually reapply changes using Chip Planner tool. stated previously, some changes reapplied directly companion revision (either manually applying commands), while others require some modifications.
Perform Revision Compare operation. revisions should match once again. Verify correctness changes (you need timing analysis). HardCopy Assembler HardCopy Netlist Writer design submission along with handoff files.
command running HardCopy Assembler follows: execute_module -tool -args "-read_settings_files=\ -write_settings_files=off" command HardCopy Netlist Writer follows: execute_module -tool -args "-generate_hardcopyii_files"\
more information about using Chip Planner, refer Quartus Engineering Change Management with Chip Planner chapter volume Quartus Handbook www.altera.com. Third-party formal verification software available your HardCopy design. Cadence Encounter Conformal verification software used Stratix HardCopy families, well several other Altera product families. Conformal software with Quartus software project your Stratix HardCopy design revisions, must enable Netlist Writer. necessary turn Netlist Writer generate necessary netlists command files needed Conformal software. automatically Netlist Writer during compile your Stratix HardCopy design revisions, perform following steps: Assignment menu, click Tool Settings. Settings dialog displays.
Formal Verification Stratix HardCopy Revisions
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Formal Verification Stratix HardCopy Revisions
Tool Settings list, select Formal Verification, Tool name list, select Conformal LEC. Compile your Stratix Hardcopy design revisions, with both Tool Settings Conformal turned Netlist Writer automatically runs.
Quartus Netlist Writer produces netlist Stratix when that revision, generates second netlist when runs HardCopy revision. compare your Stratix post-compile netlist your source code using scripts generated Netlist Writer. Similarly, compare your HardCopy post-compile netlist your source code with scripts provided Netlist Writer.
more information about using Cadence Encounter Conformal verification software, refer Cadence Encounter Conformal Support chapter volume Quartus Handbook.
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HardCopy Utilities Menu
HardCopy Utilities menu Quartus software shown Figure 4-9. access this menu, Project menu, click HardCopy Utilities. This menu contains main functions develop your HardCopy design Stratix FPGA prototype companion revision. From HardCopy Utilities menu, can:
Create update HardCopy companion revisions which HardCopy companion revision current revision Generate HardCopy Handoff Report design reviews Archive HardCopy Handoff Files submission HardCopy Design Center Compare companion revisions functional equivalence Track your design progress using HardCopy Advisor
Figure 4-9. HardCopy Utilities Menu
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HardCopy Utilities Menu
Each features within HardCopy Utilities summarized Table 4-4. process using each these features explained following sections.
Table 4-4. HardCopy Utilities Menu Options Menu Description Applicable Design Revision
Stratix prototype design HardCopy Companion Revision
Restrictions
Must disable Auto Device selection Must Stratix device HardCopy companion device
Create companion Create/Overwrite revision update existing HardCopy Companion Revision companion revision your Stratix HardCopy design. Specify which companion Current revision associate with HardCopy Companion Revision current design revision. Compare HardCopy Companion Revisions
Companion Revision must Stratix prototype design HardCopy already exist Companion Revision
Compilation both revisions Compares Stratix design Stratix prototype revision with HardCopy design HardCopy must complete Companion Revision companion design revision generates report.
Generate report containing Stratix prototype Generate HardCopy Handoff important design information design HardCopy files messages generated Companion Revision Report Quartus compile Archive HardCopy Handoff Files Generate Quartus Archive HardCopy File specifically submitting Companion Revision design HardCopy Design Center. Similar HardCopy Files Wizard HardCopy Stratix APEX.
Compilation both revisions must complete Compare HardCopy Companion Revisions must have been executed Compilation both revisions must completed Compare HardCopy Companion Revisions must have been executed Generate HardCopy Handoff Report must have been executed
HardCopy Advisor
None Open Advisor, similar Stratix prototype design HardCopy Resource Optimization Companion Revision Advisor, helping through steps creating HardCopy project.
Companion Revisions
HardCopy designs follow different development flow Quartus software compared with previous HardCopy families. create multiple revisions your Stratix prototype design, also create separate revisions your design HardCopy device. Quartus software creates specific HardCopy design
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revisions project conjunction regular project revisions. These parallel design revisions HardCopy devices called companion revisions. Although create multiple project revisions, Altera recommends that maintain only Stratix FPGA revision once have created HardCopy companion revision.
When have successfully compiled your Stratix prototype FPGA, create HardCopy companion revision your design proceed with compiling HardCopy companion revision. create companion revision, Project menu, point HardCopy Utilities click Create/Overwrite HardCopy Companion Revision. dialog create companion revision overwrite existing companion revision (Figure 4-10). Figure 4-10. Create Overwrite HardCopy Companion Revision
associate only Stratix revision HardCopy companion revision. created more than revision more than companion revision, current companion revision working Project menu, point HardCopy Utilities click Current HardCopy Companion Revision (Figure 4-11). Figure 4-11. Current HardCopy Companion Revision
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HardCopy Utilities Menu
Compiling HardCopy Companion Revision
Quartus software allows compile your HardCopy design with preliminary timing information. timing constraints HardCopy companion revision same Stratix design used create revision. Quartus software contains preliminary timing models HardCopy devices gauge much performance improvement achieve HardCopy device compared Stratix FPGA. Altera verifies that HardCopy Companion Device timing requirements HardCopy Design Center. After create your HardCopy companion revision from your compiled Stratix design, select companion revision Quartus software design revision drop-down (Figure 4-12) from Revisions list. Compile HardCopy companion revision. After Quartus software compiles your design, perform comparison check HardCopy companion revision Stratix prototype revision. Figure 4-12. Changing Current Revision
Comparing HardCopy Stratix Companion Revisions
Altera uses companion revisions single Quartus project maintain seamless migration your design from Stratix FPGA HardCopy structured ASIC. This methodology allows design with Register Transfer Level (RTL) code used both Stratix FPGA HardCopy structured ASIC, guaranteeing functional equivalency. When making changes companion revisions, Compare HardCopy Companion Revisions feature ensure that your Stratix design matches your HardCopy design functionality compilation settings. compare companion revisions, Project menu, point HardCopy Utilities click Compare HardCopy Companion Revisions. must perform this comparison after both Stratix HardCopy designs compiled order hand design Altera's HardCopy Design Center.
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Comparison Revision Summary found Compilation Report identifies where assignments were changed between revisions there change logic resource count different compilation settings.
Generate HardCopy Handoff Report
order submit design HardCopy Design Center, must generate HardCopy Handoff Report providing important information about design that want HardCopy Design Center review. generate HardCopy Handoff Report, must:
Successfully compile both Stratix HardCopy revisions your design Successfully Compare HardCopy Companion Revisions utility
Once generate HardCopy Handoff Report, archive design using Archive HardCopy Handoff Files utility described "Archive HardCopy Handoff Files" page 4-30.
Archive HardCopy Handoff Files
last step HardCopy design methodology archive HardCopy project submission HardCopy Design Center back-end migration. HardCopy archive utility creates different Quartus Archive File than standard Quartus project archive utility generates. This archive contains only necessary data from Quartus project needed implement design HardCopy Design Center. order Archive HardCopy Handoff Files utility, must complete following:
Compile both Stratix HardCopy revisions your design Compare HardCopy Revisions utility Generate HardCopy Handoff Report
select this option, Project menu, point HardCopy Utilities click Archive HardCopy Handoff File utility.
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HardCopy Utilities Menu
HardCopy Advisor
HardCopy Advisor provides list tasks should follow develop your Stratix prototype your HardCopy design. HardCopy Advisor, Project menu, point HardCopy Utilities click HardCopy Advisor. following list highlights checkpoints that HardCopy Advisor reviews. This list includes major check points design process; does show every step process completing your Stratix HardCopy designs: Select Stratix device. Select HardCopy device. Turn Design Assistant. timing constraints. Check incompatible assignments. Compile check Stratix design. Create overwrite companion revision. Compile check HardCopy companion results. Compare companion revisions.
Generate Handoff Report. Archive Handoff Files send Altera. HardCopy Advisor shows necessary steps that pertain your current selected device. Advisor shows slightly different view design with Stratix selected compared design with HardCopy selected. Quartus software, start designing with HardCopy device selected first, build Stratix companion revision second. When this approach, HardCopy Advisor task list adjusts automatically guide from HardCopy development through Stratix FPGA prototyping, then completes comparison archiving handoff Altera. When your design uses Stratix FPGA your starting point, Altera recommends following Advisor guidelines your Stratix FPGA until complete prototype revision.
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When Stratix FPGA design complete, create switch your HardCopy companion revision follow Advisor steps shown that revision until finished with HardCopy revision ready submit design Altera back-end migration. Each category HardCopy Advisor list explanation recommended settings constraints, well quick links features Quartus software that needed each section. HardCopy Advisor displays:
green check when have successfully completed steps yellow caution sign steps that must completed before submitting your design Altera HardCopy development information callout items must verify Selecting item within HardCopy flow menu provides description task recommended action. view HardCopy Advisor differs depending device select.
Figure 4-13 shows HardCopy Advisor with Stratix device selected. Figure 4-13. HardCopy Advisor with Stratix Selected
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HardCopy Utilities Menu
Figure 4-14 shows HardCopy Advisor with HardCopy device selected. Figure 4-14. HardCopy Advisor with HardCopy Device Selected
HardCopy Floorplan View
Quartus software displays preliminary timing closure floorplan placement your HardCopy companion revision. This floorplan shows preliminary placement connectivity pins, PLLs, memory blocks, HCell macros, HCell macros. Congestion mapping routing connections viewed using Layers Setting dialog View menu) settings. This useful analyzing densely packed areas your floorplan that could reducing peak performance your design. HardCopy Design Center verifies final HCell macro timing placement guarantee timing closure achieved.
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Figure 4-15 shows example HC230F1020 device floorplan. Figure 4-15. HC230F1020 Device Floorplan
this small example design, logic placed near bottom edge. placement block constructed HCell Macros, various logic HCell Macros, memory block. labeled close-up view this region shown Figure 4-16. Figure 4-16. Close-Up View Floorplan
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HardCopy Stratix Device Support
HardCopy Design Center performs final placement timing closure your HardCopy design based timing constraints provided Stratix design.
more information about HardCopy Design Center's process, refer Back-End Design Flow HardCopy Series Devices chapter volume HardCopy Series Device Handbook. Altera HardCopy devices provide comprehensive alternative ASICs. HardCopy structured ASICs offer complete solution from prototype high-volume production, maintain powerful features high-performance architecture their equivalent FPGAs with programmability removed. Quartus design software design HardCopy devices manner similar traditional ASIC design flow prototype with Altera's high density Stratix, APEX 20KC, APEX 20KE FPGAs before seamlessly migrating corresponding HardCopy device high-volume production. HardCopy structured ASICs provide following benefits:
HardCopy Stratix Device Support
Improves performance, average, over corresponding speed grade FPGA device Lowers power consumption, average, over corresponding FPGA Preserves FPGA architecture features minimizes risk Guarantees first-silicon success through proven, seamless migration process from FPGA equivalent HardCopy device Offers quick turnaround FPGA design structured ASIC device-samples available about eight weeks
Altera's Quartus software built-in support HardCopy Stratix devices. HardCopy design flow Quartus software offers following advantages:
Unified design flow from prototype production Performance estimation HardCopy Stratix device allows design systems maximum throughput Easy-to-use inexpensive design tools from single vendor integrated design methodology that enables system-on-a-chip designs
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This section discusses following areas:
design HardCopy Stratix HardCopy APEX structured ASICs using Quartus software explanation what HARDCOPY_FPGA_PROTOTYPE devices target designs these devices Performance power estimation HardCopy Stratix devices generate HardCopy design database submitting HardCopy Stratix HardCopy APEX designs HardCopy Design Center
Features
Beginning with version 4.2, Quartus software contains several powerful features that facilitate design HardCopy Stratix HardCopy APEX devices:
HARDCOPY_FPGA_PROTOTYPE Devices These virtual Stratix FPGA devices with features identical HardCopy Stratix devices. must these FPGA devices prototype your designs verify functionality silicon. HardCopy Timing Optimization Wizard Using this feature, target your design HardCopy Stratix devices, providing estimate design's performance HardCopy Stratix device. HardCopy Stratix Floorplans Timing Models Quartus software supports post-migration HardCopy Stratix device floorplans timing models facilitates design optimization design performance. Placement Constraints Location LogicLock constraints supported HardCopy Stratix floorplan level improve overall performance. Improved Timing Estimation Beginning with version 4.2, Quartus software determines routing associated buffer insertion HardCopy Stratix designs, provides Timing Analyzer with more accurate information about delays than possible previous versions Quartus software. Quartus Archive File automatically receives buffer insertion information, which greatly enhances timing closure process back-end migration your HardCopy Stratix device. Design Assistant
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HARDCOPY_FPGA_PROTOTYPE, HardCopy Stratix Stratix Devices
This feature checks your design compliance with HardCopy device design rules establishes seamless migration path quickest time.
HardCopy Files Wizard This wizard allows deliver Altera design database deliverables required migration. This feature used HardCopy Stratix HardCopy APEX devices.
HardCopy Stratix HardCopy APEX PowerPlay Early Power Estimator available Altera website www.altera.com. must HARDCOPY_FPGA_PROTOTYPE virtual devices available Quartus software target your designs actual resources package options available equivalent post-migration HardCopy Stratix device. programming file generated HARDCOPY_FPGA_PROTOTYPE used corresponding Stratix FPGA device. purpose HARDCOPY_FPGA_PROTOTYPE guarantee seamless migration HardCopy making sure that your design only uses resources FPGA that used HardCopy device after migration. equivalent Stratix FPGAs verify design's functionality in-system, then generate design database necessary migrate HardCopy device. This process ensures seamless migration design from prototyping device production device high volume. also minimizes risk, assures samples about eight weeks, guarantees first-silicon success. HARDCOPY_FPGA_PROTOTYPE devices only available HardCopy Stratix devices available HardCopy HardCopy APEX device families.
HARDCOPY_FPGA _PROTOTYPE, HardCopy Stratix Stratix Devices
Table compares HARDCOPY_FPGA_PROTOTYPE devices, Stratix devices, HardCopy Stratix devices.
Table 4-5. Qualitative Comparison HARDCOPY_FPGA_PROTOTYPE Stratix HardCopy Stratix Devices (Part Stratix Device
FPGA FPGA
HARDCOPY_FPGA_PROTOTYPE Device
Virtual FPGA Architecture identical Stratix FPGA
HardCopy Stratix Device
Structured ASIC Architecture identical Stratix FPGA
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Table 4-5. Qualitative Comparison HARDCOPY_FPGA_PROTOTYPE Stratix HardCopy Stratix Devices (Part Stratix Device
FPGA Ordered through Altera part number
HARDCOPY_FPGA_PROTOTYPE Device
Resources identical HardCopy Stratix device Cannot ordered, Altera Stratix FPGA part number
HardCopy Stratix Device
M-RAM resources different than Stratix FPGA some devices Ordered Altera part number
Table lists resources available each HardCopy Stratix devices.
Table 4-6. HardCopy Stratix Device Physical Resources Device
HC1S25F672 HC1S30F780 HC1S40F780 HC1S60F1020 HC1S80F1020
25,660 32,470 41,250 57,120 79,040
ASIC Equivalent Gates
M512 Blocks
Blocks
M-RAM Blocks
Blocks
PLLs
Maximum User Pins
Notes Table 4-6:
Combinational registered logic include blocks, on-chip RAM, PLLs. M-RAM resources these HardCopy devices differ from corresponding Stratix FPGA.
given device, number available M-RAM blocks HardCopy Stratix devices identical with corresponding HARDCOPY_FPGA_PROTOTYPE devices, different from corresponding Stratix devices. Maintaining identical resources between HARDCOPY_FPGA_PROTOTYPE HardCopy Stratix devices facilitates seamless migration from FPGA structured ASIC device.
more information about HardCopy Stratix devices, refer HardCopy Stratix Device Family Data Sheet section volume HardCopy Series Handbook. three devices, Stratix FPGA, HARDCOPY_FPGA_PROTOTYPE, HardCopy device, distinct devices Quartus software. HARDCOPY_FPGA_PROTOTYPE programming files used Stratix FPGA your design. three devices tied together with same netlist, thus single SRAM Object File (.sof) used achieve various goals each stage. same SRAM Object File generated
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HARDCOPY_FPGA_PROTOTYPE, HardCopy Stratix Stratix Devices
HARDCOPY_FPGA_PROTOTYPE design, used program Stratix FPGA device, same that used generate HardCopy Stratix device, guaranteeing seamless migration.
more information about SRAM Object File programming Stratix FPGA devices, refer Programming Configuration chapter Introduction Quartus Manual.
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HardCopy Design Flow
Figure 4-17 shows HardCopy design flow diagram. design steps explained detail following sections this chapter. HardCopy Stratix design flow utilizes HardCopy Timing Optimization Wizard automate migration process into one-step process. remainder this section explains tasks performed this automated process. detailed description HardCopy Timing Optimization Wizard HardCopy Files Wizard, refer "HardCopy Timing Optimization Wizard" page 4-43 "Generating HardCopy Design Database" page 4-54.
Figure 4-17. HardCopy Stratix HardCopy APEX Design Flow Diagram
Start Quartus HardCopy Flow Stratix APEX
Select FPGA Family
Select Stratix HARDCOPY_FPGA_PROTOTYPE Device
Step Process
Select APEX FPGA Device Supported HardCopy APEX
Compile
Step Process
Compile
Compile
Mirgrate Compiled Project Migrate Only
Migrate Compiled Project
Migrate Compiled Project
Close Quartus FPGA Project
Close Quartus FPGA Project
Close Quartus FPGA Project
Open Quartus HardCopy Project
Open Quartus HardCopy Project
Open Quartus HardCopy Project
Compile HardCopy Stratix Device (Actual HardCopy Floorplan)
Compile HardCopy Stratix Device (Actual HardCopy Floorplan)
Compile HardCopy Stratix Device (Actual HardCopy Floorplan) HardCopy Files Wizard (Quartus Archive File delivery Altera)
Placement Info HardCopy
Notes Figure 4-17:
Migrate-Only Process: displayed flow completed manually. Two-Step Process: Migration Compilation done automatically (shaded area). One-Step Process: Full HardCopy Compilation. entire process completed automatically (shaded area).
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HardCopy Design Flow
Design Flow Steps One-Step Process
following sections describe each step full HardCopy compilation (the Step Process), shown Figure 4-17.
Compile Design FPGA
This step compiles design HARDCOPY_FPGA_PROTOTYPE device gives resource utilization performance FPGA.
Migrate Compiled Project
This step generates Quartus Project File (.qpf) other files required HardCopy implementation. Quartus software also assigns appropriate HardCopy Stratix device design migration.
Close Quartus FPGA Project
Because must compile project HardCopy Stratix device, must close existing project which have targeted your design HARDCOPY_FPGA_PROTOTYPE device.
Open Quartus HardCopy Project
Open Quartus project that created "Migrate Compiled Project" step. selected device devices from HardCopy Stratix family that assigned during that step.
Compile HardCopy Stratix Device
Compile design HardCopy Stratix device. After successful compilation, Timing Analysis section compilation report shows performance design implemented HardCopy device.
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Design HardCopy Stratix Devices
This section describes process designing HardCopy Stratix device using HARDCOPY_FPGA_PROTOTYPE your initial selected device. order HardCopy Timing Optimization Wizard, must first design with HARDCOPY_FPGA_PROTOTYPE order design migrate HardCopy Stratix device. target design HardCopy Stratix device Quartus software, follow these steps: have done create project open existing project. Assignments menu, click Settings. Category list, select Device. Device page, Family list, select Stratix. Select desired HARDCOPY_FPGA_PROTOTYPE device Available Devices list (Figure 4-18).
Figure 4-18. Selecting HARDCOPY_FPGA_PROTOTYPE Device
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Design HardCopy Stratix Devices
choosing HARDCOPY_FPGA_PROTOTYPE device, design information, available resources, package option, assignments constrained guarantee seamless migration your project HardCopy Stratix device. netlist resulting from HARDCOPY_FPGA_PROTOTYPE device compilation contains information about electrical connectivity, resources used, placements, unused resources FPGA device. Assignments menu, click Settings. Category list, select HardCopy Settings specify input transition timing modeled both clock data input pins. These transition times used static timing analysis during back-end timing closure HardCopy device. constraints your HARDCOPY_FPGA_PROTOTYPE device, Processing menu, click Start Compilation compile design.
HardCopy Timing Optimization Wizard
After have successfully compiled your design HARDCOPY_FPGA_PROTOTYPE, must migrate design HardCopy Stratix device performance estimation HardCopy Stratix device. This migration required before submitting design Altera HardCopy Stratix device implementation. perform required migration, Project menu, point HardCopy Utilities click HardCopy Timing Optimization Wizard. this point, presented with following three choices target designs HardCopy Stratix devices (Figure 4-19):
Migration Only: select this option after compiling HARDCOPY_FPGA_PROTOTYPE project migrate project HardCopy Stratix project. perform following tasks manually target design HardCopy Stratix device. Refer to"Performance Estimation" page 4-46 additional information about perform these tasks. Close existing project Open migrated HardCopy Stratix project Compile HardCopy Stratix project HardCopy Stratix device
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Migration Compilation: select this option after compiling project. This option results following actions: Migrating project HardCopy Stratix project Opening migrated HardCopy Stratix project compiling project HardCopy Stratix device Full HardCopy Compilation: Selecting this option results following actions: Compiling existing HARDCOPY_FPGA_PROTOTYPE project Migrating project HardCopy Stratix project Opening migrated HardCopy Stratix project compiling HardCopy Stratix device
Figure 4-19. HardCopy Timing Optimization Wizard Options
main benefit HardCopy Timing Wizard's three options flexibility conversion process automation. first time migrate your HARDCOPY_FPGA_PROTOTYPE project HardCopy Stratix device, want Migration Only, then work HardCopy Stratix project Quartus software. your prototype FPGA project HardCopy Stratix project constraints stabilize have fewer changes, Full HardCopy Compilation ideal one-click compiling your HARDCOPY_FPGA_PROTOTYPE HardCopy Stratix projects.
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Design HardCopy Stratix Devices
After selecting wizard want run, "HardCopy Timing Optimization Wizard: Summary" page shows details about settings made Wizard, shown Figure 4-20. Figure 4-20. HardCopy Timing Optimization Wizard Summary Page
When either second options Figure 4-19 selected (Migration Compilation Full HardCopy Compilation), designs targeted HardCopy Stratix devices optimized using HardCopy Stratix placement timing analysis estimate performance. details performance optimization estimation steps, refer "Performance Estimation" page 4-46. performance requirement met, modify your source, optimize FPGA design, estimate timing until reach timing closure.
Support HardCopy Migration
complement features HardCopy migration, Quartus software provides following command-line executables (which provide tool command language (Tcl) shell -flow command) migrate HARDCOPY_FPGA_PROTOTYPE project HardCopy Stratix devices: quartus_sh -flow migrate_to_hardcopy <project_name> <revision>] This command migrates project compiled HARDCOPY_FPGA_PROTOTYPE device HardCopy Stratix device. quartus_sh -flow hardcopy_full_compile <project_name> <revision>]
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This command performs following tasks:
Compiles exsisting project HARDCOPY_FPGA_PROTOTYPE device. Migrates project HardCopy Stratix project. Opens migrated HardCopy Stratix project compiles HardCopy Stratix device.
Design Optimization Performance Estimation
HardCopy Timing Optimization Wizard creates HardCopy Stratix project Quartus software, where perform design optimization performance estimation your HardCopy Stratix device.
Design Optimization
Beginning with version 4.2, Quartus software supports HardCopy Stratix design optimization providing floorplans placement optimization HardCopy Stratix timing models. These features allows refine placement logic array blocks (LAB) optimize HardCopy design further than FPGA performance. Customized routing buffer insertion done Quartus software then used estimate design's performance migrated device. HardCopy device floorplan, routing, timing estimates Quartus software reflect actual placement design HardCopy Stratix device, used available resources, location resources actual device.
Performance Estimation
Figure 4-21 illustrates design flow estimating performance optimizing your design. target your designs HARDCOPY_FPGA_PROTOTYPE devices, migrate design HardCopy Stratix device, placement optimization timing estimation your HardCopy Stratix device. event that required performance met, can:
Work improve placement HardCopy Stratix project.
back HARDCOPY_FPGA_PROTOTYPE project optimize that design, modify your source code, repeat migration HardCopy Stratix device, perform optimization timing estimation steps.
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Design Optimization Performance Estimation
average, HardCopy Stratix devices faster than equivalent speed grade Stratix FPGA device. These performance numbers highly design dependent, must obtain final performance numbers from Altera.
Figure 4-21. Obtaining HardCopy Performance Estimation
Proven Netlist, Assignments, Timing Constraints HardCopy Placement Stratix FPGA Timing Analysis Proven Netlist Timing Placement Constraint
Timing Met?
HardCopy Stratix
perform Timing Analysis HardCopy Stratix device, follow these steps: Open existing project compiled HARDCOPY_FPGA_PROTOYPE device. Project menu, point HardCopy Utilities click HardCopy Timing Optimization Wizard. Select destination directory migrated project complete HardCopy Timing Optimization Wizard process. completion HardCopy Timing Optimization Wizard, destination directory created contains Quartus project file, files required HardCopy Stratix implementation. this stage, design copied from HARDCOPY_FPGA_PROTOTYPE project directory directory perform timing analysis. This two-project directory structure enables move back forth between HARDCOPY_FPGA_PROTOTYPE design database HardCopy Stratix design database. Quartus software creates <project name>_hardcopy_optimization directory. have select HardCopy Stratix device while performing performance estimation. When HardCopy Timing Optimization Wizard, Quartus software selects HardCopy Stratix device corresponding specified HARDCOPY_FPGA_PROTOTYPE FPGA. Thus, information necessary HardCopy Stratix device available from earlier HARDCOPY_FPGA_PROTOTYPE device selection.
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constraints related design also transferred project directory. modify these constraints, necessary, your optimized design environment achieve necessary timing closure. However, design optimized HARDCOPY_FPGA_PROTOTYPE device level modifying code device constraints, must migrate project with HardCopy Timing Optimization Wizard. existing project directory selected when HardCopy Timing Optimization Wizard run, existing information overwritten with compile results. project directory directory that chose migrated project. snapshot files inside <project name>_hardcopy_optimization directory shown Table 4-7.
Table 4-7. Directory Structure Generated HardCopy Timing Optimization Wizard
<project name>_hardcopy_optimization\ <project name>.qsf <project name>.qpf <project name>.sof <project name>.macr <project name>.gclk hardcopy_fpga_prototype\ fpga_<project name>_violations.datasheet fpga_<project name>_target.datasheet fpga_<project name>_rba_pt_hcpy_v.tcl fpga_<project name>_pt_hcpy_v.tcl fpga_<project name>_hcpy_v.sdo fpga_<project name>_hcpy.vo fpga_<project name>_cpld.datasheet fpga_<project name>_cksum.datasheet fpga_<project name>.tan.rpt fpga_<project name>.map.rpt fpga_<project name>.map.atm fpga_<project name>.fit.rpt fpga_<project name>.db_info fpga_<project name>.cmp.xml fpga_<project name>.cmp.rcf fpga_<project name>.cmp.atm fpga_<project name>.asm.rpt fpga_<project name>.qarlog fpga_<project name>.qar fpga_<project name>.qsf fpga_<project name>.pin fpga_<project name>.qpf db_export\ <project name>.map.atm <project name>.map.hdbx <project name>.db_info
Open migrated Quartus project created Step
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Design Optimization Performance Estimation
Perform full compilation. After successful compilation, Timing Analysis section Compilation Report shows performance design.
Performance estimation supported HardCopy APEX devices Quartus software. Your design optimized modifying code FPGA design constraints. should contact Altera discuss desired performance improvements with HardCopy APEX devices.
Buffer Insertion
Beginning with version 4.2, Quartus software provides improved HardCopy Stratix device timing closure estimation, more accurately reflect results expected after back-end migration. Quartus software performs necessary buffer insertion your HardCopy Stratix device during Fitter process, stores location these buffers necessary routing information Quartus Archive File. This buffer insertion improves estimation Quartus Timing Analyzer HardCopy Stratix device.
Placement Constraints
Beginning with version 4.2, Quartus software supports placement constraints LogicLock regions HardCopy Stratix devices. Figure 4-22 shows iterative process modify placement constraints until best placement HardCopy Stratix device achieved.
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Figure 4-22. Placement Constraints Flow HardCopy Stratix Devices
Compile Design HARDCOPY_FPGA_PROTOTYPE
Migrate HardCopy Stratix Device Using HardCopy Timing Optimization Wizard
Add/Update Placement Constraints
Add/Update LogicLock Constraints Compile HardCopy Stratix Device
Performance Met?
Generate HardCopy Files
Location Constraints
This section provides information about HardCopy Stratix logic location constraints.
Assignments
Logic placement HardCopy Stratix limited placement optimization interconnecting signals between them. Stratix FPGA, individual logic elements (LE) placed Quartus Fitter into LABs. HardCopy Stratix migration process requires that contents cannot change after Timing Optimization Wizard task done. Therefore, only make LAB-level placement optimization location assignments after migrating HARDCOPY_FPGA_PROTOTYPE project HardCopy Stratix device.
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Location Constraints
Quartus software supports these location constraints HardCopy Stratix devices. entire contents moved empty when using location assignments. want move logic contents entire contents moved empty example, logic contents LAB_X33_Y65 moved empty LAB_X43_Y56 individual logic cell LC_X33_Y65_N1 moved itself HardCopy Stratix Timing Closure Floorplan.
LogicLock Assignments
LogicLock feature Quartus software provides block-based design approach. Using this technique partition your design create each block logic independently, optimize placement area, integrate blocks into level design.
learn more about this methodology, refer Quartus Analyzing Optimizing Design Floorplan chapter volume Quartus Handbook. LogicLock constraints supported when migrate project from HARDCOPY_FPGA_PROTOTYPE project HardCopy Stratix project. LogicLock region specified "Size=Fixed" "Location=Locked" HARDCOPY_FPGA_PROTOTYPE project, converted have "Size=Auto" "Location=Floating" shown following LogicLock examples. This modification necessary because floorplan HardCopy Stratix device different from that Stratix device, assigned coordinates HARDCOPY_FPGA_PROTOTYPE match HardCopy Stratix floorplan. this modification occur, LogicLock assignments would lead incorrect placement Quartus Fitter. Making regions auto-size floating, maintains your LogicLock assignments, allowing easily adjust LogicLock regions required lock their locations again after HardCopy Stratix placement. Example Example show examples LogicLock assignments.
Example 4-1. LogicLock Region Definition HARDCOPY_FPGA_PROTOTYPE Quartus Settings File set_global_assignment -name LL_HEIGHT -entity risc8 -section_id test set_global_assignment -name LL_WIDTH -entity risc8 -section_id test set_global_assignment -name LL_STATE LOCKED -entity risc8 -section_id test set_global_assignment -name LL_AUTO_SIZE -entity risc8 -section_id test
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Example 4-2. LogicLock Region Definition Migrated HardCopy Stratix Quartus Settings File set_global_assignment -name LL_HEIGHT -entity risc8 -section_id test set_global_assignment -name LL_WIDTH -entity risc8 -section_id test set_global_assignment -name LL_STATE FLOATING -entity risc8 -section_id test set_global_assignment -name LL_AUTO_SIZE -entity risc8 -section_id test
Checking Designs HardCopy Design Guidelines
When develop design with HardCopy migration mind, must follow Altera-recommended design practices that ensure straightforward migration process design will able implemented HardCopy device. Prior starting migration design HardCopy device, must review design identify address design issues. design issues that have been addressed jeopardize silicon success.
Altera-Recommended Coding Guidelines
Designing Altera PLD, FPGA, HardCopy structured ASIC devices requires certain specific design guidelines hardware description language (HDL) coding style recommendations followed.
more information about design recommendations coding styles, refer Design Guidelines section volume Quartus Handbook.
Design Assistant
Quartus software includes Design Assistant feature check your design against HardCopy design guidelines. Some design rule checks performed Design Assistant include following rules:
Design should contain combinational loops Design should contain delay chains Design should contain latches
Design Assistant, must Analysis Synthesis design Quartus software. Altera recommends that Design Assistant check compliance with HardCopy design guidelines early design process after every compilation.
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Checking Designs HardCopy Design Guidelines
Design Assistant Settings
must select design rules Design Assistant page prior running design. Assignments menu, click Settings. Settings dialog box, Category list, select Design Assistant turn Design Assistant during compilation. Altera recommends enabling this feature Design Assistant automatically during compilation your design.
Running Design Assistant
Design Assistant independently other Quartus features, Processing menu, point Start click Start Design Assistant. Design Assistant automatically runs background Quartus software when HardCopy Timing Optimization Wizard launched, does display Design Assistant results immediately display. design checked before Quartus software migrates design creates project directory performing timing analysis. Also, Design Assistant runs automatically whenever generate HardCopy design database with HardCopy Files Wizard. Design Assistant report generated used Altera HardCopy Design Center review your design.
Reports Summary
results running Design Assistant your design available Design Assistant Results section Compilation Report. Design Assistant also generates summary report <project name>\hardcopy subdirectory project directory. This report file titled <project name>_violations.datasheet. Reports include settings, summary, results summary, details results messages. Design Assistant report indicates rule name, severity violation, circuit path where violation occurred.
learn about design rules standard design practices comply with HardCopy design rules, refer Quartus Help HardCopy Series Design Guidelines chapter volume HardCopy Series Handbook.
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Generating HardCopy Design Database
HardCopy Files Wizard generate complete deliverables required migrating design HardCopy device single click. HardCopy Files Wizard asks questions related design archives your design, settings, results, database files delivery Altera. Your responses design details stored <project name>.hps.txt. generate archive HardCopy design database only after compiling design HardCopy Stratix device. Quartus Archive File generated same directory level targeted project, either before after optimization. Design Assistant automatically runs when HardCopy Files Wizard started.
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Generating HardCopy Design Database
Table shows archive directory structure files collected HardCopy Files Wizard.
Table 4-8. HardCopy Stratix Design Files Collected HardCopy Files Wizard
<project name>_hardcopy_optimization\ <project name>.flow.rpt <project name>.qpf <project name>.asm.rpt <project name>.blf <project name>.fit.rpt <project name>.gclk <project name>.hps.txt <project name>.macr <project name>.pin <project name>.qsf <project name>.sof <project name>.tan.rpt hardcopy\ <project name>.apc <project name>_cksum.datasheet <project name>_cpld.datasheet <project name>_hcpy.vo <project name>_hcpy_v.sdo <project name>_pt_hcpy_v.tcl <project name>_rba_pt_hcpy_v.tcl <project name>_target.datasheet <project name>_violations.datasheet hardcopy_fpga_prototype\ fpga_<project name>.asm.rpt fpga_<project name>.cmp.rcf fpga_<project name>.cmp.xml fpga_<project name>.db_info fpga_<project name>.fit.rpt fpga_<project name>.map.atm fpga_<project name>.map.rpt fpga_<project name>.pin fpga_<project name>.qsf fpga_<project name>.tan.rpt fpga_<project name>_cksum.datasheet fpga_<project name>_cpld.datasheet fpga_<project name>_hcpy.vo fpga_<project name>_hcpy_v.sdo fpga_<project name>_pt_hcpy_v.tcl fpga_<project name>_rba_pt_hcpy_v.tcl fpga_<project name>_target.datasheet fpga_<project name>_violations.datasheet db_export\ <project name>.db_info <project name>.map.atm <project name>.map.hdbx
After creating migration database with HardCopy Timing Optimization Wizard, must compile design before generating project archive. will receive error create archive before compiling design.
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Static Timing Analysis
addition performing timing analysis, Quartus software also provides requisite netlists scripts perform static timing analysis (STA) using Synopsys tool, PrimeTime. following files, necessary timing analysis with PrimeTime tool, generated HardCopy Files Wizard:
<project name>_hcpy.vo-Verilog output format <project name>_hpcy_v.sdo-Standard Delay Format Output File <project name>_pt_hcpy_v.tcl-Tcl script
These files available <project name>\hardcopy directory. PrimeTime libraries HardCopy Stratix Stratix devices included with Quartus software. HardCopy Stratix libraries PrimeTime perform during timing analysis designs targeted HARDCOPY_FPGA_PROTOTYPE device.
more information about static timing analysis, refer Classic Timing Analyzer Synopsys PrimeTime Support chapters volume Quartus Handbook. PowerPlay Early Power Estimation estimate amount power your HardCopy Stratix HardCopy APEX device will consume. This tool available Altera website. Using Early Power Estimator requires some knowledge your design resources specifications, including:
Early Power Estimation
Target device package Clock networks used design Resource usage LEs, blocks, PLL, blocks High speed differential interfaces (HSDI), general power consumption requirements, counts Environmental thermal conditions
HardCopy Stratix Early Power Estimation
PowerPlay Early Power Estimator provides initial estimate HardCopy Stratix device based typical conditions. This calculation saves significant time effort gaining quick understanding power requirements device. stimulus vectors necessary power estimation, which established clock frequency toggle rate each clock domain.
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Support HardCopy Stratix
This calculation should only used estimation power, specification. actual should verified during operation because this estimate sensitive actual logic device environmental operating conditions.
more information about simulation-based power estimation, refer Power Estimation Analysis Section volume Quartus Handbook. average, HardCopy Stratix devices expected consume less power than equivalent FPGA.
HardCopy APEX Early Power Estimation
PowerPlay Early Power Estimator from Altera website device support section cannot open this feature Quartus software. With HardCopy APEX PowerPlay Early Power Estimator, estimate power consumed HardCopy APEX devices design systems with appropriate power budget. Refer page instructions using HardCopy APEX PowerPlay Early Power Estimator. HardCopy APEX devices generally expected consume about less power than equivalent APEX 20KE APEX 20KC FPGA devices.
Support HardCopy Stratix
Quartus software also supports HardCopy Stratix design flow command prompt using scripts.
details Quartus support scripting, refer Scripting chapter volume Quartus Handbook.
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Targeting Designs HardCopy APEX Devices
Beginning with version 4.2, Quartus software supports targeting designs HardCopy APEX device families. After compiling your design APEX 20KC APEX 20KE FPGA devices supported HardCopy APEX device, HardCopy Files Wizard generate necessary files HardCopy migration. HardCopy APEX device requires different design files migration than HardCopy Stratix. Table shows files collected HardCopy APEX HardCopy Files Wizard.
Table 4-9. HardCopy APEX Files Collected HardCopy Files Wizard
<project name>.tan.rpt <project name>.asm.rpt <project name>.fit.rpt <project name>.hps.txt <project name>.map.rpt <project name>.pin <project name>.sof <project name>.qsf <project name>_cksum.datasheet <project name>_cpld.datasheet <project name>_hcpy.vo <project name>_hcpy_v.sdo <project name>_pt_hcpy_v.tcl <project name>_rba_pt_hcpy_v.tcl <project name>_target.datasheet <project name>_violations.datasheet
Refer "Generating HardCopy Design Database" page 4-54 information about generating complete deliverables required migrating design HardCopy APEX device. After have successfully HardCopy Files Wizard, submit your design archive Altera implement your design HardCopy device. should contact Altera more information about this process.
Conclusion
methodology designing HardCopy Stratix devices using Quartus software same that designing Stratix FPGA equivalent. familiar Quartus software tools design flow, target designs HardCopy Stratix devices, optimize designs higher performance lower power consumption than Stratix FPGAs, deliver design database migration HardCopy Stratix device. Compatible APEX FPGA designs migrate HardCopy APEX after compilation using HardCopy Files Wizard archive design files. Submit files HardCopy Design Center complete back-end migration.
4-58 Preliminary
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Referenced Documents
Referenced Documents
This chapter references following documents:
HardCopy Series Handbook Introduction Quartus Manual Introduction HardCopy Devices chapter HardCopy Device Family Data Sheet HardCopy Series Handbook Description, Architecture Features chapter HardCopy Device Family Data Sheet HardCopy Series Handbook Design Guidelines HardCopy Series Devices chapter HardCopy Series Handbook Quartus TimeQuest Timing Analyzer chapter volume Quartus Handbook Quartus Analyzing Optimizing Design Floorplan chapter volume Quartus Handbook Quartus PowerPlay Power Analysis chapter volume Quartus Handbook Quartus Incremental Compilation Hierarchical Team-Based Design chapter volume Quartus Handbook AN432: Using Different Settings Between Stratix HardCopy Devices Cadence Encounter Conformal Support chapter volume Quartus Handbook Back-End Design Flow HardCopy Series Devices chapter volume HardCopy Series Device Handbook HardCopy Stratix Device Family Data Sheet section volume HardCopy Series Handbook Programming Configuration chapter Introduction Quartus Manual Design Guidelines Section volume Quartus Handbook Classic Timing Analyzer chapter volume Quartus Handbook Synopsys PrimeTime Support chapter volume Quartus Handbook Power Estimation Analysis section volume Quartus Handbook Scripting chapter volume Quartus Handbook Quartus Handbook
Altera Corporation 2007
4-59 Preliminary
Quartus Handbook, Volume
Document Revision History
Table 4-10 shows revision history this chapter.
Table 4-10. Document Revision History Date Document Version
2007 v7.1.0
Changes Made
Summary Changes
Updated Quartus Updated "Timing Settings" page 4-13. version Updated "TimeQuest" page 4-14 Added "Setting TimeQuest Timing Analyzer" page 4-14 Added Constraints Clock Effect Characteristics page 4-15 Changed Performing ECOs with Change Manager Chip Planner title Performing ECOs with Quartus Engineering Change Management with Chip Planner page 4-20 Updated Migrating Changes that must Implemented Differently page 4-21 Added Referenced Documents page 4-59 medium update chapter, changes Quartus software version release; most changes were Performing ECOs with Change Manager Chip Planner Overall Migration Flow sections.
March 2007 v7.0.0 November 2006 v6.1.0
Updated Quartus software revision date only. other changes made chapter. Minor updates Quartus software version Added Performing ECOs with Change Manager Chip Planner Overall Migration Flow sections. Updated Quartus Software Features Supported HardCopy Designs section.
2006 v6.0.0
Minor updates Quartus software version 6.0.
October 2005 v5.1.0 Updated Quartus software version 5.1. 2005 v5.0.0
Chapter formerly Chapter Updated consistency with Quartus Support HardCopy Devices Quartus Support HardCopy Stratix Devices chapters HardCopy Series Handbook. Added HardCopy Device Material. Chapter formerly Chapter Updates tables, figures. functionality Quartus software Updates tables, figures. functionality Quartus software 4.1.
Jan. 2005 v2.1 Dec. 2004 v2.1
June 2004 v2.0 Feb. 2004 v1.0
Initial release.
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