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"Configurable Soft-Core Processor Concepts" on page 1­4

1. Introduction
NII51001-7.1.0
Introduction
This chapter is an introduction to the Nios® II embedded processor family. This chapter helps hardware and software engineers understand the similarities and differences between the Nios II processor and traditional embedded processors. This chapter contains the following sections:
"Configurable Soft-Core Processor Concepts" on page 1-4
Nios II Processor System Basics
The Nios II processor is a general-purpose RISC processor core, providing:
A Nios II processor system is equivalent to a microcontroller or "computer on a chip" that includes a processor and a combination of peripherals and memory on a single chip. The term "Nios II processor
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Introduction
system" refers to a Nios II processor core, a set of on-chip peripherals, onchip memory, and interfaces to off-chip memory, all implemented on a single Altera device. Like a microcontroller family, all Nios II processor systems use a consistent instruction set and programming model.
Getting Started with the Nios II Processor
Getting started with the Nios II processor is similar to any other microcontroller family. The easiest way to start designing effectively is to purchase a development kit from Altera that includes a ready-made evaluation board and all the software development tools necessary to write Nios II software. The Nios II software development environment is called The Nios II integrated development environment (IDE). The Nios II IDE is based on the GNU C / C++ compiler and the Eclipse IDE, and provides a familiar and established environment for software development. Using the Nios II IDE, you can immediately begin developing and simulating Nios II software applications. Using the Nios II hardware reference designs included in an Altera development kit, you can prototype an application running on a board before building a custom hardware platform. Figure 1-1 shows an example of a Nios II processor reference design available in an Altera Nios II development kit.
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Introduction
Figure 1-1. Example of a Nios II Processor System
JTAG connection to software debugger Reset Clock
JTAG Debug Module
Data Nios II Processor Core Inst.
TXD RXD
Timer1 Avalon Switch Fabric SDRAM Memory SDRAM Controller
Timer2 LCD Screen Buttons, LEDs, etc. Ethernet MAC / PHY Compact Flash
LCD Display Driver
On-Chip ROM Flash Memory Tristate bridge to off-chip memory SRAM Memory
General-Purpose I / O
Ethernet Interface CompactFlash Interface
If the prototype system adequately meets design requirements using an Altera-provided reference design, you can copy the reference design and use it as-is in the final hardware platform. Otherwise, you can customize the Nios II processor system until it meets cost or performance requirements.
Customizing Nios II Processor Designs
In practice, most FPGA designs implement some extra logic in addition to the processor system. Altera FPGAs provide flexibility to add features and enhance performance of the Nios II processor system. Conversely, you can eliminate unnecessary processor features and peripherals to fit the design in a smaller, lower-cost device.
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Configurable Soft-Core Processor Concepts
Because the pins and logic resources in Altera devices are programmable, many customizations are possible:
Configurable Soft-Core Processor Concepts
This section introduces Nios II concepts that are unique or different from other discrete microcontrollers. The concepts described in this section provide a foundation for understanding the rest of the features discussed in this document. For the most part, these concepts relate to the flexibility available to hardware designers to fine-tune system implementation. Software programmers generally are not affected by the hardware implementation details, and can write programs without awareness of the configurable nature of the Nios II processor core.
Configurable Soft-Core Processor
The Nios II processor is a configurable soft-core processor, as opposed to a fixed, off-the-shelf microcontroller. In this context, "configurable" means that you can add or remove features on a system-by-system basis to meet performance or price goals. "Soft-core" means the processor core is offered in "soft" design form (i.e., not fixed in silicon), and can be targeted to any Altera FPGA family. Configurability does not require you to create a new Nios II processor configuration for every new design. Altera provides ready-made Nios II system designs that you can use as-is. If these designs meet the system requirements, there is no need to configure the design further. In addition, software designers can use the Nios II instruction set simulator to begin writing and debugging Nios II applications before the final hardware configuration is determined.
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Introduction
Flexible Peripheral Set and Address Map
A flexible peripheral set is one of the most notable differences between Nios II processor systems and fixed microcontrollers. Because of the softcore nature of the Nios II processor, you can easily build made-to-order Nios II processor systems with the exact peripheral set required for the target applications. A corollary of flexible peripherals is a flexible address map. Altera provides software constructs to access memory and peripherals generically, independently of address location. Therefore, the flexible peripheral set and address map does not affect application developers. There are two broad classes of peripherals: standard peripherals and custom peripherals.
Standard Peripherals
Altera provides a set of peripherals commonly used in microcontrollers, such as timers, serial communication interfaces, general-purpose I / O, SDRAM controllers, and other memory interfaces. The list of available peripherals continues to grow as Altera and third-party vendors release new soft peripheral cores.
Custom Peripherals
You can also create custom peripherals and integrate them into Nios II processor systems. For performance-critical systems that spend most CPU cycles executing a specific section of code, it is a common technique to create a custom peripheral that implements the same function in hardware. This approach offers a double performance benefit: the hardware implementation is faster than software and the processor is free to perform other functions in parallel while the custom peripheral operates on data.
Custom Instructions
Like custom peripherals, custom instructions allow you to increase system performance by augmenting the processor with custom hardware. The soft-core nature of the Nios II processor enables you to integrate custom logic into the arithmetic logic unit (ALU). Similar to native Nios II instructions, custom instruction logic can take values from up to two source registers and optionally write back a result to a destination register.
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Referenced Documents
Because the processor is implemented on reprogrammable Altera FPGAs, software and hardware engineers can work together to iteratively optimize the hardware and test the results of software running on hardware. From the software perspective, custom instructions appear as machinegenerated assembly macros or C functions, so programmers do not need to know assembly in order to use custom instructions.
Automated System Generation
Referenced Documents
This chapter references no other documents.
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Introduction
Document Revision History
Table 1-1 shows the revision history for this document.
Table 1-1. Document Revision History Date & Document Version
May 2007 v7.1.0 March 2007 v7.0.0 November 2006 v6.1.0 May 2006 v6.0.0 October 2005 v5.1.0 May 2005 v5.0.0 September 2004 v1.1 May 2004 v1.0
Changes Made
Added table of contents to Introduction section. Added Referenced Documents section.
Summary of Changes
No change from previous release. No change from previous release.
Added single precision floating point and integration with SignalTap®II logic analyzer to features list. Updated performance to 250 DMIPS.
No change from previous release.
Updates for Nios II 1.01 release.
Initial release.
Altera Corporation May 2007
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Document Revision History
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