This chapter introduction Nios® embedded processor family. This chapte

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NII51001-7.1.0
This chapter introduction Nios® embedded processor family. This chapter helps hardware software engineers understand similarities differences between Nios processor traditional embedded processors. This chapter contains following sections:
"Configurable Soft-Core Processor Concepts" page
Nios Processor System Basics
Nios processor general-purpose RISC processor core, providing:
Full 32-bit instruction set, data path, address space general-purpose registers external interrupt sources Single-instruction multiply divide producing 32-bit result Dedicated instructions computing 64-bit 128-bit products multiplication Floating-point instructions single-precision floating-point operations Single-instruction barrel shifter Access variety on-chip peripherals, interfaces off-chip memories peripherals Hardware-assisted debug module enabling processor start, stop, step trace under integrated development environment (IDE) control Software development environment based C/C++ tool chain Eclipse Integration with Altera®'s SignalTap® logic analyzer, enabling realtime analysis instructions data along with other signals FPGA design Instruction architecture (ISA) compatible across Nios processor systems Performance DMIPS
Nios processor system equivalent microcontroller "computer chip" that includes processor combination peripherals memory single chip. term "Nios processor
Altera Corporation 2007
system" refers Nios processor core, on-chip peripherals, onchip memory, interfaces off-chip memory, implemented single Altera device. Like microcontroller family, Nios processor systems consistent instruction programming model.
Getting Started with Nios Processor
Getting started with Nios processor similar other microcontroller family. easiest start designing effectively purchase development from Altera that includes ready-made evaluation board software development tools necessary write Nios software. Nios software development environment called Nios integrated development environment (IDE). Nios based C/C++ compiler Eclipse IDE, provides familiar established environment software development. Using Nios IDE, immediately begin developing simulating Nios software applications. Using Nios hardware reference designs included Altera development kit, prototype application running board before building custom hardware platform. Figure shows example Nios processor reference design available Altera Nios development kit.
Nios Processor Reference Handbook
Altera Corporation 2007
Figure 1-1. Example Nios Processor System
JTAG connection software debugger Reset Clock
JTAG Debug Module
Data Nios Processor Core Inst.
UART
Timer1 Avalon Switch Fabric SDRAM Memory SDRAM Controller
Timer2 Screen Buttons, LEDs, etc. Ethernet MAC/PHY Compact Flash
Display Driver
On-Chip Flash Memory Tristate bridge off-chip memory SRAM Memory
General-Purpose
Ethernet Interface CompactFlash Interface
prototype system adequately meets design requirements using Altera-provided reference design, copy reference design as-is final hardware platform. Otherwise, customize Nios processor system until meets cost performance requirements.
Customizing Nios Processor Designs
practice, most FPGA designs implement some extra logic addition processor system. Altera FPGAs provide flexibility features enhance performance Nios processor system. Conversely, eliminate unnecessary processor features peripherals design smaller, lower-cost device.
Altera Corporation 2007
Nios Processor Reference Handbook
Configurable Soft-Core Processor Concepts
Because pins logic resources Altera devices programmable, many customizations possible:
rearrange pins chip siimplify board design. example, move address data pins external SDRAM memory side chip shorten board traces. extra pins logic resources chip functions unrelated processor. Extra resources provide extra gates registers "glue logic" board design; extra resources implement entire systems. example, Nios processor system consumes only large Altera FPGA, leaving rest chip's resources available implement other functions. extra pins logic chip implement additional peripherals Nios processor system. Altera offers library peripherals that easily connect Nios processor systems.
Configurable Soft-Core Processor Concepts
This section introduces Nios concepts that unique different from other discrete microcontrollers. concepts described this section provide foundation understanding rest features discussed this document. most part, these concepts relate flexibility available hardware designers fine-tune system implementation. Software programmers generally affected hardware implementation details, write programs without awareness configurable nature Nios processor core.
Configurable Soft-Core Processor
Nios processor configurable soft-core processor, opposed fixed, off-the-shelf microcontroller. this context, "configurable" means that remove features system-by-system basis meet performance price goals. "Soft-core" means processor core offered "soft" design form (i.e., fixed silicon), targeted Altera FPGA family. Configurability does require create Nios processor configuration every design. Altera provides ready-made Nios system designs that as-is. these designs meet system requirements, there need configure design further. addition, software designers Nios instruction simulator begin writing debugging Nios applications before final hardware configuration determined.
Nios Processor Reference Handbook
Altera Corporation 2007
Flexible Peripheral Address
flexible peripheral most notable differences between Nios processor systems fixed microcontrollers. Because softcore nature Nios processor, easily build made-to-order Nios processor systems with exact peripheral required target applications. corollary flexible peripherals flexible address map. Altera provides software constructs access memory peripherals generically, independently address location. Therefore, flexible peripheral address does affect application developers. There broad classes peripherals: standard peripherals custom peripherals.
Standard Peripherals
Altera provides peripherals commonly used microcontrollers, such timers, serial communication interfaces, general-purpose I/O, SDRAM controllers, other memory interfaces. list available peripherals continues grow Altera third-party vendors release soft peripheral cores.
Custom Peripherals
also create custom peripherals integrate them into Nios processor systems. performance-critical systems that spend most cycles executing specific section code, common technique create custom peripheral that implements same function hardware. This approach offers double performance benefit: hardware implementation faster than software; processor free perform other functions parallel while custom peripheral operates data.
Custom Instructions
Like custom peripherals, custom instructions allow increase system performance augmenting processor with custom hardware. soft-core nature Nios processor enables integrate custom logic into arithmetic logic unit (ALU). Similar native Nios instructions, custom instruction logic take values from source registers optionally write back result destination register.
Altera Corporation 2007
Nios Processor Reference Handbook
Referenced Documents
Because processor implemented reprogrammable Altera FPGAs, software hardware engineers work together iteratively optimize hardware test results software running hardware. From software perspective, custom instructions appear machinegenerated assembly macros functions, programmers need know assembly order custom instructions.
Automated System Generation
Altera's SOPC Builder design tool fully automates process configuring processor features generating hardware design that program into FPGA. SOPC Builder graphical user interface (GUI) enables configure Nios processor systems with number peripherals memory interfaces. create entire processor systems without performing schematic hardware description-language (HDL) design entry. SOPC Builder also import design files, providing easy mechanism integrate custom logic into Nios processor system. After system generation, download design onto board, debug software executing board. software developer, processor architecture design set. Software development proceeds same manner traditional, non-configurable processors.
Referenced Documents
This chapter references other documents.
Nios Processor Reference Handbook
Altera Corporation 2007
Document Revision History
Table shows revision history this document.
Table 1-1. Document Revision History Date Document Version
2007 v7.1.0 March 2007 v7.0.0 November 2006 v6.1.0 2006 v6.0.0 October 2005 v5.1.0 2005 v5.0.0 September 2004 v1.1 2004 v1.0
Changes Made
Added table contents Introduction section. Added Referenced Documents section.
Summary Changes
change from previous release. change from previous release.
Added single precision floating point integration with SignalTap®II logic analyzer features list. Updated performance DMIPS.
change from previous release.
change from previous release.
Updates Nios 1.01 release.
Initial release.
Altera Corporation 2007
Nios Processor Reference Handbook
Document Revision History
Nios Processor Reference Handbook
Altera Corporation 2007

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