MII51009-1.5 Technological advancements deep submicron processes

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Chapter Using Devices Multi-Voltage Systems
MII51009-1.5
Technological advancements deep submicron processes have lowered supply voltage levels semiconductor devices, creating design environment where devices system board potentially many different supply voltages such 5.0, 3.3, 2.5, 1.8, which ultimately lead voltage conflicts. accommodate interfacing with variety devices system boards, MAX® devices have MultiVoltI/O interfaces that allow devices mixed-voltage design environment communicate directly with devices. MultiVolt interface separates power supply voltage (VCCINT) from output voltage (VCCIO), enabling devices interface with other devices using different voltage level same printed circuit board (PCB). Additionally, with MultiVolt core feature, devices able operate with 3.3-V 2.5-V power supply devices 1.8-V power supply devices (MAX devices have internal voltage regulator that regulates devices, internal voltage regulator bypassed requiring user supply device. This chapter discusses several features that allow implement Altera® devices multiple-voltage systems without damaging device system, including:
Hot-Socketing-Insert remove devices from powered-up system without affecting device system operation Power-Up Sequence Flexibility-MAX devices accommodate possible power-up sequence Power-On Reset-MAX devices maintain reset state until voltage within operating range
Altera Corporation December 2006
Core Version a.b.c variable
Preliminary
Standards
Standards
buffer devices programmable supports wide range voltage standards. Each bank device programmed comply with different standard. banks configured with following standards:
3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS
Schmitt trigger input option supported 3.3-V 2.5-V standard. Bank also includes 3.3-V standard interface capability EPM1270 EPM2210 devices. Figure 8-1.
Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation December 2006
Using Devices Multi-Voltage Systems
Figure 8-1. Standards Supported Devices
Bank
Notes (1), (2), (3), (4),
Bank also supports 3.3-V Standard
Bank
Banks support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS
Bank
Individual Power
Bank
Notes Figure 8-1:
Figure view silicon die. Figure graphical representation only. Refer list Quartus® software exact locations. EPM240 EPM570 devices only have banks. 3.3-V standard only supported EPM1270 EPM2210 devices. Schmitt trigger input option 3.3-V 2.5-V standards supported pins.
MultiVolt Core Operation
devices include MultiVolt core operation capability, allowing core blocks device powered-up with separate supply voltages. VCCINT pins supply power device core VCCIO pins supply power device buffers. VCCINT pins powered-up with devices V/3.3 devices. VCCIO pins given bank that have MultiVolt capability should supplied from same voltage level (e.g., 5.0, 3.3, 2.5, 1.8, Figure 8-2.
Altera Corporation December 2006
Core Version a.b.c variable
Device Handbook, Volume
5.0-V Device Compatibility
Figure 8-2. Implementing Multiple-Voltage System with Device Notes (1), (2), (3),
V/2.5 V/3.3 Power Supply
VCCINT
5.0-V Device
VCCIO
Device
VCCIO
3.3-V Device
VCCIO
2.5-V Device
Notes Figure 8-2:
devices, VCCINT pins will only accept 1.8-V power supply. devices, VCCINT pins will only accept 2.5-V 3.3-V power supply. devices drive 5.0-V input when VCCIO drive 5.0-V CMOS, open-drain setting with internal clamp diode external resistor required. devices 5.0-V tolerant with external resistor internal clamp diode EPM1270 EPM2210 devices.
5.0-V Device Compatibility
device drive 5.0-V device connecting VCCIO pins device This possible because output high voltage (VOH) 3.3-V interface meets minimum high-level voltage 5.0-V device.
Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation December 2006
Using Devices Multi-Voltage Systems
device correctly interoperate with 5.0-V CMOS device output device connected directly input 5.0-V CMOS device. device`s VOUT greater than VCCIO, PMOS pull-up transistor still conducts driving high, preventing external pull-up resistor from pulling signal make device outputs compatible with 5.0-V CMOS devices, configure output pins open-drain pins with clamp diode enabled, external pull-up resistor. Figure 8-3. Figure 8-3. Device Compatibility with 5.0-V CMOS Devices
CCIO CCIO
CCIO
REXT
Open Drain Model RINT VOUT 5.0-V CMOS Device
Note Figure 8-3:
This diode only active after power-up. devices require external diode driven before power-up.
open-drain never drives high, only tri-state. When open-drain active, drives low. When open-drain inactive, tri-stated trace pulls external resistor. purpose enabling clamping diode protect device's pins. 3.3-V VCCIO supplied clamping diodes causes voltage point clamp which meets device's reliability limits when trace voltage exceeds device operates successfully because 5.0-V input within input specification.
Altera Corporation December 2006
Core Version a.b.c variable
Device Handbook, Volume
5.0-V Device Compatibility
clamping diode only supported EPM1270 EPM2210 device's Bank external protection diode needed other banks EPM1270 EPM2210 devices pins EPM240 EPM570 devices.
pull-up resistor value should small enough sufficient signal rise time, large enough that does violate (output low) specification devices. maximum device depends programmable drive strength output. Table shows programmable drive strength settings that available 3.3-V LVTTL/LVCMOS standard devices. standard always with alternate setting.
Table 8-1. 3.3-V LVTTL/LVCMOS Programmable Drive Strength Standard
3.3-V LVTTL
IOH/IOL Current Strength Setting (mA)
3.3-V LVCMOS
compute required value REXT, first calculate model open-drain transistors device. This output resistor (REXT) modeled dividing (REXT VOL/IOL). Table shows maximum 3.3-V LVTTL/LVCMOS standard devices. Refer chapter Switching Characteristics information standard specifications.
Table 8-2. 3.3-V LVTTL/LVCMOS Maximum Standard
3.3-V LVTTL 3.3-V LVCMOS
Voltage
0.45 0.20
Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation December 2006
Using Devices Multi-Voltage Systems
Select REXT that device's specification violated. compute required pull-up resistor value REXT using equation: REXT (VCC/IOL) RINT. example, configured 3.3-V LVTTL with drive strength, given that maximum power supply (VCC) value REXT calculated follows: 5.5V 0.45 315.6 This resistor value computation assumes worst-case conditions. adjust REXT value according device configuration drive strength. Additionally, your system does wide variation voltage-supply levels, adjust these calculations accordingly. Because devices 3.3-V, 32-bit, 66-MHz compliant, input circuitry accepts maximum high-level input voltage (VIH) drive device with 5.0-V device, must connect resistor (R2) between device 5.0-V device. Figure 8-4. Figure 8-4. Driving PCI-Compliant Device with 5.0-V Device
Device 5.0-V Device
CCIO Clamp CCIO
Model
Note Figure 8-4:
This diode only active after power-up. devices require external diode driven before power-up.
Altera Corporation December 2006
Core Version a.b.c variable
Device Handbook, Volume
5.0-V Device Compatibility
VCCIO devices clamping diode enabled, voltage point Figure which meets devices reliability limits when trace voltage exceeds limit large current draw from 5.0-V device, should small enough fast signal rise time large enough that does violate high-level output current (IOH) specifications devices driving trace. compute required value first calculate model pullup transistors 5.0-V device. This output resistor (R1) modeled dividing 5.0-V device supply voltage (VCC) IOH: VCC/IOH. Figure shows example typical output drive characteristics 5.0-V device. Figure 8-5. Output Drive Characteristics 5.0-V Device
VCCINT VCCIO
Typical Output Current (mA)
Output Voltage
shown above, V/135 values usually shown data sheets reflect typical operating conditions. Subtract from data sheet value guard band. This subtraction applied above example gives value
Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation December 2006
Using Devices Multi-Voltage Systems
Select that device's specification violated. example, above device maximum given clamping diode, VCCIO Given that maximum supply load 5.0-V device (VCC) 5.50 value calculated follows: 5.50V This analysis assumes worst-case conditions. your system does wide variation voltage-supply levels, adjust these calculations accordingly. Because 5.0-V device tolerance devices requires clamp, this clamp activated only after power-up, 5.0-V signals driven into device until configured. clamping diode only supported EPM1270 EPM2210 device's Bank external protection diode needed other banks EPM1270 EPM2210 devices pins EPM240 EPM570 devices.
Recommended Operating Condition 5.0-V Compatibility
mentioned earlier, 5.0-V tolerance supported with clamp diode enable with external series/pull-up resistance. guarantee long term reliability device's buffer, there restrictions signal duty cycle that drive which based maximum clamp current. Table shows maximum signal duty cycle 3.3-V VCCIO given clamp current handling capability.
Table 8-3. Maximum Signal Duty Cycle
Notes Table 8-3:
voltage package pin. calculated with 3.3-V VCCIO. higher VCCIO value will have lower value with same VIN.
(mA)
5.00 11.67 18.33 25.00 31.67 38.33 45.00
Duty Cycle
Altera Corporation December 2006
Core Version a.b.c variable
Device Handbook, Volume
Hot-Socketing
signals with duty cycle greater than input pins, Altera recommends VCCIO voltage guarantee long-term reliability. signals with duty cycle less than 30%, VCCIO voltage
Hot-Socketing Power-Up Sequencing
information socketing, refer chapter Socketing Power-On Reset Devices. devices designed operate multiple-voltage environments where difficult control power sequencing. Therefore, devices designed tolerate possible power-up sequence. Either VCCINT VCCIO initially supply power device, 3.3-V, 2.5-V, 1.8-V, 1.5-V input signals drive devices without special precautions before VCCINT VCCIO applied. devices operate with VCCIO voltage level that higher than VCCINT level. When VCCIO VCCINT supplied from different power sources device, delay between VCCIO VCCINT occur. Normal operation does occur until both power supplies their recommended operating range. When VCCINT powered-up, IEEE Std. 1149.1 Joint Test Action Group (JTAG) circuitry active. connected VCCIO VCCIO powered-up, JTAG signals left floating. Thus, transition cause state machine transition unknown JTAG state, leading incorrect operation when VCCIO finally powered-up. disable JTAG state during power-up sequence, should pulled ensure that inadvertent rising edge does occur TCK.
Power-On Reset Conclusion
information Power-On Reset (POR), refer chapter Socketing Power-On Reset Devices. devices have MultiVolt support, allowing 1.5-V, 1.8-V, 2.5-V, 3.3-V devices interface directly with devices without causing voltage conflicts. addition, devices interface with 5.0-V devices slightly modifying external hardware interface enabling clamping diodes Quartus software. This MultiVolt capability also enables device core core voltage, VCCINT, while maintaining compatibility with other devices. Altera taken further steps make system design easier designing devices that allow VCCINT VCCIO power-up sequence incorporating support hot-socketing.
8-10 Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation December 2006
Using Devices Multi-Voltage Systems
Document Revision History
Table shows revision history this document.
Table 8-4. Document Revision History Date Document Version Changes Made Summary Changes
December 2006 Added document revision history. v1.5 August 2006 v1.4 February 2006 v1.3 January 2005 v1.2 Updated 5.0-V Device Compatibility section. Updated Figure 8-3. Previously published Chapter changes content.
December 2004 Corrected typographical errors Note Figure 8-2. v1.1
Altera Corporation December 2006
Core Version a.b.c variable
8-11 Device Handbook, Volume

MII51009-1.5 Technological advancements deep submicron processes

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