Specification PARAMETERS Input Output Delay (first rising edge af
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Appendix PLL701-04
Specification PARAMETERS
Input Output Delay (first rising edge after input rising edge) Group Delay (first falling edge after input rising edge)
CONDITIONS
Input clock 16.5MHz Output clock 66MHz (Fin Load 15pF Input clock 10~30MHz Output clock 40~120MHz (Fin Load 15pF
MIN.
TYP.
MAX.
UNITS
Test Circuit:
Test condition:
Rising edge VDD/2 Falling edge VDD/2
FOUT
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/30/03 Page
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