Less than 0.4ps (12KHz 20MHz) phase jitter frequencies phase noise out

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Less than 0.4ps (12KHz 20MHz) phase jitter frequencies phase noise out

Datasheet Thumbnail

Top Searches for this datasheet

38MHz 640MHz Phase Noise
Less than 0.4ps (12KHz 20MHz) phase jitter frequencies phase noise output 1MHz offset) -144dBc/Hz 106.25MHz -144dBc/Hz 156.25MHz -144dBc/Hz 212.5MHz -140dBc/Hz 312.5MHz -131dBC/Hz 622.08MHz Fundamental Crystal Input Frequency: 19MHz 40MHz (3.3V) 19MHz 28.125MHz (2.5V) Output Frequency: 38MHz 640MHz (3.3V) 38MHz 450MHz (2.5V) Selectable LVPECL, LVDS, LVCMOS outputs Output Enable selector 2.5V 3.3V operation Available form
CONFIGURATION
OUTSEL0v
OUTSEL1^
VDDOSC
VDDANA
VDDANA
VDDDIG
SEL0^
SEL1^
(1550,1475)
GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^
XOUT SEL2^
2525-27
OE_CTRL
C502A
GNDOSC
GNDANA
(0,0)
Note1: Denotes internal pull resistor.
DESCRIPTION
PL680-30 monolithic jitter phase noise capable 0.4ps phase jitter LVPECL, LVDS, LVCMOS outputs, covering wide frequency output range 640MHz. PL680-30 designed address demanding requirements high performance applications such SONET, GPS, XDSL, etc.
SPECIFICATIONS
Name Size Reverse side dimensions Thickness Value micron micron
BLOCK DIAGRAM
SEL[0:2]
Divider
XOUT
Xtal
Phase Detector
Charge Pump Loop Filter
(FXiNx16)
Output Divider (1,2,4,8)
GNDBUF
GNDDIG
QBAR
Performance Tuner
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page
38MHz 640MHz Phase Noise
OUTPUT ENABLE LOGICAL LEVELS
OUTSEL0 (Pad #25) OUTSEL1 (Pad #18) Selected Output LVDS LVPECL (Default) High Drive LVCMOS Standard Drive LVCMOS
Note: bonding convenience, `OUTSEL0' incorporates internal pull down resistor while `OUTSEL1' incorporates internal pull resistor.
OUTPUT SELECTION OUTPUT ENABLE LOGIC
OE_SEL (Pad (Default) OE_CTRL (Pad #30) (Default) (Default) State Output enabled Tri-state Tri-state Output enabled
Bond "0", bond leave floating "1", #30: Logical states defined LVPECL levels OE_SELECT Logical states defined LVCMOS levels OE_SELECT
FREQUENCY SELECTION TABLE
SEL2 SEL1 SEL0 Selected Multiplier/Output Frequency Max* Min* Reserved Reserved
pads have internal pull-ups (default value `1'). Bond "0". Special Test Modes help selecting inductor value target output frequency.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page
38MHz 640MHz Phase Noise
ASSIGNMENT
Name GNDOSC GNDANA GNDDIG GNDBUF OE_SELECT LVDS PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1 SEL1 SEL0 VDDDIG VDDANA VDDANA VDDOSC OUTSEL0 XOUT SEL2 OE_CTRL 1042 1171 1400 1400 1400 1400 1400 1400 1400 1400 1389 1232 1042 1089 1227 1365 1365 1365 1365 1365 1365 1365 1365 1365 1223 1017 Description Ground, Oscillator circuitry. Ground, Analog circuitry. Performance/Frequency tuning Inductor. Performance/Frequency tuning Inductor. Connect. Connect. Ground, Digital circuitry. Ground, buffer circuitry. Used select between LVPECL LVCMOS/LVDS logic states Incorporates internal pull resistor. LVDS Output. LVPECL Output. 2.5V 3.3V power supply, Buffer circuitry. 2.5V 3.3V power supply, Buffer circuitry. Complementary LVPECL Output. Complementary LVDS Output. Single ended LVCMOS output. Ground, buffer circuitry. Used select LVCMOS, LVPECL LVDS output type. Incorporates internal pull resistor. Used select multiplication factor. Incorporates internal pull resistor. Used select multiplication factor. Incorporates internal pull resistor. 2.5V 3.3V power supply, Digital circuitry. 2.5V 3.3V power supply, Analog circuitry. 2.5V 3.3V power supply, Analog circuitry. 2.5V 3.3V power supply, Oscillator circuitry. Used select CMOS, PECL LVDS output type. Incorporates internal pull down resistor. Crystal input. crystal specification details. Crystal output. crystal specification details. Used select multiplication factor. Incorporates internal pull Connect Used enable/disable output(s). Output Selection Output Enable Logic table page Incorporates internal pull (LVCMOS/LVDS) pull down (LVPECL) resistor. Connect.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page
38MHz 640MHz Phase Noise
PERFORMANCE TUNING INDUCTOR VALUE SELECTION
Please refer PhaseLink's `PhasorV Tuning Assistance' software automatically calculate optimum inductor values your application. addition, chart below could used reference quick inductor value selection. Please note that inductor values mentioned table below, when using `PhasorV Tuning Assistance' derived based parasitic values PhaseLink's evaluation board. performance enhancement your custom board design, please follow following instruction: special test modes "VCO Max" "VCO Min" determine optimum inductor value. "VCO Max" represents high range "VCO Min" represents range. output frequency "VCO Max" "VCO Min" test modes VCO/16. This means that output frequencies around crystal frequency that will used. optimum inductor value where target crystal frequency closest middle between "VCO Max" "VCO Min" output frequencies. this case will lock middle tuning range with maximum margin either side.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page
38MHz 640MHz Phase Noise
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) SYMBOL -0.5 -0.5 MIN. MAX. +0.5 +0.5 UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied. Note: Operating Temperature guaranteed design parts (COMMERCIAL INDUSTRIAL), tested COMMERCIAL grade only.
Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Shunt Capacitance Recommended SYMBOL (xtal) (xtal) CONDITIONS Parallel Fundamental Mode, 3.3V Parallel Fundamental Mode, 2.5V MIN. TYP. MAX. 28.125 UNITS
General Electrical Specifications PARAMETERS Supply Current, Dynamic (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current Stabilization Time SYMBOL (LVCMOS) 1.25V (LVDS) 1.3V (LVPECL) From power valid CONDITIONS LVPECL/LVDS 38MHz<F <100MHz /LVCMOS 100MHz<F <320MHz LVPECL/LVDS 320MHz<F <640MHz 2.25** MIN. TYP. MAX. 65/45/30 80/60/40 90/70 3.63 UNITS
Note: LVCMOS operation advised above 200MHz with 15pF load; 320MHz with 10pF load. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. 2.5V operating supply voltage, denoted (**), limited maximum output frequency MHz.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page
38MHz 640MHz Phase Noise
Jitter Specifications PARAMETERS CONDITIONS FREQUENCY 106.25MHz Integrated jitter 156.25MHz Integrated 12kHz 20MHz 212.5MHz 312.5MHz 622.08MHz 106.25MHz Period jitter With capacitive decoupling between GND. Over 10,000 cycles. 156.25MHz 212.5MHz 312.5MHz 622.08MHz 106.25MHz Period jitter Peak-to-Peak With capacitive decoupling between GND. Over 10,000 cycles. 156.25MHz 212.5MHz 312.5MHz 622.08MHz Phase Noise Specifications PARAMETERS FREQ. 106.25MHz Phase Noise relative carrier (typical) 156.25MHz 212.5MHz 312.5MHz 622.08MHz @10Hz @100Hz @1kHz -122 -120 -118 -117 -111 @10kHz -132 -132 -126 -128 -120 @100kHz -126 -128 -120 -125 -118 -144 -140 -140 -139 -128 @10M -150 -150 -150 -148 -138 dBc/Hz UNITS MIN. TYP. MAX. UNITS
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page
38MHz 640MHz Phase Noise
LVDS Electrical Characteristics PARAMETERS Output Differential Voltage Magnitude Change Output High Voltage Output Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
SYMBOL
CONDITIONS
MIN.
TYP.
MAX. 1.375
UNITS
(see figure)
1.125
-5.7
SYMBOL
CONDITIONS (see figure)
MIN.
TYP.
MAX.
UNITS
LVDS Switching Test Circuit
10pF
VDIFF
10pF
LVDS Transistion Time Waveform
(Differential)
VDIFF
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page
38MHz 640MHz Phase Noise
LVPECL Electrical Characteristics PARAMETERS Output High Voltage Output Voltage SYMBOL CONDITIONS (see figure) MIN. 1.025 1.620 MAX. UNITS
LVPECL Switching Characteristics PARAMETERS Clock Rise Fall Times Clock Rise Fall Times Clock Rise Fall Times SYMBOL FREQ. <150MHz >150MHz <320MHz >320MHz
LVPECL Levels Test Circuit
CONDITIONS @20/80% LVPECL @80/20% LVPECL
MIN.
TYP.
MAX. 0.55 0.45
UNITS
LVPECL Output Skew
2.0V
tSKEW
LVPECL Transition Time Waveform
DUTY CYCLE
LVCMOS Electrical Characteristics PARAMETERS Output Drive Current Output Clock Rise/Fall Time SYMBOL CONDITIONS -0.4V, =3.3V 0.4V, 3.3V 0.3V 3.0V with load 20%-80% with Load MIN. TYP. MAX. UNITS
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page
38MHz 640MHz Phase Noise
ORDERING INFORMATION
part ordering, please contact Sales Department: 47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER order number this device combination following: Part number, Package type Operating temperature range
PL680-30
PART NUMBER PACKAGE TYPE TEMPERATURE C=COMMERCIAL (0°C 70°C) I=INDUSTRAL (-40°C 85°C)
Part/Order Number PL680-30DC
Marking P680-30DC
Package Option (Waffle Pack)
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/14/07 Page

Less than 0.4ps (12KHz 20MHz) phase jitter frequencies phase noise out

Top Searches for this datasheet

Other recent searches