Advanced design low-frequency (KHz) input applications. Accepts >0.1V

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Advanced design low-frequency (KHz) input applications. Accepts >0.1V

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1.8V-3.3V PicoPLL Input, Output Clock
Advanced design low-frequency (KHz) input applications. Accepts >0.1V reference signal input voltage Very Jitter Phase Noise (30-70ps Pk-Pk typical) Input Frequency: 32.768kHz Output Frequency: 12MHz 24MHz Single 1.8V 3.3V, power supply Operating temperature range from -40C Available 6-pin DFN, SOT23, SC70 GREEN/RoHS compliant packages.
DESCRIPTION
PL611s-52 low-cost general purpose frequency synthesizer member PhaseLink's PicoPLL family. Designed small SOT23, SC70, package high performance applications, PL611s-52 accepts frequency 32.768kHz Reference input generates selectable 12MHz 24MHz output with best phase noise, jitter performance, power consumption handheld devices notebook applications.
BLOCK DIAGRAM
FSEL (32.768kHz)
Fixed Multiplier
CLK0 (12.0MHz/24.0MHz)
PL611s-52
CLK0 FSEL
CLK0
PL611s-52
PL611s-52
FSEL
CLK0
FSEL
DFN-6L (2.0mmx1.3mmx0.6mm)
SC70-6L (2.3mmx2.25mmx1.0mm)
SOT23-6L (3.0mmx3.0mmx1.35mm)
PACKAGE ASSIGNMENT
Name
SC70
Type
connection.
Description
FSEL
Frequency Select (FSEL) Control. State CLK0 Output (default) Reference input pin. Loop Filter input pin. connection Selectable 12MHz 24MHz output 12MHz 24MHz
CLK0
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/5/07 Page
1.8V-3.3V PicoPLL Input, Output Clock
APPLICATION RECOMMENDATIONS PL611s-52
PL611s-52 accepts reference input 32.768kHz produces 12MHz 24MHz clock output shown diagram `1', below. However, save costs consumer product system designs greater area optimization, possible XOUT crystal (32.768KHz) reference input PL611s52, shown diagram `2', below.
32.768 XOUT
ASIC
32.768kHz FSEL 3.3V
LFGND (12MHz 24MHz)
XOUT
REFIN FSEL 3.3V
LFGND (12MHz 24MHz)
Diagram
Diagram
Note: Coupling required Clock amplitude small.
LAYOUT CONSIDERATIONS PERFORMANCE OPTIMIZATION following guidelines assist with performance optimized design: Keep traces PL611s-52 short possible, well keeping other traces away from possible. When reference input clock generated from crystal (see diagram above), place PL611s-52 `FIN' close possible `Xout' crystal pin. This will reduce cross-talk between reference input other signals. Place Loop Filter (LF) components close package PL611s-52 possible. Place 0.01µF~0.1µF decoupling capacitor between GND, component side PCB, close pin. recommended place this component backside PCB. Going through vias will reduce signal integrity, causing additional jitter phase noise. highly recommended keep traces short possible. When connecting long traces inch) CMOS output, important design traces transmission line `stripline', avoid reflections ringing. this case, CMOS output needs matched trace impedance. Usually `striplines' designed impedance CMOS outputs usually have lower than impedance matching achieved adding resistor series with CMOS output `stripline' trace. Please contact PhaseLink additional applications support.
DFN-6L Evaluation Board
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/5/07 Page
1.8V-3.3V PicoPLL Input, Output Clock
GUIDELINES EXTERNAL COMPONENT SELECTION
optimum performance, accurate external loop filter components must selected. general guideline selecting these components based input frequency shown below table. Input Frequency
32.768kHz
Capacitor Value
6.8nF
Resistor Value
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature (Green package) Data Retention Storage Temperature Ambient Operating Temperature*
SYMBOL
MIN.
-0.5 -0.5 -0.5
MAX.
+0.5 +0.5
UNITS
Year
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied. *Operating temperature guaranteed design. Parts tested commercial grade only.
SPECIFICATIONS
PARAMETERS
Input Frequency (FIN) Output Frequency Settling Time Input (FIN) Signal Amplitude Output Rise Time Output Fall Time Duty Cycle
CONDITIONS
Reference Clock Input =3.3V power-up (after increases over 1.62V) Internally coupled 15pF Load, 10/90% Drive, 3.3V 15pF Load, 90/10% Drive, 3.3V
MIN.
TYP.
32.768 12/24
MAX.
UNITS
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/5/07 Page
1.8V-3.3V PicoPLL Input, Output Clock
SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with Loaded CMOS Outputs Operating Voltage Output Voltage Output High Voltage Output Current, drive
SYMBOL
CONDITIONS
=3.3V,12MHz, load=15pF
MIN.
TYP.
MAX.
UNITS
2.97 +4mA -4mA 0.4V, 2.4V
3.63
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/5/07 Page
1.8V-3.3V PicoPLL Input, Output Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6 Symbol SC70-6L Symbol DFN-6L
Dimension Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.00 0.35 0.55 0.95
Pin1
Dimension Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC
Pin1
Symbol
Dimension Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30
Chamfer
Pin1
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/5/07 Page
1.8V-3.3V PicoPLL Input, Output Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
part ordering, please contact Sales Department: 47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER order number this device combination following: Part number, Package type Operating temperature range
PL611s-52-XXX
PART NUMBER
DIGIT Code (will assigned programming time) PACKAGE TYPE T=SOT U=SC70 G=DFN
NONE= TUBE R=TAPE REEL TEMPERATURE C=COMMERCIAL (0°C 70°C) INDUSTRIAL (-40°C 85°C)
Part Number/Order Number
PL611s-52-XXXGC-R PL611s-52-XXXUC-R PL611s-52-XXXTC-R
Marking
DXXX
Package Option
6-Pin (Tape Reel) 6-Pin SC70 (Tape Reel) 6-Pin SOT-23 (Tape Reel)
Note: `XXX' designates marking identifier that could independent part number.
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/5/07 Page

Advanced design low-frequency (KHz) input applications. Accepts >0.1V

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