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Section HardCopy Device Family Data Sheet
This section provides designers with data sheet specifications HardCopy® devices. These chapters contain feature definitions internal architecture, configuration JTAG boundary-scan testing information, operating conditions, timing parameters, reference power consumption, ordering information HardCopy devices. This section contains following:
Chapter Introduction HardCopy Devices Chapter Description, Architecture, Features Chapter Boundary-Scan Support Chapter Switching Specifications Operating Conditions Chapter Quartus Support HardCopy Devices Chapter Script-Based Design HardCopy Devices Chapter Timing Constraints HardCopy Devices Chapter Migrating Stratix Device Resources HardCopy Devices
Revision History
Refer each chapter specific revision history. information when each chapter updated, refer Chapter Revision Dates section, which appears complete handbook.
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Section Preliminary
Revision History
HardCopy Series Handbook, Volume
Section Preliminary
Altera Corporation
Introduction HardCopy Devices
H51015-2.5
Introduction
HardCopy devices low-cost, high-performance structured ASICs with pin-outs, densities, architecture that complement Stratix devices. HardCopy device features, such phase-locked loops (PLLs), memory, elements (IOEs), functionally electrically equivalent Stratix FPGA features. combination Stratix FPGAs in-system prototype design verification, HardCopy devices high-volume production, Quartus software design, provide complete, low-risk design solution. HardCopy devices improve successful proven methodology previous generations HardCopy series devices. Altera® HardCopy devices same base arrays across multiple designs given device density customized using only metal layers. HardCopy devices offer cost reduction compared Stratix FPGA prototypes. Quartus software provides complete tools, common both designing Stratix FPGA prototypes quickly migrating design HardCopy companion device. HardCopy devices also supported through other front-end design tools from Synopsys, Synplicity, Mentor Graphics
Feature Overview
HardCopy structured ASICs manufactured all-layer-copper metal fabrication process nine layers metal). HardCopy devices offer following features:
Fine-grained HCell architecture resulting low-cost, high-performance, low-power structured ASIC Customized using only metal layers fast turn-around times non-recurring expenses (NRE) Fully tested prototypes available approximately weeks from date your design submission Support instant-on instant-on-after-50-ms power-up modes Preserves design functionality Stratix FPGA prototype 1,000,000 3,600,000 usable gates both logic functions
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HardCopy Series Handbook, Volume
System performance power reduction (dynamic static) typical designs compared Stratix FPGA prototypes actual performance power consumption improvements mentioned this datasheet design-dependent. Internal Memory 8,847,360 bits available (including parity bits) True dual-port memory, suitable first-in-first-out (FIFO) buffers Phase-Locked Loops (PLLs) global clocks with clocking resources device region Clock control block supports dynamic clock network enable/disable dynamic global clock network source selection PLLs (four enhanced PLLs eight fast PLLs) device which provide identical features FPGA counterparts, including spread spectrum, programmable bandwidth, clock switchover, real-time reconfiguration, advanced multiplication, phase shifting Standards Intellectual Property (IP) Support numerous single-ended differential standards such LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL, LVDS High-speed differential support channels with dynamic phase alignment (DPA) circuitry 1-Gigabit-per-second (Gbps) performance Support high-speed networking communications standards including Parallel RapidIO, SPI-4 Phase (POS-PHY Level HyperTransporttechnology, SFI-4 Support high-speed external memory, including DDR2 SDRAM, RLDRAM QDRII SRAM, SDRAM Support multiple intellectual property megafunctions from Altera MegaCore functions, Altera Megafunction Partners Program (AMPPSM) megafunctions Packaging Pin-compatible with Stratix FPGA prototypes user pins available Available wire bond flip-chip space-saving FineLine packages (Table 1-3).
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Feature Overview
HardCopy device family consists five devices. Table summarizes features available HardCopy devices.
Table 1-1. HardCopy Device Family Features Feature
ASIC equivalent gates blocks Kbits plus parity) M-RAM blocks (512 Kbits plus parity) Total bits (including parity bits) Enhanced PLLs Fast PLLs Maximum user pins (4), Notes Table 1-1:
HC210W devices wire bond package. other HardCopy devices Stratix FPGAs flip-chip package. Devices wire bond package offer different performance signal integrity characteristics compared devices flip-chip package. This number ASIC equivalent gates available HardCopy base array, shared between both adaptive logic module (ALM) logic functions from Stratix FPGA prototype. Each Stratix adaptive logic module (ALM) equal approximately ASIC equivalent gates. number ASIC equivalent gates usable bounded number ALMs companion Stratix FPGA device. Total number usable blocks 768, which allows migration compatibility when prototyping with EP2S180 device. This different from Quartus software total physical count HC240. counts include dedicated input pins, which used clock signals data inputs. Quartus counts include additional (PLLENA), which available general-purpose pin. PLLENA only used enable PLLs.
HC210W
1,000,000 875,520
HC210
1,000,000 875,520
HC220
1,900,000 3,059,712
HC230
2,900,000 6,368,256
HC240
3,600,000 8,847,360
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Migration Packaging Overview
HardCopy devices offer pin-to-pin compatibility Stratix prototype, which makes them drop-in replacements FPGAs. Therefore, same system board software developed prototyping field trials retained, enabling fastest time-to-market high-volume production. When migrating specific Stratix FPGA HardCopy device, there number FPGA prototype choices, shown Table 1-2. Depending design resource needs, designers choose appropriate HardCopy device.
Table 1-2. Stratix FPGA HardCopy Migration Paths HardCopy Device
HC210W HC210 HC220 HC220 HC230 HC240 HC240
Stratix Device Package EP2S30
484-pin FineLine 484-pin FineLine 672-pin FineLine 780-pin FineLine 1,020-pin FineLine 1,020-pin FineLine 1,508-pin FineLine
EP2S60
EP2S90
EP2S130
EP2S180
Notes Table 1-2:
HC210W device uses wire bond package while Stratix FPGA prototype device uses pin-compatible flip-chip package. Depending design specific resource utilization, opportunistic migration path exist between this device pair. sure confirm your design potential candidate such path fitting with Quartus software consulting Altera applications engineer.
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Document Revision History
HardCopy devices available packages shown Table 1-3.
Table 1-3. HardCopy Package Options Counts Package Type Dimension
Pitch (mm) Area (mm2) 1.00 1.00 1.00
Notes (1),
484-Pin 484-Pin 672-Pin 780-Pin 1,020-Pin 1,508-Pin FineLine FineLine FineLine FineLine FineLine FineLine
Wire bond Flip-chip Flip-chip Flip-chip Flip-chip Flip-chip
1.00
1.00 1,089
1.00 1,600
Length width
Device
HC210W HC210 HC220 HC230 HC240 Notes Table 1-3:
Maximum User Pins
Quartus counts include additional (PLLENA) which available general-purpose pin. PLLENA only used enable PLLs. counts include dedicated input pins, which used clock signals data inputs. EP2S90 FPGA prototype uses 484-pin hybrid FineLine package. more information, refer Stratix Device Handbook.
Document Revision History
Table shows revision history this chapter.
Table 1-4. Document Revision History (Part Date Document Version
June 2007, v2.5 December 2006 v2.4 Minor text edits.
Changes Made
Summary Changes
Minor updates Quartus software version 6.1.0 Merged Table Table Added revision history
minor update chapter, changes Quartus software version release. Merged Table Table 1-4.
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Table 1-4. Document Revision History (Part Date Document Version
March 2006, v2.3
Changes Made
Updated Table Table 1-3. Minor edits clarifications throughout.
Summary Changes
October 2005, v2.2. Updated graphics July 2005, v2.2. 2005, v2.0 Updated graphics
Updated Table 1-1. Updated migration process time. Updated "Features" section.
January 2005 v1.0
Added document HardCopy Series Handbook.
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Description, Architecture, Features
H51016-2.4
Introduction
Altera® HardCopy devices feature architecture that provides high-density, high-performance, low-power consumption suitable variety applications. HardCopy devices low-cost structured ASICs with pin-outs, densities, architecture that complement Stratix FPGAs. HardCopy devices make optimal area core resources while offering features that functionally equivalent Stratix FPGA. combination Stratix FPGAs in-system prototype design verification, HardCopy devices high-volume production, Quartus® design software, provide complete, seamless path from prototype volume production. Table provides overview HardCopy device features.
Table 2-1. HardCopy Family Overview (Part Feature
ASIC gates blocks bits plus parity) M-RAM blocks (512k bits plus parity) Total bits (including parity bits) Enhanced PLLs Fast PLLs Package (maximum user pins) (4),
HC210W
1,000,000 875,520 484-pin FineLine (308)
HC210
1,000,000 875,520 484-pin FineLine (334)
HC220
1,900,000 3,059,712 672-pin FineLine (492) 780-pin FineLine (494)
HC230
2,900,000 6,368,256 1,020-pin FineLine (698)
HC240
3,600,000 8,847,360 1,020-pin FineLine (742) 1,508-pin FineLine (951)
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Table 2-1. HardCopy Family Overview (Part Feature
FPGA prototype options Notes Table 2-1:
HC210W devices wire bond package. other HardCopy devices Stratix FPGAs flip-chip package. Devices wire bond package offer different performance signal integrity characteristics compared devices flip-chip package. This number ASIC gates available HardCopy base array both logic functions that implemented Stratix FPGA prototype. Total number usable blocks 768, which allows migration compatibility when prototyping with EP2S180 device. This different from Quartus software total physical count HC240. counts include dedicated clock input pins, which used clock signals data inputs. Quartus counts include additional (PLLENA), which available general-purpose pin. PLLENA only used enable PLLs.
HC210W
EP2S30 EP2S60 EP2S90
HC210
EP2S30 EP2S60 EP2S90
HC220
EP2S60 EP2S90 EP2S130
HC230
EP2S90 EP2S130 EP2S180
HC240
EP2S180
Functional Description
HardCopy device family provides greater flexibility design with FPGA prototypes before moving structured ASICs production. Before seamlessly migrating HardCopy structured ASIC, designers prototype test their design functionality using Stratix FPGA. There multiple options prototype FPGA, allowing designers choose right HardCopy device volume production maximum cost savings. Quartus design software includes features such Device Resource Guide, help select optimal HardCopy device based design requirements. more information Device Resource Guide, refer Quartus Support HardCopy Devices chapter HardCopy Series Handbook. HardCopy devices require minimal involvement from designer device migration process. Additionally, unlike ASICs, designer required generate test benches, test vectors, timing functional simulations since prototyping performed using FPGA. HardCopy devices consist base arrays that common designs particular device density, with design-specific customization done using metal layers. reprogrammable FPGA logic, routing, memory, FPGA configuration-related logic stripped from HardCopy devices. Removing programmable configuration resources replacing them with direct metal connections results considerable size reduction cost savings. fine-grain architecture consisting array HCells extends reduction cost
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Functional Description
savings, which results low-cost structured ASICs with high-performance low-power suitable wide variety applications. SRAM configuration cells Stratix FPGAs replaced HardCopy devices with metal connections, which define function logic, memory, phase-locked loop (PLL), elements (IOEs) device. These resources interconnected using metallization layers. Once HardCopy device manufactured, functionality device fixed. HardCopy devices manufactured using same 90-nm process technology operate using same core voltage (1.2 Stratix FPGAs. Additionally, almost architectural features HardCopy devices functionally equivalent features found Stratix FPGA architecture. HardCopy devices feature HCells, memory blocks, PLLs, IOEs (Figure 2-1). Figure 2-1. Example Block Diagram HC230 Device
Blocks Array HCells Blocks IOEs Array HCells Enhanced
Note
Fast
Array HCells
M-RAM Block
Fast Array HCells Array HCells Array HCells
Note Figure 2-1:
Figure shows graphical representation device floor plan. detailed floor plan available Quartus software.
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HardCopy Series Handbook, Volume
HardCopy Stratix Similarities Differences
HardCopy devices preserve functionality Stratix FPGAs. Implementation these architectural features HardCopy structured ASICs matches Stratix FPGA implementation, with exceptions. Table shows qualitative comparison HardCopy device feature implementation versus Stratix FPGA feature implementation. Other sections within this chapter provide details similarities differences particular HardCopy feature.
Table 2-2. HardCopy Device Stratix FPGA Feature Implementation Feature
Logic blocks blocks Memory Clock networks PLLs features Configuration Note Table 2-2:
HardCopy structured ASICs need configured upon power-up.
Equivalent
Different
major similarities differences between Stratix FPGAs HardCopy devices highlighted below:
HardCopy result power reduction than equivalent Stratix FPGAs operating same frequency. Power consumption design dependent direct result design performance resource utilization. HardCopy devices offer 100% performance improvement when compared Stratix FPGA prototypes. performance improvement achieved efficient logic blocks, metal interconnect optimization, size reduction, customized signal buffering. Logic blocks, known HCells, basic building block core logic HardCopy devices replace Stratix adaptive logic modules (ALMs). HCells implement logic functions. block functions implemented using HCells, instead dedicated blocks. M-RAM memory blocks implement various types memory (the same Stratix FPGAs), with without parity, including true dual-port, simple dual-port, single-port RAM, ROM, first-in first-out (FIFO) buffers.
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HardCopy Stratix Similarities Differences
Unlike Stratix FPGAs, HardCopy block contents cannot pre-loaded with Memory Initialization File (.mif) when used RAM. When used ROM, HardCopy blocks initialized contents. When used RAM, select non-registered output mode, HardCopy M-RAM blocks power with outputs unknown. Stratix FPGAs, blocks power with outputs cleared, while M-RAM blocks power with outputs unknown. registered outputs mode selected, outputs cleared both M-RAM blocks HardCopy memory contents unknown under both instances. HardCopy clock network features same Stratix FPGAs. Enhanced fast implementations HardCopy devices same Stratix FPGAs. Stratix features supported standards offered HardCopy devices. Joint Test Action Group (JTAG) boundary scan order length HardCopy devices different than that Stratix FPGA. HardCopy boundary-scan description language (BSDL) file that describes re-ordered shortened boundary scan chain. Unlike Stratix devices, HardCopy devices customized using metal layers. Therefore, configuration circuitry required. FPGA configuration emulation other configuration modes, including remote system upgrades design security using configuration bitstream encryption, supported HardCopy devices. Even though configuration required, CRC_ERROR function supported HardCopy using Quartus software version above. There need recompile Stratix design eliminate this feature. Only supplementary information highlight HardCopy similarities differences compared Stratix FPGA architecture functionality provided this chapter. more information similarities differences available resources HardCopy refer Migrating Stratix Device Resources HardCopy Devices chapter this Handbook. addition, Stratix Device Handbook detailed explanations architectural features functions that similar HardCopy devices.
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HardCopy Series Handbook, Volume
HCells
HardCopy devices built using array fine-grained architecture blocks called HCells. HCells collection logic transistors based process technology, similar Stratix devices. construction logic using HCells allows flexible functionality such that when HCells combined, viable logic combinations Stratix functionality replicated. These HCells constitute array HCells area Figure 2-1. Only HCells needed implement customer design assembled together, which optimizes HCell utilization. unused area HCell logic fabric powered down, resulting significant power savings compared with Stratix FPGA prototype. Quartus software uses library pre-characterized HCell macros place Stratix configurations into HardCopy HCell-based logic fabric. HCell macro defines group HCells connected together within array. HCell macros construct combinations combinational logic, adder, register functions that implemented Stratix ALM. HCells used configurations used implement block functions. Based design requirements, Quartus software will chose appropriate HCell macros implement design functionality. example, Stratix ALMs offer flexible look-up table (LUT) blocks, registers, arithmetic blocks, LAB-wide control signals. HardCopy devices, your design requires these architectural elements, Quartus synthesis tool will design appropriate HCells, resulting improved design performance compared Stratix FPGA prototype. Stratix FPGAs have dedicated blocks implement various functions. Stratix blocks consist multiplier block, adder/subtractor/accumulator block, summation block, input output interfaces, input output registers. HardCopy devices, HCell macros implement Stratix block functionality with area efficiency performance with dedicated blocks Stratix FPGAs. There eight HCell macros which implement eight supported modes operation Stratix block:
multiplier two-multiplier adder complex multiply) four-multiplier adder multiplier two-multiplier adder complex multiply) four-multiplier adder 52-bit multiplier-accumulator multiplier
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HCells
Only HCells that required implement design's functions enabled. HCells needed functions used configurations, which results efficient logic usage. addition area management, placement these HCell macros allows optimized routing performance. example efficient logic area usage seen when comparing multiplier implementation Stratix FPGAs using dedicated block versus implementation HardCopy devices using HCells. Stratix function only calls multiplier, other three multipliers block's adder output block used (Figure 2-2). HardCopy devices, HCell-based logic fabric that used functions used implement other combinational logic, adder, register functions. Figure 2-2. Stratix Block versus HardCopy HCell 18-Bit Multiplier Implementation
Stratix Block Input Registers Output Registers HardCopy HCell-Based Logic Fabric Input Registers Output Registers
Multiplier
Multiplier
Multiplier
These elements implemented using HCell macros. Adder/ Subtractor/ Accumulator Block
Input Registers
Multiplier
Output Registers
Multiplier
Unused logic area used perform other logic functions.
Used portions block Unused portions block
HardCopy devices support Stratix configurations multipliers) Stratix block features, such dynamic sign controls, dynamic addition/subtraction, saturation, rounding, dynamic input shift registers, except dynamic mode switching.
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Dynamic mode switching allows designer each Stratix block dynamically switch between following three modes:
four 18-bit independent multipliers 8-bit multiplier-accumulators 36-bit multiplier
Each half Stratix block separate mode control signals. Since block functions implemented HardCopy devices using HCells, HardCopy devices support dynamic mode switching. this feature used, Quartus software flags implementation does allow migrate design. fitter reports that HardCopy devices compatible with design. migrate your Stratix design HardCopy companion device, disable dynamic switching blocks.
more information Stratix operational modes, refer Stratix Device Handbook. HardCopy memory blocks implement various types memory with without parity, including true dual-port, simple dual-port, single-port RAM, ROM, FIFO buffers. HardCopy devices support same memory functions features Stratix FPGAs. Functionally, memory both devices identical. However, number available memory blocks differs based density (Table 2-3).
Embedded Memory
Table 2-3. HardCopy Embedded Memory Resources Feature
blocks Kbits) M-RAM blocks (512 Kbits) Total bits (bits)
HC210W
875,520
HC210
875,520
HC220
3,059,712
HC230
6,368,256
HC240
8,847,360
Since device functionality fixed HardCopy devices, block contents cannot preloaded initialized with when they configured RAM. When blocks used ROM, they will initialize design's contents. When using non-registered outputs mode HardCopy memory block, outputs power uninitialized. When using registered outputs mode HardCopy memory blocks,
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PLLs Clock Networks
outputs cleared power designer needs take these into consideration when designing logic that might evaluate initial power-up values memory block. HardCopy embedded memory consists M-RAM memory blocks have one-to-one mapping from Stratix M-RAM resources. Table shows size features different blocks.
more information Stratix memory block features, refer Stratix Device Handbook. Both HardCopy enhanced fast PLLs feature rich, supporting advanced capabilities such clock switchover, reconfigurable phase shift, reconfiguration, reconfigurable bandwidth. PLLs used general-purpose clock management, supporting multiplication, division, phase shifting, programmable duty cycle. addition, enhanced PLLs support external clock feedback mode, spread-spectrum clocking, counter cascading. Fast PLLs offer high speed outputs manage high-speed differential interfaces. Stratix features supported HardCopy PLLs.
PLLs Clock Networks
Similar Stratix FPGAs, HardCopy devices also support power-down mode where unused clock networks disabled. HardCopy Stratix clock control blocks support dynamic selection input clock from four possible sources, giving designer flexibility choose from multiple four) clock sources.
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Table 2-4. HardCopy Embedded Memory Features Feature
Maximum performance (1), Total bits (including parity bits) Configurations
(Part Notes (1), (2), M-RAM Blocks
589,824
Blocks
4,608
Parity bits Byte enable Pack mode Address clock enable Single-port memory Simple dual-port memory True dual-port memory Embedded shift register FIFO buffer Simple dual-port mixed width support True dual-port mixed width support Memory initialization file (.mif) Mixed-clock mode Power-up condition Register clears Same-port read-during-write Mixed-port read-during-write
supported, except mode
supported
Outputs unknown Output registers only
Outputs unknown Output registers only
data available positive clock data available positive clock edge edge Outputs unknown data Unknown output
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PLLs Clock Networks
Table 2-4. HardCopy Embedded Memory Features Feature
Note Table 2-4:
(Part Notes (1), (2), M-RAM Blocks
Blocks
Maximum performance information preliminary until device characterization. memory cells power randomly, reads before writes valid. Make sure write memory location before read Even though output register cleared, memory cells power randomly. reads before write valid. Make sure write memory location first before reading Violating setup hold time requirements address registers could corrupt memory contents. This applies both read write operations.
Enhanced Fast PLLs
number PLLs available differs based density (Table 2-5).
Table 2-5. HardCopy PLLs Feature
Enhanced PLLs Fast PLLs
HC210W
HC210
HC220
HC230
HC240
target HardCopy device support same number enhanced PLLs prototyping Stratix FPGA. However, since HardCopy enhanced PLLs fast PLLs offer similar feature (Table page 2-13), fast could used place enhanced PLL. type used design should chosen using Quartus software accommodate resources available HardCopy device. Table shows which PLLs available each device density. Figure shows location each PLL. During prototyping stage using FPGA, must select appropriate number enhanced fast PLLs that will used your HardCopy device. Table ensure that FPGA prototyping design uses same resources available HardCopy device.
Table 2-6. HardCopy PLLs Available Device
HC210W HC210
(Part
Note Enhanced PLLs
Fast PLLs
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Table 2-6. HardCopy PLLs Available Device
HC220 HC230 HC240
(Part
Note Enhanced PLLs
Fast PLLs
Note Table 2-6:
performance HC210W device differ from Stratix FPGA prototype.
Figure 2-3. HardCopy Locations
Notes (1),
CLK[15.12]
FPLL7CLK
FPLL10CLK
CLK[3.0]
CLK[8.11]
PLLs
FPLL8CLK
FPLL9CLK
CLK[7.4]
Notes Figure 2-3:
PLLs located periphery core device. This die-level view device only graphical representation locations.
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PLLs Clock Networks
functionality HardCopy devices remains same Stratix FPGA PLLs. Therefore, HardCopy PLLs support reconfiguration (the dynamically configured user mode). HardCopy enhanced fast PLLs support one-to-one mapping from Stratix resources. Table shows features different PLLs. more information Stratix features, refer Stratix Device Handbook.
Table 2-7. HardCopy Features Feature
Clock multiplication division Phase shift Clock switchover reconfiguration Reconfigurable bandwidth Spread-spectrum clocking Programmable duty cycle Number clock outputs
Enhanced
m/(n post-scale counter) Down 125-ps increments
Fast
m/(n post-scale counter) Down 125-ps increments
Number dedicated external clock outputs Three differential singledper ended Number feedback clock inputs Notes Table 2-7:
enhanced PLLs, range from post-scale counters range from with duty cycle. non-50% duty-cycle clock outputs, post-scale counters range from 256. fast PLLs, range from post-scale counters range from non-50% duty-cycle clock outputs, post-scale counters range from smallest phase shift determined voltage controlled oscillator (VCO) period divided eight. supported phase shift range from HardCopy devices shift output frequencies increments least Smaller degree increments possible depending frequency divide parameters. non-50% duty cycle clock outputs post-scale counters range from 256. HardCopy fast PLLs only support manual clock switchover. clock outputs driven internal clock networks pin. clock outputs fast PLLs drive used external clock output. high-speed differential pins, device uses data channel generate transmitter output clock (txclkout). design uses external feedback input pins, will lose two, fBIN differential) dedicated external clock output pin.
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HardCopy Series Handbook, Volume
Clock Networks
There clock pins (CLK[15.0]) HardCopy devices that drive either global- regional-clock networks. pins drive clock ports data inputs. HardCopy devices provide dedicated global-clock networks regional-clock networks; same Stratix FPGAs. These clocks organized provide unique clock sources device quadrant with skew delay. This clocking scheme provides unique clock domains within entire HardCopy device. Table lists clock resources features available HardCopy devices.
Table 2-8. Clock Network Resources Features Available HardCopy Devices Resources Features
Number global clock networks Number regional clock networks Global clock input sources Regional clock input sources Number unique clock sources quadrant Number unique clock sources entire device Power-down mode Clocking regions high fan-out applications Clock input pins, outputs, logic array Clock input pins, outputs, logic array global clocks regional clocks) global clocks regional clocks) Global- regional-clock networks, dual-regional-clock region Quadrant region, dual-regional, entire device globalor regional-clock networks
Availability
HardCopy devices also support same features Stratix clock control block, which available each global- regional-clock network. control block functions:
Clock source selection (dynamic selection global clocks): user either dynamically select between outputs, between clock pins (CLKp CLKn), combination clock pins outputs. Clock power-down (dynamic clock enable disable): HardCopy devices, dynamically turn clock user-mode.
Structure Features
structure features HardCopy remains same Stratix feature implemented Stratix IOEs migrated Hardcopy IOEs.
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Structure Features
feature HardCopy devices classified three categories:
General purpose IOEs-The most commonly used type designs. Memory Interface IOEs-Includes features interface with common external memory standards. High-speed IOEs-Supports high-speed data transmission reception.
pins Stratix FPGAs support general-purpose standards, which includes LVTTL LVCMOS standards. Stratix FPGAs, clamping diode memory interfaces supported bottom pins, while high-speed interfaces supported left right side pins device. general purpose IOEs HardCopy devices cost saving area efficient advantage. complex memory interface high-speed circuitry removed save area while still offering more commonly-used features. memory interface supports features available general purpose IOE. high-speed also supports same features standards general purpose IOE, except clamping diode (supported bottom general purpose IOEs HC210 HC220 devices). order increase area efficiency HardCopy devices, features available given depends location. Table shows which standards supported different types.
Table 2-9. HardCopy Supported Standards (Part VCCIO Level Standard
3.3-V LVTTL/ LVCMOS 2.5-V LVTTL/ LVCMOS 1.8-V LVTTL/ LVCMOS 1.5-V LVCMOS SSTL-2 class
Type Input
Single-ended Single-ended Single-ended Single-ended Voltage referenced 3.3/2.5 3.3/2.5 1.8/1.5 1.8/1.5
Output
Memory Interface IOEs
General Purpose IOEs
High-Speed IOEs
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Table 2-9. HardCopy Supported Standards (Part VCCIO Level Standard
SSTL-2 class SSTL-18 class SSTL-18 class 1.8-V HSTL class 1.8-V HSTL class 1.5-V HSTL Class 1.5-V HSTL Class PCI/PCI-X Differential SSTL-2 class input Differential SSTL-2 class output Differential SSTL-18 class input Differential SSTL-18 class output 1.8-V differential HSTL class input 1.8-V differential HSTL class output 1.5-V differential HSTL class input 1.5-V differential HSTL class output LVDS HyperTransporttechnology
Type Input
Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Single-ended Pseudo differential Pseudo differential Pseudo differential Pseudo differential Pseudo differential Pseudo Differential Pseudo differential Pseudo Differential Differential Differential 3.3/2.5/ 1.8/1.5 3.3/2.5/ 1.8/1.5 3.3/2.5/ 1.8/1.5 3.3/2.5/ 1.8/1.5
Output
Memory Interface IOEs
General Purpose IOEs
High-Speed IOEs
(4), (4),
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Structure Features
Table 2-9. HardCopy Supported Standards (Part VCCIO Level Standard
LVPECL Notes Table 2-9:
Pseudo-differential HSTL SSTL inputs only positive-polarity input speed path. negative input connected internally. Pseudo-differential HSTL SSTL outputs single-ended outputs with second output programmed inverted. This similar Stratix device implementation. clamping diode only supported pins bottom sides device. This standard only supported DQS, PLL_FB input pins PLL_OUT output pins. This standard only supported bottom PLL_FB input pins bottom PLL_OUT output pins. This standard only supported PLL_FB input pins PLL_OUT output pins. Also supported CLK9 CLK11 pins. This standard only supported PLL_FB input pins. LVPECL input standard supported bottom PLL_FB input pins. LVPECL output standard supported bottom PLL_OUT output pins. LVPECL support similar Stratix devices.
Type Input
Differential 3.3/2.5/ 1.8/1.5
Output
Memory Interface IOEs
General Purpose IOEs
High-Speed IOEs
three types IOEs located different areas device described following sections. HardCopy devices have eight banks, just Stratix FPGAs. Figures through show which type each bank supports.
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Figure 2-4. Type Support HC210 HC220 Devices
Bank Memory Interface IOEs Bank
Notes (1),
Bank Memory Interface IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL PCI/PCI-X standards. Bank High-Speed IOEs CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards. Bank General-Purpose IOEs
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS HyperTransport Technology
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS &1.5-V LVCMOS
Bank High-Speed IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS PCI/PCI-X standards. CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL.
Bank General-Purpose IOEs
Bank General Purpose IOEs
Bank
Bank General Purpose IOEs
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Structure Features
Figure 2-5. Type Support HC230 Devices
Bank Memory Interface IOEs
Notes (1),
Bank Bank Bank Memory Interface IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL PCI/PCI-X standards. Bank High-Speed IOEs CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards. Bank General-Purpose IOEs
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS HyperTransport Technology
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS &1.5-V LVCMOS
Bank High-Speed IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS PCI/PCI-X standards. CLK, PLL_FB input pins, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST, PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards.
Bank General-Purpose IOEs
Bank Memory Interface IOEs
Bank Bank
Bank Memory Interface IOEs
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HardCopy Series Handbook, Volume
Figure 2-6. Type Support HC240 Devices
Bank Memory Interface IOEs
Notes (1),
Bank Bank Bank Memory Interface IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL PCI/PCI-X standards. Bank High-Speed IOEs CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards. Bank High-Speed IOEs
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS HyperTransport Technology
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS HyperTransport Technology
Bank High-Speed IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS PCI/PCI-X standards. CLK, PLL_FB input pins SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST, PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards.
Bank High-Speed IOEs
Bank Memory Interface IOEs
Bank Bank
Bank Memory Interface IOEs
Notes Figures through 2-6:
addition supporting external memory interfaces, memory interface IOEs have same features general purpose IOEs. addition supporting high-speed interfaces, high-speed IOEs have same features general purpose IOEs, except clamping diode LVPECL clock input support. This view silicon which corresponds reverse view flip-chip packages. graphical representation only.
When planning placement designs targeting HardCopy devices, care should taken ensure same standards supported same HardCopy banks Stratix banks.
General Purpose
general purpose IOEs HC210 HC220 devices located right side bottom device. general purpose IOEs HC230 devices located right side device. (Directions based view silicon die.) HC240 devices have general purpose IOEs. general purpose functionality supported memory interface IOEs these devices. high-speed IOEs also
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Structure Features
provide same features general purpose IOEs except clamping diode. Stratix FPGAs, IOEs support general purpose features except diode, which only supported bottom pins. general purpose many features, including:
Dedicated single-ended buffers 3.3-V, 64-bit, compliance 3.3-V, 64-bit, PCI-X compliance JTAG boundary-scan test (BST) support On-chip driver series termination (non-calibrated) Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs clamping diode (supported bottom pins only) Double data rate (DDR) registers
General purpose IOEs support following standards:
3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V 3.3-V PCI-X mode
general purpose PLL_FB input pins PLL_OUT output pins support following standards:
LVDS HyperTransport technology LVPECL input clocks PLL_OUT only)
programmable drive strengths available vary depending standard being used listed Table 2-10.
Table 2-10. Programmable Drive Strength Support General-Purpose IOEs (Part Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS
Programmable Drive Strength Options (mA)
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HardCopy Series Handbook, Volume
Table 2-10. Programmable Drive Strength Support General-Purpose IOEs (Part Standard
LVTTL/LVCMOS LVCMOS
Programmable Drive Strength Options (mA)
General purpose IOEs support non-calibrated on-chip series termination. on-chip series termination available 3.3-V 2.5-V standards. on-chip series termination available 1.8- 1.5-V standards (pending characterization).
Memory Interface
Memory interface IOEs HC210 HC220 devices located device. Memory interface IOEs HC230 HC240 devices located bottom device. Stratix FPGAs, bottom IOEs support memory interface features. memory interface many features, including:
Dedicated single-ended buffers 3.3-V, 64-bit, compliance 3.3-V, 64-bit, PCI-X compliance JTAG support On-chip driver series termination VREF pins Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs clamping diode pins Double data rate (DDR) registers
following standards supported when using memory interface IOEs used interface external memory, including DDR2 SDRAM, QDRII, RLDRAM SRAM:
3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V 3.3-V PCI-X mode
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Structure Features
SSTL-2 class SSTL-18 class 1.8-V HSTL class 1.5-V HSTL class
memory interface DQS, CLK, PLL_FB input pins PLL_OUT output pins support following standards:
LVTTL/LVCMOS SSTL-2 class SSTL-18 class 1.8-V HSTL class 1.5-V HSTL class Differential SSTL-2 class Differential SSTL-18 class 1.8-V differential HSTL class 1.5-V differential HSTL class LVDS (not supported pins) HyperTransport technology (not supported pins) LVPECL input clocks PLL_OUT only (not supported pins)
Pseudo-differential HSTL SSTL inputs supported clock pins, while outputs supported dedicated PLL_OUT pins. Pseudo-differential HSTL SSTL standards single-ended outputs with second output programmed inverted. Pseudo-differential HSTL SSTL inputs treat differential inputs single-ended HSTL SSTL inputs only decode them. This support same Stratix FPGAs. functionality circuitry HardCopy devices same Stratix FPGAs. Table 2-11 shows number DQS/DQ groups supported each HardCopy device density package.
Table 2-11. Mode Support (Part Device
HC210W HC210 HC220
Package
484-pin FineLine (Wire Bond) 484-pin FineLine 672-pin FineLine 780-pin FineLine
Number Number Number Number Groups Groups Groups Groups
HC230
1,020-pin FineLine
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HardCopy Series Handbook, Volume
Table 2-11. Mode Support (Part Device
HC240
Package
1,020-pin FineLine 1,508-pin FineLine
Number Number Number Number Groups Groups Groups Groups
programmable drive strengths available vary depending standard used. options listed Table 2-12.
Table 2-12. Programmable Drive Strength Support Memory Interface IOEs Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS SSTL-2 class SSTL-2 class SSTL-18 class SSTL-18 class 1.8-V HSTL class 1.8-V HSTL class 1.5-V HSTL class 1.5-V HSTL class
Programmable Drive Strength Options (mA)
Memory interface IOEs support both non-calibrated calibrated on-chip series termination. on-chip series termination available 3.3-, 2.5-, 1.8-V standards. on-chip series termination available 1.5- 1.2-V standards (pending characterization). on-chip series termination enabled, programmable drive strength support available.
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Structure Features
High-Speed
High-speed IOEs HC210, HC220, HC230 devices located left side device. High-speed IOEs HC240 devices located left right sides device. (Directions based view silicon die.) Unlike Stratix left right side pins, HardCopy left right side pins support SSTL HSTL standards clamping diode. Stratix FPGAs, right left IOEs support high-speed features. high-speed many features, including:
Dedicated single-ended buffers Differential buffer JTAG support On-chip driver series termination (non-calibrated) On-chip termination differential standards Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs Transmit serializer Receive deserializer Dynamic phase alignment (DPA) Double data rate (DDR) registers
following standards supported when using high-speed IOEs:
3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS HyperTransport technology
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HardCopy Series Handbook, Volume
SERDES circuitry functionality same HardCopy devices Stratix FPGAs. HardCopy devices support differential standards rates Gbps when using DPA, rates Mbps when using DPA. Table 2-13 provides number differential channels HardCopy device.
Table 2-13. Number Differential Channels HardCopy Devices HC210W Channel 484-Pin FineLine (WireBond)
Notes (1), HC230 HC240 1,020-Pin FineLine
HC210 484-Pin FineLine
HC220 672-Pin FineLine
780-Pin FineLine
1,020-Pin FineLine
1,508-Pin FineLine
Transmitter channels Receiver channels Notes Table 2-13:
count does include dedicated input output pins. total number receiver channels includes non-dedicated clock channels that optionally used data channels.
HardCopy high-speed IOEs, which left and/or right sides device, support fewer programmable drive strengths than Stratix side IOEs. programmable drive strengths available vary depending standard being used. options listed Table 2-14.
Table 2-14. Programmable Drive Strength Support High-Speed IOEs Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS
Programmable Drive Strength Options (mA)
High-speed IOEs support non-calibrated on-chip series termination differential termination receiver channels. on-chip series termination available 3.3- 2.5-V standards. on-chip series termination available 1.8- 1.5-V standards (pending characterization).
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Altera Corporation June 2007
Power-Up Modes
Power-Up Modes
functionality structured ASICs determined before they produced. Therefore, they require programmability. HardCopy structured ASICs follow same principle, enabling traditional ASIC-like power Although prototyping FPGAs require configuration upon power HardCopy structured ASICs need configured. HardCopy devices support configuration designers should take this into account prototyping-to-production development process. HardCopy device does require configuration device, must ensure that that nCONFIG nSTATUS pins high after power HardCopy devices support FPGA configuration emulation other configuration modes, including remote system upgrades design security using configuration bitstream encryption.
HardCopy devices support both instant instant after power-up modes. instant power-up mode, HardCopy device available shortly after device powers safe operating voltage. on-chip power-on reset (POR) circuit will reset registers. nCE, nCONFIG, nSTATUS signals must appropriate logic levels CONF_DONE output tristated once elapsed. This option similar ASIC's functionality upon power most likely scenario production. instant after power-up mode, HardCopy device behaves similarly instant mode, except that there additional delay during which time device will held reset. CONF_DONE output pulled during this time, then tri-stated after have elapsed.
more information about which power-up modes HardCopy devices support, refer Power-Up Modes Configuration Emulation HardCopy Series Devices chapter HardCopy Series Handbook.
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HardCopy Series Handbook, Volume
Document Revision History
Table 2-15 shows revision history this chapter.
Table 2-15.Document Revision History Date Document Version
June 2007, v2.4 December 2006 v2.3 March 2006, v2.2 October 2005, v2.1 2005, v2.0
Changes Made
Added Note Table 2-4. Updated Table 2-1, Table 2-4, Table 2-11. Added revision history. Updated Table 2-1, Table 2-9, Table 2-13. Updated Figure Figure 2-6.
Summary Changes
Updated graphics.
Added Table 2-1. Updated HCell information functions Functional Description section. Updated Table 2-9. Updated Figures 2-4, 2-5, 2-6.
January 2005, v1.0
Added document HardCopy Series Handbook.
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Altera Corporation June 2007
Boundary-Scan Support
H51017-2.3
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
HardCopy® structured ASICs provide Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that complies with IEEE Std. 1149.1-1990 specification. architecture offers capability efficiently test components printed circuit boards (PCBs) with tight lead spacing testing connections, without using physical test probes, capturing functional data while device normal operation. Boundary-scan cells device force signals onto pins, capture data from core logic signals. Forced test data serially shifted into boundary-scan cells. Captured data serially shifted externally compared expected results. device using JTAG interface uses four required pins, TDI, TDO, TMS, TCK, optional pin, TRST. internal weak pull-down resistor, while TDI, TMS, TRST pins have weak internal pull-up resistors. output powered VCCIO. HardCopy devices support JTAG instructions shown Table 3-1.
Table 3-1. HardCopy JTAG Instructions (Part JTAG Instruction
SAMPLE/PRELOAD
Instruction Code
0000 0101
Description
Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. Allows external circuitry board-level interconnects tested forcing test pattern output pins capturing test results input pins. Places 1-bit BYPASS register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation.
EXTEST
0000 1111
BYPASS
1111 1111
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HardCopy Series Handbook, Volume
Table 3-1. HardCopy JTAG Instructions (Part JTAG Instruction
USERCODE
Instruction Code
0000 0111
Description
Selects 32-bit USERCODE register places between pins, allowing USERCODE serially shifted TDO. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. Places 1-bit BYPASS register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation, while tri-stating pins. Places 1-bit BYPASS register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation while holding pins state defined data boundary-scan register.
IDCODE
0000 0110
HIGHZ
0000 1011
CLAMP
0000 1010
Note Table 3-1:
hold weak pull-up resistor features override high-impedance state HIGHZ, CLAMP, EXTEST.
BSDL files HardCopy devices different from corresponding Stratix® FPGAs. more information, receive BSDL files IEEE Std. 1149.1- compliant Hardcopy devices, visit Altera website www.altera.com. HardCopy device instruction register length bits USERCODE register length bits. USERCODE registers reprogrammable mask-programmed. designer choose appropriate sequence which will programmed into USERCODE registers.
Preliminary
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IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Tables show boundary-scan register length device IDCODE information HardCopy devices.
Table 3-2. HardCopy Boundary-Scan Register Length Device
HC210W HC210 HC220 HC230 HC240
Boundary-Scan Register Length
1050 1050 1530 2154 2910
Table 3-3. 32-Bit HardCopy Device IDCODE IDCODE Bits) Device
HC210W HC210 HC220 HC230 HC240 Notes Table 3-3:
most significant (MSB) left. least significant (LSB) IDCODE always
Version Bits)
0000 0000 0000 0000 0000
Part Number Bits)
0010 0000 1100 0001 0010 0000 1100 0010 0010 0000 1100 0011 0010 0000 1100 0100 0010 0000 1100 0101
Manufacturer Identity Bits)
0110 1110 0110 1110 0110 1110 0110 1110 0110 1110
Bit)
Boundary-Scan Test (BST) HardCopy Devices
order boundary-scan test HardCopy devices, need files: generic HardCopy BSDL file download from Altera website www.altera.com. file your design from Quartus software.
With these files, must through tool called BSDLCustomizer.
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Preliminary
HardCopy Series Handbook, Volume
BSDLCustomizer script which used modify BSDL file's port definitions boundary-scan chain groups' attributes according design assignments from Quartus software file. Once generic BSDL file your file through BSDLCustomizer tool, modified BSDL file created which should used boundary-scan test. Before running boundary scan test your board make sure that nCONFIG externally pulled that nSTATUS low. more information BSDLCustomizer tool, refer BSDLCustomizer User Guide that download with BSDLCustomizer tool from Altera website www.altera.com. Figure shows timing requirements JTAG signals. Figure 3-1. HardCopy JTAG Waveforms
tJPZX JPCO JPXZ JPSU
Table shows JTAG timing parameters values HardCopy devices.
Table 3-4. HardCopy JTAG Timing Parameters Values (Part Symbol
Parameter
clock period clock high time clock time
JTAG port setup time
Unit
Preliminary
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Document Revision History
Table 3-4. HardCopy JTAG Timing Parameters Values (Part Symbol
Parameter
JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time
Unit
more information JTAG boundary-scan testing, refer IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices. Like Stratix FPGAs, HardCopy devices support SignalTap® embedded logic analyzer, which monitors design operation over period time through JTAG interface. SignalTap logic analyzer useful feature during FPGA prototyping phase, should removed needed once design been migrated HardCopy device. HardCopy mask programmed device, Signal logic cannot eliminated after HardCopy device fabricated.
Document Revision History
Table shows revision history this chapter.
Table 3-5. Document Revision History (Part Date Document Version
June 2007, v2.3
Changes Made
Added resource information Figure changes section Boundary-Scan Test (BST) HardCopy devices. Minor updates Quartus 6.1.0 software version Added revision history
Summary Changes
December 2006 v2.2 October 2005, v2.1
Updated Quartus software version.
Updated graphics.
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Preliminary
HardCopy Series Handbook, Volume
Table 3-5. Document Revision History (Part Date Document Version
2005, v2.0 January 2005 v1.0 Updated Table 3-2. Added document HardCopy Series Handbook.
Changes Made
Summary Changes
Preliminary
Altera Corporation June 2007
Switching Specifications Operating Conditions
H51018-3.1
Introduction
This chapter provides preliminary information absolute maximum ratings, recommended operating conditions, electrical characteristics, other specifications HardCopy® devices. HardCopy devices offered both commercial industrial grades. parameter limits representative worst-case supply voltage junction temperature conditions. Unless otherwise noted, parameter values this chapter apply HardCopy devices. Table contains absolute maximum ratings HardCopy device family.
Absolute Maximum Ratings
Table 4-1. HardCopy Device Absolute Maximum Ratings Symbol
VCCINT VCCIO VCCPD VCCA VCCD IOUT TSTG
Notes (1), (2), Minimum
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Parameter
Supply voltage Supply voltage Supply voltage Analog power supply PLLs Digital power supply PLLs input voltage(4) output current, Storage temperature Junction temperature
Conditions
With respect ground With respect ground With respect ground With respect ground With respect ground
Maximum
Unit
bias Ball-grid array (BGA) packages under bias
Notes Table 4-1:
Refer Operating Requirements Altera Devices Data Sheet more information. Conditions beyond those listed Table cause permanent damage device. Additionally, device operation absolute maximum ratings extended periods time have adverse effects device. Supply voltage specifications apply voltage readings taken device pins, power supply. During transitions, inputs overshoot voltage shown Table based upon input duty cycle. case equivalent 100% duty cycle. During transitions, inputs undershoot -2.0 input currents less than periods shorter than
Altera Corporation June 2007
Preliminary
HardCopy Series Handbook, Volume
Table 4-2. Maximum Duty Cycles Voltage Transitions
Maximum Duty Cycles
100%
Recommended Operating Conditions
Table contains HardCopy device family recommended operating conditions.
Table 4-3. HardCopy Device Recommended Operating Conditions Symbol
VCCINT VCCIO
Note (Part Minimum Maximum Unit
1.15 3.135 (3.0) 2.375 1.71 1.425 3.135 1.25 3.465 (3.6) 2.625 1.89 1.575 3.465
Parameter
Supply voltage internal logic input buffers Supply voltage output buffers, 3.3-V operation Supply voltage output buffers, 2.5-V operation Supply voltage output buffers, 1.8-V operation Supply voltage output buffers, 1.5-V operation
Conditions
rise time rise time (2), rise time rise time rise time rise time
VCCPD
Supply voltage pre-drivers well configuration JTAG buffers Analog power supply PLLs Digital power supply PLLs Input voltage Output voltage
VCCA VCCD
rise time rise time (4),
1.15 1.15 -0.5
1.25 1.25 VCCIO
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Electrical Characteristics
Table 4-3. HardCopy Device Recommended Operating Conditions Symbol
Note (Part Minimum Maximum Unit
Parameter
Operating junction temperature
Conditions
commercial industrial
Notes Table 4-3:
Supply voltage specifications apply voltage readings taken device pins, power supply. Maximum rise time must rise monotonically. VCCPD must ramp-up from within VCCPD ramped within this specified time, HardCopy device will power successfully. During transitions, inputs overshoot voltage shown Table based upon input duty cycle. case equivalent 100% duty cycle. During transitions, inputs undershoot -2.0 input currents less than periods shorter than pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT, VCCPD, VCCIO powered. VCCIO maximum minimum conditions PCI-X shown parentheses.
Electrical Characteristics
Table shows HardCopy device family electrical characteristics.
Table 4-4. HardCopy Device Operating Conditions Symbol
ICCINT0
Note (Part Minimum Typical Maximum
0.09 0.09 0.19 0.34 0.52
Parameter
Input leakage current Tri-stated leakage current
Conditions
VCCIO VCCIO
Device
Unit
VCCINT supply current ground, (standby) load, toggling inputs
HC210W HC210 HC220 HC230 HC240
ICCPD0
VCCPD supply current (standby)
ground, load, toggling inputs VCCPD
HC210W HC210 HC220 HC230 HC240
Altera Corporation June 2007
HardCopy Series Handbook, Volume
Table 4-4. HardCopy Device Operating Conditions Symbol
ICCIO0
Note (Part Minimum Typical Maximum
Parameter
VCCIO supply current (standby)
Conditions
ground, load, toggling inputs
Device
HC210W HC210 HC220 HC230 HC240
Unit
RCONF(4)
Value pull-up resistor before during configuration
VCCIO VCCIO VCCIO VCCIO VCCIO
Recommended value external pull-down resistor before during configuration Notes Table 4-4:
Typical values VCCINT VCCIO 1.5-, 1.8-, 2.5-, 3.3-V. This value specified normal device operation. value vary during power-up. This applies VCCIO settings (3.3-, 2.5-, 1.8-, 1.5-V). This specification preliminary pending further device characterization. pull-up resistor values will lower external source drives higher than VCCIO. Maximum values depend actual design utilization. PowerPlay Early Power Estimator (available www.altera.com) Quartus PowerPlay Power Analyzer feature maximum values.
Standard Specifications
Tables through 4-27 show HardCopy device family standard specifications.
Table 4-5. LVTTL Specifications (Part Symbol
VCCIO
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage
Conditions
Minimum
3.135 -0.3
Maximum
3.465
Unit
(2),
Altera Corporation June 2007
Standard Specifications
Table 4-5. LVTTL Specifications (Part Symbol
Parameter
Low-level output voltage
Conditions
(2),
Minimum
Maximum
0.45
Unit
Notes Table 4-5:
HardCopy devices comply narrow range supply voltage specified EIA/JEDEC Standard, JESD8-B. Drive strength programmable according values Table 4-10, Table 4-12, Table 4-14. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-6. LVCMOS Specifications Symbol
VCCIO
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.135 -0.3
Maximum
3.465
Unit
VCCIO 3.0, -0.1 (2), VCCIO 3.0, (2),
VCCIO
Notes Table 4-6:
HardCopy devices comply narrow range supply voltage specified EIA/JEDEC Standard, JESD8-B. Drive strength programmable according values Tables 2-10, 2-12, and2-14. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-7. 2.5-V Specifications (Part Symbol
VCCIO
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage
Conditions
Minimum
2.375 -0.3
Maximum
2.625
Unit
(2),
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HardCopy Series Handbook, Volume
Table 4-7. 2.5-V Specifications (Part Symbol
Parameter
Low-level output voltage
Conditions
(2),
Minimum
Maximum
Unit
Notes Table 4-7:
HardCopy devices VCCIO voltage-level support narrower than defined normal range EIA/JEDEC Standard. Drive strength programmable according values Tables 2-10, 2-12, and2-14. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-8. 1.8-V Specifications Symbol
VCCIO
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.65 VCCIO -0.3
Maximum
1.89 2.25 0.35 VCCIO
Unit
(2), (2),
VCCIO 0.45 0.45
Notes Table 4-8:
HardCopy devices VCCIO voltage-level support narrower than defined normal range EIA/JEDEC Standard. Drive strength programmable according values Tables 2-10, 2-12, and2-14. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-9. 1.5-V Specifications (Part Symbol
VCCIO
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage
Conditions
Minimum
1.425 0.65 VCCIO -0.3
Maximum
1.575 VCCIO 0.35 VCCIO
Unit
(2),
0.75 VCCIO
Altera Corporation June 2007
Standard Specifications
Table 4-9. 1.5-V Specifications (Part Symbol
Parameter
Low-level output voltage
Conditions
(2),
Minimum
Maximum
0.25 VCCIO
Unit
Notes Table 4-9:
HardCopy devices VCCIO voltage-level support narrower than defined normal range EIA/JEDEC Standard. Drive strength programmable according values Tables 2-10, 2-12, and2-14. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Figure Figure show receiver input transmitter waveforms, respectively, differential LVPECL HyperTransport technology. Figure 4-1. Receiver Input Waveforms Differential Standards
Single-Ended Waveform Positive Channel Negative Channel Ground
Differential Waveform (Mathematical Function Positive Negative Channel)
p-n=0V (Peak-to-peak)
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HardCopy Series Handbook, Volume
Figure 4-2. Transmiter Output Waveforms Differential Standards
Single-Ended Waveform Positive Channel Negative Channel Ground
Differential Waveform (Mathematical Function Positive Negative Channel)
p-n=0V
Table 4-10. 2.5-V LVDS Specifications Symbol
VCCIO
Parameter
supply voltage banks that support high-speed IOEs (1), Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (singleended) Output common mode voltage Receiver differential input discrete resistor (external HardCopy devices)
Conditions
Minimum
2.375
Typical
Maximum
2.625
Unit
VICM VOCM
1.125
1,250
1,800 1.375
Notes Table 4-10:
IOEs elements. information which banks support high-speed IOEs, refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook.
Altera Corporation June 2007
Standard Specifications
Table 4-11. 3.3-V LVDS Specifications Note Symbol
VCCIO VICM VOCM
Parameter
Output feedback pins banks Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input discrete resistor (external HardCopy devices)
Conditions
Minimum
3.135
Typical
1,250
Maximum
3.465 1,800 1.570
Unit
0.84
Notes Table 4-11:
Like Stratix devices, 3.3-V LVDS supported bottom clock input differential buffers, clock output feedback pins. bottom clock input differential buffers banks powered VCCINT, VCCIO. clock output feedback differential buffers powered VCC_PLLOUT. differential clock output feedback operation, connect VCC_PLLOUT
Table 4-12. LVPECL Specifications (Part Symbol
VCCIO
Note Minimum
3.135
Parameter
supply voltage banks that support highspeed IOEs Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage
Conditions
Typical
Maximum
3.465
Unit
(peakto-peak) VICM VOCM
1,000
1.650
2.275
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HardCopy Series Handbook, Volume
Table 4-12. LVPECL Specifications (Part Symbol
Note Minimum
Parameter
Receiver differential input discrete resistor (external HardCopy devices)
Conditions
Typical
Maximum
Unit
Notes Table 4-12:
Like Stratix devices, LVPECL supported bottom clock input differential buffers, clock output feedback pins. bottom clock input differential buffers banks powered VCCINT, VCCIO. clock output feedback differential buffers powered VCC_PLLOUT. differential clock output feedback operation, connect VCC_PLLOUT
Table 4-13. HyperTransport Technology Specifications Symbol
VCCIO
Parameter
supply voltage banks that support highspeed IOEs (1), Output feedback pins banks
Conditions
Minimum
2.375
Typical
Maximum
2.625
Unit
3.135
3.465
(peakto-peak) VICM VOCM VOCM
Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change between high Output common mode voltage Change VOCM between high Receiver differential input discrete resistor (external HardCopy devices)
Notes Table 4-13:
information which banks support high-speed IOEs, refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook. bottom clock input differential buffers banks powered VCCINT, VCCIO. clock output feedback differential buffers powered VCC_PLLOUT. differential clock output feedback operation, connect VCC_PLLOUT
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Standard Specifications
Table 4-14. 3.3-V Specifications Symbol
VCCIO
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VCCIO -0.3
Typical
Maximum
VCCIO VCCIO
Unit
IOUT -500 IOUT 1,500
VCCIO VCCIO
Table 4-15. PCI-X Mode Specifications Symbol
VCCIO VIPU
Parameter
Output-supply voltage High-level input voltage Low-level input voltage Input pull-up voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VCCIO -0.3 VCCIO
Typical
Maximum
VCCIO 0.35 VCCIO
Unit
IOUT -500 IOUT 1,500
VCCIO VCCIO
Table 4-16. SSTL-18 Class Specifications (Part Symbol
VCCIO VREF VIH(DC) VIL(DC) VIH(AC) VIL(AC)
Parameter
Output-supply voltage Reference voltage Termination voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage
Conditions
Minimum
1.71 0.855 VREF 0.04 VREF 0.125
Typical
VREF
Maximum
1.89 0.945 VREF 0.04
Unit
VREF 0.125 VREF 0.25 VREF 0.25 -6.7 (1), 0.475
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HardCopy Series Handbook, Volume
Table 4-16. SSTL-18 Class Specifications (Part Symbol
Parameter
Low-level output voltage
Conditions
(1),
Minimum
Typical
Maximum
0.475
Unit
Notes Table 4-16:
This specification supported across programmable drive settings available this standard shown Structure Features section located Description, Architecture, Features chapter volume HardCopy Series Devices Handbook. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-17. SSTL-18 Class Specifications Symbol
VCCIO VREF VIH(DC) VIL(DC) VIH(AC) VIL(AC)
Parameter
Output-supply voltage Reference voltage Termination voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.855 VREF 0.04 VREF 0.125
Typical
VREF
Maximum
1.89 0.945 VREF 0.04
Unit
VREF 0.125 VREF 0.25 VREF 0.25 -13.4 (1), 13.4 (1), VTT- 0.28 0.28
Notes Table 4-17:
This specification supported across programmable drive settings available this standard shown Structure Features section located Description, Architecture, Features chapter volume HardCopy Series Devices Handbook. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-18. SSTL-18 Differential Specifications (Part Symbol
VCCIO VSWING(DC)
Parameter
Output-supply voltage differential input voltage
Conditions
Minimum
1.71 0.25
Typical
Maximum
1.89
Unit
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Altera Corporation June 2007
Standard Specifications
Table 4-18. SSTL-18 Differential Specifications (Part Symbol
VX(AC) VSWING(AC) VISO VISO VOX(AC)
Parameter
differential input cross point voltage differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation differential cross point voltage
Conditions
Minimum
(VCCIO/2) 0.175
Typical
Maximum
(VCCIO/2) 0.175
Unit
VCCIO ±200 (VCCIO/2) 0.125 (VCCIO/2) 0.125
Table 4-19. SSTL-2 Class Specifications Symbol
VCCIO VREF (DC) (DC) (AC) (AC)
Parameter
Output-supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.188 VREF 0.18 -0.3 VREF 0.35
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.313 VREF 0.18
Unit
VREF 0.35 -8.1 (1), (1), 0.57 0.57
Notes Table 4-19:
This specification supported across programmable drive settings available this standard shown Structure Features section Description, Architecture, Features chapter volume HardCopy Series Devices Handbook. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
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HardCopy Series Handbook, Volume
Table 4-20. SSTL-2 Class Specifications Symbol
VCCIO VREF (DC) (DC) (AC) (AC)
Parameter
Output-supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.188 VREF 0.18 -0.3 VREF 0.35
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.313 VCCIO VREF 0.18
Unit
VREF 0.35 -16.4 (1), 16.4 (1), 0.76 0.76
Notes Table 4-20:
This specification supported across programmable drive settings available this standard shown Structure Features section located Description, Architecture, Features chapter volume HardCopy Series Devices Handbook. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-21. SSTL-2 Differential Specifications Symbol
VCCIO VSWING (DC) (AC) VSWING (AC) VISO VISO (AC)
Parameter
Output-supply voltage differential input voltage differential input cross point voltage differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation differential output cross point voltage
Conditions
Minimum
2.375 0.36 (VCCIO/2)
Typical
Maximum
2.625
Unit
(VCCIO/2)
VCCIO ±200 (VCCIO/2) (VCCIO/2)
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Altera Corporation June 2007
Standard Specifications
Table 4-22. 1.5-V HSTL Class Specifications Symbol
VCCIO VREF (DC) (DC) (AC) VIL(AC)
Parameter
Output-supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.425 0.713 0.713 VREF -0.3 VREF
Typical
0.75 0.75
Maximum
1.575 0.788 0.788
Unit
VREF
VREF (1), (1), VCCIO
Notes Table 4-22:
This specification supported across programmable drive settings available this standard shown Structure Features section located Description, Architecture, Features chapter voume HardCopy Series Devices Handbook. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-23. 1.5-V HSTL Class Specifications (Part Symbol
VCCIO VREF (DC) (DC) (AC) (AC)
Parameter
Output-supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output voltage
Conditions
Minimum
1.425 0.713 0.713 VREF VREF
Typical
0.75 0.75
Maximum
1.575 0.788 0.788
Unit
VREF
VREF (1), VCCIO
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HardCopy Series Handbook, Volume
Table 4-23. 1.5-V HSTL Class Specifications (Part Symbol
Parameter
Low-level output voltage
Conditions
(1),
Minimum
Typical
Maximum
Unit
Notes Table 4-23:
This specification supported across programmable drive settings available this standard shown inthe Structure Features section Description, Architecture, Features chapter volume HardCopy Series Devices Handbook. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-24. 1.5-V Differential HSTL Specifications Symbol
VCCIO VDIF (DC) (DC) VDIF (AC) (AC)
Parameter
supply voltage input differential voltage common mode input voltage differential input voltage differential cross point voltage
Conditions
Minimum
1.425 0.68 0.68
Typical
Maximum
1.575
Unit
Table 4-25. 1.8-V HSTL Class Specifications (Part Symbol
VCCIO VREF (DC) (DC) VIH( (AC)
Parameter
Output-supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input low-level input voltage High-level output voltage
Conditions
Minimum
1.71 0.85 0.85 VREF VREF
Typical
Maximum
1.89 0.95 0.95
Unit
VREF
VREF (1), VCCIO
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Altera Corporation June 2007
Standard Specifications
Table 4-25. 1.8-V HSTL Class Specifications (Part Symbol
Parameter
Low-level output voltage
Conditions
(1),
Minimum
Typical
Maximum
Unit
Notes Table 4-25:
This specification supported across programmable drive settings available this standard shown Structure Features section located Description, Architecture, Features chapter HardCopy Series Devices Handbook. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-26. 1.8-V HSTL Class Specifications Symbol
VCCIO VREF (DC) (DC) (AC) (AC)
Parameter
Output-supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.85 0.85 VREF -0.3 VREF
Typical
Maximum
1.89 0.95 0.95
Unit
VREF
VREF (1), IOL= (1), VCCIO
Notes Table 4-26:
This specification supported across programmable drive settings available this standard shown Structure Features section located Description, Architecture, Features chapter volume HardCopy Series Devices Handbook. Drive strength varies based location. Refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook more information.
Table 4-27. 1.8-V Differential HSTL Specifications (Part Symbol
VCCIO VDIF (DC) (DC)
Parameter
supply voltage input differential voltage common mode input voltage
Conditions
Minimum
1.71 0.78
Typical
Maximum
1.89 VCCIO 1.12
Unit
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
Table 4-27. 1.8-V Differential HSTL Specifications (Part Symbol
VDIF (AC) (AC)
Parameter
differential input voltage differential cross point voltage
Conditions
Minimum
0.68
Typical
Maximum
VCCIO
Unit
Hold Specifications
Table 4-28 shows HardCopy device family hold specifications.
Table 4-28. Hold Parameters
VCCIO Level Parameter sustaining current High sustaining current overdrive current Conditions
(maximum)
Unit
(minimum) VCCIO
-160 0.50 1.00 0.68
-200 1.07 0.70
-300 1.70 0.80
-500 2.00
High overdrive current VCCIO Bus-hold trip point
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Altera Corporation June 2007
On-Chip Termination Specifications
On-Chip Termination Specifications
Table 4-29 defines specification internal termination specification when using series differential on-chip termination HC210W devices only.
Table 4-29. Series On-Chip Termination Specification Banks Supporting Memory Interface IOEs HC210W Notes (1), (2), Resistance Tolerance Symbol
3.3/2.5
Description
Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting)
Conditions
3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5
Commercial
Industrial
Unit
3.3/2.5
Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting)
Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
Notes Table 4-29:
information which banks support memory interface IOEs, refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook. resistance tolerances calibrated SOCT POCT time initial calibration. temperature voltage changes over time, tolerance also change. This table applies only HC210W device.
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HardCopy Series Handbook, Volume
Tables 4-30 4-31 define specification internal termination specification when using series differential on-chip termination.
Table 4-30. Series On-Chip Termination Specification Banks Supporting Memory Interface IOEs Notes (1), (2), Resistance Tolerance Symbol
3.3/2.5
Description
Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting)
Conditions
3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5
Commercial
Industrial
Unit
3.3/2.5
Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting)
Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
Notes Table 4-30:
information which banks support memory interface IOEs, refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook. resistance tolerances calibrated SOCT POCT time initial calibration. temperature voltage changes over time, tolerance also change. This table applies only HC210, HC220, HC230 HC240 devices.
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Altera Corporation June 2007
Capacitance
Table 4-31. Series Differential On-Chip Termination Specification Banks Supporting HighSpeed General Purpose IOEs Notes (1), (3), Resistance Tolerance Symbol
3.3/2.5
Description
Internal series termination without calibration (25- setting)
Conditions
VCCIO 3.3/2.5 VCCIO 3.3/2.5/1.8 CCIO
Commercial
Industrial
Unit
Internal series termination without 3.3/2.5/1.8 calibration (50- setting) Internal series termination without calibration (50- setting) Internal differential termination LVDS HyperTransport technology
Notes Table 4-31:
information which banks support high-speed IOEs, refer Description, Architecture, Features chapter HardCopy Device Family Data Sheet section volume HardCopy Series Handbook. only supported high-speed IOEs. resistance tolerances calibrated SOCT POCT time initial calibration. temperature voltage changes over time, tolerance also change. This table applies only HC210, HC220, HC230, HC240 devices.
Capacitance
Table 4-32 shows HardCopy device family capacitance.
Table 4-32. HardCopy Device Capacitance Symbol
CGPIO
Note (Part HC210W Typical
Parameter
Input capacitance pins banks supporting general-purpose IOEs. Input capacitance pins banks supporting memory interface IOEs. Input capacitance pins banks supporting high-speed IOEs. Input capacitance top/bottom clock input pins CLK[4.7] CLK[12.15].
HC210, HC220, HC230, HC240 Typical
Unit
CMIIO
CHSIO CCLKTB
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HardCopy Series Handbook, Volume
Table 4-32. HardCopy Device Capacitance Symbol
CCLKLR CCLKLR+ COUTFB
Note (Part HC210W Typical
Parameter
Input capacitance left/right clock inputs CLK0, CLK2, CLK8, CLK10. Input capacitance left/right clock inputs CLK1, CLK3, CLK9, CLK11. Input capacitance dual-purpose clock output/feedback pins banks
HC210, HC220, HC230, HC240 Typical
Unit
Note Table 4-32:
Capacitance sample-tested only. Capacitance measured using time-domain reflections (TDR). Measurement accuracy within
Maximum Input Clock Rates
Tables 4-33 4-34 show maximum input clocking rates HardCopy I/Os.
Table 4-33. HardCopy Maximum Input Clock Rates HC210, HC220, HC230 HC240 Devices (Part I/OStandard
LVTTL LVCMOS SSTL2 class SSTL2 class SSTL18 class SSTL18 class HSTL class VHSTL class VHSTL class VHSTL class
Memory Interface IOEs
High General Speed Purpose IOEs IOEs
[0.3, 8.11]
[4.7, FPLL_CLK PLL_FB 12.15]
Unit
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Altera Corporation June 2007
Maximum Input Clock Rates
Table 4-33. HardCopy Maximum Input Clock Rates HC210, HC220, HC230 HC240 Devices (Part I/OStandard
PCIX Differential SSTL2 class (2), Differential SSTL2 class (2), Differential SSTL18 class (2), Differential SSTL18 class (2), 1.8-V Differential HSTL class (2), 1.8-V Differential HSTL class (2), 1.5-V Differential HSTL class (2), 1.5-V Differential HSTL class (2), LVDS LVPECL HyperTransport Notes Table 4-33:
clamping diode only supported bottom pins. This standard only supported DQS, CLK, PLL_FB input pins. HC210 HC220, Differential HSTL/SSTL input supported top/bottom PLL_FB, clock pins pins located I/Os.
Memory Interface IOEs
High General Speed Purpose IOEs IOEs
[0.3, 8.11]
[4.7, FPLL_CLK PLL_FB 12.15]
Unit
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HardCopy Series Handbook, Volume
Table 4-34. HardCopy Maximum Input Clock Rates HC210W Devices Standard
LVTTL 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVTTL/LVCMOS LVCMOS SSTL2 class SSTL2 class SSTL18 class SSTL18 class 1.5-V HSTL class 1.5-V HSTL class 1.8-V HSTL class 1.8-V HSTL class PCIX Differential SSTL2 class Differential SSTL2 class Differential SSTL18 class Differential SSTL18 class 1.8-V differential HSTL class 1.8-V differential HSTL class 1.5-V differential HSTL class 1.5-V differential HSTL class LVDS LVPECL
Note (Part FPLL_C [4.7, PLL_FB 12.15]
Memory Interface IOEs
High Speed IOEs
General Purpose IOEs
[0.3, 8.11]
Unit
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Maximum Output Clock Rates
Table 4-34. HardCopy Maximum Input Clock Rates HC210W Devices Standard
HyperTransport Notes Table 4-34:
Note (Part FPLL_C [4.7, PLL_FB 12.15]
Memory Interface IOEs
High Speed IOEs
General Purpose IOEs
[0.3, 8.11]
Unit
clamping diode only supported bottom pins. HC210W, differential HSTL/SSTL input supported clock pins, pins banks top/bottom PLL_FB input pins. These numbers preliminary pending further silicon characterization.
Maximum Output Clock Rates
Tables 4-35 4-36 show maximum output toggle rates HardCopy I/O's available drive strengths.
Table 4-35. HardCopy Maximum Output Clock Rate HC210, HC220, HC230 HC240 Devices Note (Part Memory Interface IOEs
1040
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs Bottom Column
Right
[4.7, PLL_OUT 12.15]
1040 1040
Unit
3.3-V LVTTL
3.3-V LVCMOS
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HardCopy Series Handbook, Volume
Table 4-35. HardCopy Maximum Output Clock Rate HC210, HC220, HC230 HC240 Devices Note (Part Memory Interface IOEs
1040
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs Bottom Column
Right
[4.7, PLL_OUT 12.15]
1040 1040
Unit
2.5-V LVTTL LVCMOS
1.8-V LVTTL LVCMOS
1.5-V LVTTL LVCMOS
SSTL2 class SSTL2 class
SSTL18 class
SSTL18 class
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Maximum Output Clock Rates
Table 4-35. HardCopy Maximum Output Clock Rate HC210, HC220, HC230 HC240 Devices Note (Part Memory Interface IOEs
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs Bottom Column
Right
[4.7, PLL_OUT 12.15]
Unit
1.8-V HSTL class
1.8-V HSTL class
1.5-V HSTL class
1.5-V HSTL class
PCIX LVDS HyperTransport LVPECL Differential SSTL2 class Differential SSTL2 class
Altera Corporation June 2007
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Table 4-35. HardCopy Maximum Output Clock Rate HC210, HC220, HC230 HC240 Devices Note (Part Memory Interface IOEs
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs Bottom Column
Right
[4.7, PLL_OUT 12.15]
Unit
Differential SSTL18 class
Differential SSTL18 class
1.8-V differential HSTL class
1.8-V differential HSTL class 1.5-V differential HSTL class
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Maximum Output Clock Rates
Table 4-35. HardCopy Maximum Output Clock Rate HC210, HC220, HC230 HC240 Devices Note (Part Memory Interface IOEs
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs Bottom Column
Right
[4.7, PLL_OUT 12.15]
Unit
1.5-V differential HSTL class Notes Table 4-35:
toggle rate applies output load standards except LVDS HyperTransport technology pins. LVDS HyperTransport technology pins, toggle rates apply load from FPLL_CLK dedicated input clocks, excluded from this table. This default setting Quartus software supported location. clamping diode only supported bottom pins. Like Stratix devices, differential HSTL SSTL supported only column CLK, PLL_OUT memory interface pins. HC210 HC220, Only column clock pins support Differential HSTL SSTL.
Table 4-36. HardCopy Maximum Output Clock Rate HC210W Devices Memory Interface IOEs
Notes (1), (Part
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs [4.7, PLL_OUT Bottom Right 12.15] Column
Unit
3.3-V LVTTL
3.3-V LVCMOS
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HardCopy Series Handbook, Volume
Table 4-36. HardCopy Maximum Output Clock Rate HC210W Devices Memory Interface IOEs
Notes (1), (Part
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs [4.7, PLL_OUT Bottom Right 12.15] Column
Unit
2.5-V LVTTL LVCMOS
1.8-V LVTTL LVCMOS
1.5-V LVTTL LVCMOS
SSTL2 class
SSTL2 class
SSTL18 class
SSTL18 class
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Altera Corporation June 2007
Maximum Output Clock Rates
Table 4-36. HardCopy Maximum Output Clock Rate HC210W Devices Memory Interface IOEs
Differential SSTL18 class
Notes (1), (Part
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs [4.7, PLL_OUT Bottom Right 12.15] Column
Unit
1.8-V HSTL class
1.8-V HSTL class
1.5-V HSTL class
1.5-V HSTL class
PCIX LVDS HyperTransport LVPECL Differential SSTL2 class Differential SSTL2 class
Altera Corporation June 2007
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Table 4-36. HardCopy Maximum Output Clock Rate HC210W Devices Memory Interface IOEs
Notes (1), (Part
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs [4.7, PLL_OUT Bottom Right 12.15] Column
Unit
Differential SSTL18 class
1.8-V differential HSTL class
1.8-V differential HSTL class
1.5-V differential HSTL class
1.5-V differential HSTL class
Notes Table 4-36:
toggle rate applies output load standards except LVDS HyperTransport technology pins. LVDS HyperTransport technology pins, toggle rates apply load from FPLL_CLK dedicated input clocks, excluded from this table. This default setting Quartus software supported location. clamping diode only supported bottom pins. Like Stratix devices, differential HSTL SSTL supported only column CLK, PLL_OUT memory interface pins. HC210 HC220, only column clock pins support Differential HSTL SSTL. These numbers preliminary pending further silicon characterization.
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Maximum Output Clock Rates
Tables 4-37 4-38 show maximum output toggle rates HardCopy I/O's using OCT.
Table 4-37. HardCopy Maximum Output Clock Rate HC210, HC220, HC230 HC240 Devices (OCT) Note (Part Memory Interface IOEs
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs [4.7, PLL_OUT Bottom Right 12.15] Column
Unit
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 3.3-V LVCMOS 1.5-V LVCMOS SSTL-2 Class SSTL-2 Class SSTL-18 Class
SSTL-18 Class 1.5-V HSTL Class 1.8-V HSTL Class 1.8-V HSTL Class Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class
Differential SSTL-18 Class 1.8-V Differential HSTL Class
1.8-V Differential HSTL Class
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Table 4-37. HardCopy Maximum Output Clock Rate HC210, HC220, HC230 HC240 Devices (OCT) Note (Part Memory Interface IOEs
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs [4.7, PLL_OUT Bottom Right 12.15] Column
Unit
1.5-V Differential HSTL Class
Notes Table 4-37:
toggle rate applies output load standards except LVDS HyperTransport technology pins. LVDS HyperTransport technology pins, toggle rates apply load from FPLL_CLK dedicated input clocks, excluded from this table. Like Stratix devices, differential HSTL SSTL supported only column CLK, PLL_OUT memory interface pins. HC210 HC220, only column clock pins support Differential HSTL SSTL.
Table 4-38. HardCopy Maximum Output Clock Rate HC210W using Memory Interface IOEs
Notes (1), (Part
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs [4.7, PLL_OUT Bottom Right 12.15] Column
Unit
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 3.3-V LVCMOS 1.5-V LVCMOS SSTL-2 Class SSTL-2 Class SSTL-18 Class
SSTL-18 Class 1.5-V HSTL Class 1.8-V HSTL Class 1.8-V HSTL Class
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Altera Corporation June 2007
HighSpeed Specifications
Table 4-38. HardCopy Maximum Output Clock Rate HC210W using Memory Interface IOEs
Notes (1), (Part
Standard
Drive Strength
High Speed IOEs
General Purpose IOEs [4.7, PLL_OUT Bottom Right 12.15] Column
Unit
Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class
Differential SSTL-18 Class 1.8-V Differential HSTL Class
1.8-V Differential HSTL Class 1.5-V Differential HSTL Class
Notes Table 4-38:
toggle rate applies output load standards except LVDS HyperTransport technology pins. LVDS HyperTransport technology pins, toggle rates apply load from FPLL_CLK dedicated input clocks, excluded from this table. Like Stratix devices, differential HSTL SSTL supported only column CLK, PLL_OUT memory interface pins. HC210 HC220, only column clock pins support Differential HSTL SSTL. These numbers preliminary pending further silicon characterization.
HighSpeed Specifications
Table 4-39 provides high-speed timing specifications definitions.
Table 4-39. HighSpeed Timing Specifications Definitions (Part HighSpeed Timing Specifications
fHSCLK
Definitions
Highspeed receiver/transmitter input output clock period. Highspeed receiver/transmitter input output clock frequency. De-serialization factor (width parallel data bus).
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Table 4-39. HighSpeed Timing Specifications Definitions (Part HighSpeed Timing Specifications
tRISE tFALL Timing unit interval (TUI) multiplication factor Low-to-high transmission time. High-to-low transmission time. timing budget allowed skew, propagation delays, data sampling window. (TUI 1/(Receiver Input Clock Frequency Multiplication Factor) tC/w). Maximum/minimum LVDS data transfer rate (fHSDR 1/TUI), non-DPA. Maximum/minimum LVDS data transfer rate (fHSDRDPA 1/TUI), DPA. timing difference between fastest slowest output edges, including variation clock skew. clock included TCCS measurement. period time during which data must valid order capture correctly. setup hold times determine ideal strobe position within sampling window. Peak-to-peak input jitter highspeed PLLs. Peak-to-peak output jitter highspeed PLLs. Duty cycle highspeed transmitter output clock. Lock time highspeed transmitter receiver PLLs.
Definitions
fHSDR fHSDRDPA Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak) Output jitter (peak-to-peak) tDUTY tLOCK
Table 4-40 shows high-speed timing specifications HC210W F484 WireBond devices.
Table 4-40. HardCopy High-Speed Specifications HC210W Device Notes (1), (Part Symbol
fHSCLK (clock frequency) fHSCLK fHSDR
Conditions
(LVDS, HyperTransport technology) (SERDES bypass, LVDS only) (SERDES used, LVDS only)
Unit
Mbps Mbps Mbps Mbps
fHSDR (data rate)
(LVDS, HyperTransport technology) (LVDS, HyperTransport technology) t(LVDS only)
fHSDRDPA (DPA data rate) TCCS Output jitter
(LVDS, HyperTransport technology) differential standards differential standards
4-36
Altera Corporation June 2007
HighSpeed Specifications
Table 4-40. HardCopy High-Speed Specifications HC210W Device Notes (1), (Part Symbol
Output tRISE Output tFALL tDUTY length jitter tolerance (peak-to-peak) lock time Standard Training Pattern Transition Density
Conditions
differential standards differential standards
Unit
Number repetitions
6,400
SPI4 Parallel Rapid
0000000000 1111111111 10010000 10010000
100%
Miscellaneous
10101010 10101010
Notes Table 4-40:
These numbers preliminary pending further silicon characterization. When SERDES block used. When SERDES block bypassed. input clock frequency factor must satisfy following fast specification: input clock frequency 640. minimum specification dependent clock source (fast PLL, enhanced PLL, clock pin, clock routing resource (global, regional, local) utilized. differential buffer input register have minimum toggle rate. Contact Altera Applications Group more information.
Table 4-41 shows high-speed timing specifications HC210, HC220, HC230 HC240 HardCopy devices.
Table 4-41. HardCopy High-Speed Specifications HC210, HC220, HC230 HC240 Devices Note (Part Symbol
fHSCLK (clock frequency) fHSCLK fHSDR
Conditions
(LVDS, HyperTransport technology) (SERDES bypass, LVDS only) (SERDES used, LVDS only)
Unit
Altera Corporation June 2007
4-37
HardCopy Series Handbook, Volume
Table 4-41. HardCopy High-Speed Specifications HC210, HC220, HC230 HC240 Devices Note (Part Symbol
fHSDR (data rate)
Conditions
(LVDS, HyperTransport technology) (LVDS, HyperTransport technology) (LVDS only)
1,040 1,040
Unit
Mbps Mbps Mbps Mbps
fHSDRDPA (DPA data rate) TCCS Output jitter Output tRISE Output tFALL tDUTY length jitter tolerance (peak-to-peak) lock time
(LVDS, HyperTransport technology) differential standards differential standards
Number repetitions
differential standards differential standards
6,400 0.44
Standard
Training Pattern
Transition Density
SPI4 Parallel Rapid
0000000000 1111111111 10010000 10010000
100%
Miscellaneous
10101010 10101010
Notes Table 4-41:
When SERDES block used. When SERDES block bypassed. input clock frequency factor must satisfy following fast specification: input clock frequency 1,040. minimum specification dependent clock source (fast PLL, enhanced PLL, clock pin, clock routing resource (global, regional, local) utilized. differential buffer input register have minimum toggle rate.
4-38
Altera Corporation June 2007
Timing Specifications
Timing Specifications
Tables 4-42 4-43 describe HardCopy specifications when operating both commercial junction temperature range industrial junction temperature range (-40° 100° except clock switchover feature. Like Stratix devices, clock switchover feature only supported from 100° junction temperature range.
Table 4-42. HardCopy Enhanced Specifications (Part Name
Description
Input clock frequency HC210, HC220, HC230 HC240 devices Input clock frequency HC210W device
Unit
(pp) (pp)
fINPFD fINDUTY fEINDUTY tINJITTER
Input frequency Input clock duty cycle External feedback input clock duty cycle Input external feedback clock input jitter tolerance terms period jitter. Bandwidth 0.85 Input external feedback clock input jitter tolerance terms period jitter. Bandwidth 0.85
tOUTJITTER
Dedicated clock output period jitter HC210, HC220, HC230 HC240 devices Dedicated clock output period jitter HC210W device
outclk outclk outclk outclk 174/fSCANCLK
tFCOMP fOUT tOUTDUTY fSCANCLK tCONFIGEPLL fOUT_EXT
External feedback compensation time Output frequency internal global regional clock Duty cycle external clock output (when 50%). Scanclk frequency Time required reconfigure scan chains enhanced PLLs external clock output frequency
Altera Corporation June 2007
4-39
HardCopy Series Handbook, Volume
Table 4-42. HardCopy Enhanced Specifications (Part Name
tLOCK
Description
Time required lock from time enabled device configuration Time required lock dynamically after automatic clock switchover between identical clock frequencies Frequency range where clock switchover performs properly closed loop bandwidth operating range HC210, HC220, HC230 HC240 devices operating range HC210W devices
0.03
Unit
tDLOCK
fSWITCHOVER fCLKW fVCO
0.13
16.9 1,040
spread tPLL_PSERR tARESET tARESET_RECONFIG
Spread spectrum modulation frequency Percent down spread given clock frequency Accuracy phase shift Minimum pulse width ARESET signal. Minimum pulse width areset signal when using reconfiguration. Reset after scan done goes high.
Notes Table 4-42:
Limited fMAX. counter cascading feature utilized, there minimum output clock frequency. Applicable when input clock been running continuously least Applicable when input clock stopped toggling been running continuously less than
4-40
Altera Corporation June 2007
Timing Specifications
Table 4-43. HardCopy Fast Specifications (Part Name
Description
Input clock frequency HC210, HC220, HC230 HC240 devices Input clock frequency HC210W device
Unit
(pp) (pp)
fINPFD fINDUTY tINJITTER
Input frequency Input clock duty cycle Input clock jitter tolerance terms period jitter. Bandwidth Input clock jitter tolerance terms period jitter. Bandwidth
4.6875 1,040 1,040
fVCO
Upper frequency range HC210, HC220, HC230 HC240 devices Upper frequency range HC210W devices Lower frequency range HC210, HC220, HC230 HC240 devices Lower frequency range HC210W device
fOUT
output frequency GCLK RCLK output frequency LVDS clock HC210, HC220, HC230 HC240 devices output frequency LVDS clock HC210W devices
4.6875 75/fSCANCLK 1.16 0.03
fOUT_IO tCONFIGPLL fCLBW tLOCK
clock output frequency regular Time required reconfigure scan chains fast PLLs closed loop bandwidth Time required lock from time enabled device configuration Accuracy phase shift Minimum pulse width areset signal.
tPLL_PSERR tARESET
Altera Corporation June 2007
4-41
HardCopy Series Handbook, Volume
Table 4-43. HardCopy Fast Specifications (Part Name Description
Unit
tARESET_RECONFIG Minimum pulse width areset signal when using reconfiguration. Reset after scan done goes high. Note Table 4-43:
Limited fMAX.
External Memory Interface Specifications
Table 4-44 summarizes maximum clock rate that HardCopy devices support with external memory devices.
Table 4-44. HardCopy Maximum Clock Rate Support External Memory Interfaces HardCopy Device Memory Standards Wire Bond Package HC210W
Note
Flip Chip Package HC210 HC220 HC230 HC240
Unit
DDR2 QDRII RLDRAMII Notes Table 4-44:
HardCopy devices support PLL-based external memory interface except SDRAM's which does require DLL. HC210W supports memory interface banks. HC210 HC220 support memory interface banks. HC230 HC240 support memory interface bottom banks. will need under-clock memory device. will need under-clock memory device. Based DDIO scheme with 1.8-V HSTL standard. Based dedicated scheme. same FMAX specification Static-PHY Auto-PHY since write-side limited tDS/tH specification.
4-42
Altera Corporation June 2007
External Memory Interface Specifications
Tables 4-45 through 4-51 contain HardCopy device specifications dedicated circuitry used interfacing with external memory devices.
Table 4-45. Frequency Range Specifications Frequency Mode
Frequency Range
Resolution (Degrees)
22.5
Table 4-46 lists maximum delay fast timing model HardCopy delay buffer. Multiply number delay buffers that using logic block maximum delay achievable your system. example, implement phase shift MHz, three delay buffers mode maximum achievable delay from block then .416 1.248
Table 4-46. Delay Buffer Maximum Delay Fast Timing Model Frequency Mode Maximum Delay Delay Buffer
0.833 0.416
Unit
Table 4-47. Period Jitter Specifications DLL-Delayed Clock (tDQS_JITTER) Note Number Delay Buffer Stages
Notes Table 4-47:
Peak-to-peak period jitter phase shifted clock. Delay stages used requested phase shift reported your project's Compilation Report Quartus software.
Commercial
Industrial
Unit
Altera Corporation June 2007
4-43
HardCopy Series Handbook, Volume
Table 4-48. Phase Jitter Specifications DLL-Delayed Clock (tDQS PHASE_JITTER) Note Number Delay Buffer Stages
Notes Table 4-48:
Peak-to-peak phase jitter phase shifted clock (digital jitter caused tracking). Delay stages used requested phase shift reported your project's Compilation Report Quartus software.
Phase Jitter
Unit
Table 4-49. Phase-Shift Error Specifications DLL-Delayed Clock (tDQS_PSERR) Note Number Delay Buffer Stages (2))
Notes Table 4-49:
This error specification absolute maximum minimum error. example, skew three delay buffer stages with HC240 device 52.5 Delay stages used requested phase shift reported your project's Compilation Report Quartus software.
HC210, HC220, HC230 HC240
Unit
4-44
Altera Corporation June 2007
Socketing
Table 4-50. Clock Skew Adder Specifications (tDQS_CLOCK_SKEW_ADDER) Note Mode
Note Table 4-50:
This skew specification absolute maximum minimum skew. example, skew group
Clock Skew Adder
Unit
Table 4-51. Phase Offset Delay Stage Note HardCopy Devices
Note Table 4-51
delay settings linear. valid settings phase offset frequency mode frequency modes typical value equals average minimum maximum values.
Unit
Socketing
HardCopy devices offer socketing, which also known plugin swap, power sequencing support without external devices. insert remove HardCopy board sy
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