Skew Zero Delay Buffer Frequency Range 10MHz 220MHz Zero input ou

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Skew Zero Delay Buffer Frequency Range 10MHz 220MHz Zero input ou

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PL123E-09
Skew Zero Delay Buffer
Frequency Range 10MHz 220MHz Zero input output delay. Output Output Skew Optional Drive Strength: Standard (8mA) PL123E-09 High (12mA) PL123E-09H 2.5V 3.3V, ±10% operation. Available 16-Pin TSSOP packages
DESCRIPTION
PL123E-09 (-09H High Drive) high performance, skew, jitter zero delay buffer designed distribute high speed clocks. lowskew output banks, outputs each, that synchronized with input. Control banks outputs achieved using inputs shown Selector Definition table page synchronization established CLKOUT feed back input PLL. Since skew between input output less than ±100ps, device acts zero delay buffer. input output propagation delay advanced delayed adjusting load CLKOUT pin. These parts intended input-tolerant applications.
BLOCK DIAGRAM
CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1
Bank
CLKA1 CLKA2 CLKB1
CLKOUT CLKA4 CLKA3 CLKB4 CLKB3
PL123E-09
Bank
Selector Inputs
CLKB2 CLKB3 CLKB4
CLKB2
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
DESCRIPTIONS
Name CLKA1 CLKA2 CLKB1 CLKB2 CLKB3 CLKB4 CLKA3 CLKA4 CLKOUT Package Type TSSOP-16L 4,13 5,12 SOP-16L 4,13 5,12 Type Description Input reference frequency. Buffered clock output, Bank Buffered clock output, Bank connection connection Buffered clock output, Bank Buffered clock output, Bank Selector input Selector input Buffered clock output, Bank Buffered clock output, Bank Buffered clock output, Bank Buffered clock output, Bank Buffered clock output. Internal feedback this pin.
Notes: Weak pull-down. Weak pull-down outputs. Weak Pull-Up
SELECTOR DEFINITION
CLOCK A1-A4 (Bank Three-state Driven Driven Driven CLOCK B1-B4 (Bank Three-state Three-state Driven Driven CLKOUT Driven Driven Driven Driven Output Source Reference Shutdown
INPUT OUTPUT SKEW CONTROL
PL123E-09 will achieve Zero Delay from input output when outputs loaded equally. Adjustments input/output delay made adding additional loading CLKOUT pin. Please contact PhaseLink more information.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
LAYOUT RECOMMENDATIONS
following guidelines assist with performance optimized design:
Signal Integrity Termination Considerations
Keep traces short! Trace Inductor. With capacitive load this equals ringing! Long trace Transmission Line. Without proper termination this will cause reflections looks like ringing Design long traces "striplines" "microstrips" with defined impedance. Match trace side avoid reflections bouncing back forth.
Decoupling Power Supply Considerations
Place decoupling capacitors close possible pin(s) limit noise from power supply Addition ferrite bead series with help prevent noise from other board sources Value decoupling capacitor frequency dependant. Typical values 0.1F designs using frequencies 50MHz 0.01F designs using frequencies 50MHz.
Typical CMOS termination Place Series Resistor close possible CMOS output CMOS Output Buffer
Typical buffer impedance line
CMOS Input
Series Resistor
value match output buffer impedance trace. Typical value
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
ABSOLUTE MAXIMUM CONDITIONS
Supply Voltage Ground Potential -0.5V 4.6V Input Voltage 0.5V 4.6V Storage Temperature -65°C 150°C Junction Temperature 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015).> 2000V
OPERATING CONDITIONS
Description Supply Voltage Load Capacitance, <100 MHz, 3.3V Load Capacitance, <100 MHz, 2.5V with High Drive Load Capacitance, <133.3 MHz, 3.3V Load Capacitance, <133.3 MHz, 2.5V with High Drive Load Capacitance, <133.3 MHz, 2.5V with Standard Drive Load Capacitance, >133.3 MHz, 3.3V Load Capacitance, >133.3 MHz, 2.5V with High Drive Input Capacitance Closed-loop bandwidth (typical), 3.3V Closed-loop bandwidth (typical), 2.5V Output Impedance (typical), 3.3V High Drive Output Impedance (typical), 3.3V Standard Drive Output Impedance (typical), 2.5V High Drive Output Impedance (typical), 2.5V Standard Drive Power-up time reach minimum specified voltage (power ramps must monotonic) Dissipation, Junction Ambient, 16-pin Dissipation, Junction Ambient, 16-pin TSSOP Dissipation, Junction Case, 16-pin Dissipation, Junction Case, 16-pin TSSOP
Notes:
Parameter
2.25
3.63
Unit
Theta Theta Theta Theta
0.01
°C/W °C/W °C/W °C/W
Applies Test Circuit Applies both Clock internal feedback path CLKOUT. Theta JEDEC test board conditions, 2S2P; Theta Mil-Spec 883E Method 1012.1.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
3.3V ELECTRICAL SPECIFICATIONS
Description Supply Voltage Input Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output Voltage Output HIGH Voltage Power Down Supply Current Supply Current Parameter (Standard Drive) (High Drive) (Standard Drive) (High Drive) (Industrial) Unloaded outputs, 66-MHz Test Conditions 2.97 3.63 Unit
mode) (Commercial)
2.5V ELECTRICAL SPECIFICATIONS
Description Supply Voltage Input Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output Voltage Output HIGH Voltage Power Down Supply Current Supply Current Parameter mode) (Standard Drive) (High Drive) (Standard Drive) (High Drive) (Commercial) (Industrial) Unloaded outputs, 66-MHz Test Conditions 2.25 2.75 Unit
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
3.3V 2.5V ELECTRICAL SPECIFICATIONS
Description Maximum Frequency (Input/Output) Parameter Test Conditions 3.3V High Drive 3.3V Standard Drive 2.5V High Drive 2.5V Standard Drive Input Duty Cycle Output Duty Cycle <133.3 >133.3 <133.3 >133.3 Standard Drive, <100 Standard Drive, <133.3 Rise, Fall Time (3.3V) Standard Drive, <167 High Drive, <100 High Drive, <133.3 High Drive, >133.3 Standard Drive, <133.33 Rise, Fall Time (2.5V) High Drive, <100 High Drive, <133.3 High Drive, >133.3 Output Output Skew
-100 -200
±150 ±300
Unit
outputs equally loaded enabled 3.3V enabled @2.5V Measured output output, 3.3V supply Measured output output, 2.5V supply Stable power supply, valid clocks presented CLKOUT pins 3.3V, MHz, 3.3V, MHz, Standard. Drive
Delay, Rising Edge CLKOUT Rising Edge
Part Part
Skew
Lock Time
LOCK
Cycle-to-Cycle Jitter, Peak
JCC[9,10]
3.3V, MHz, High Drive 2.5V, MHz, Standard. Drive 2.5V, MHz, High Drive 2.5V, MHz, High Drive
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
3.3V 2.5V ELECTRICAL SPECIFICATIONS (continued)
Description Cycle-to-Cycle Jitter, Peak Parameter Test Conditions S2:S1 1:0, 3.3V, <15pF, Standard Drive JCC[9,10] S2:S1 1:0, 3.3V, <15pF, High Drive S2:S1 1:0, 2.5V, <15pF, Standard Drive S2:S1 1:0, 2.5V, <15pF, High Drive 3.3V, 66-100 MHz, 3.3V, >100 MHz, 3.3V, MHz, Standard Drive 3.3V, MHz, High Drive 2.5V, MHz, Standard. Drive Period Jitter, Peak PER[9,10] 2.5V, 66-100 MHz, High Drive 2.5V, >100 MHz, High Drive S2:S1 1:0, 3.3V, <15pF, Standard Drive S2:S1 1:0, 3.3V, <15pF, High Drive S2:S1 1:0, 2.5V, <15pF, Standard Drive S2:S1 1:0, 2.5V, <15pF, High Drive Unit
Notes: given maximum loading conditions. Operating Conditions Table. Parameter guaranteed design characterization. 100% tested production. Typical jitter measured 3.3V 2.5V, 29°C, with outputs driven into maximum specified load.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
SWITCHING WAVEFORMS
Duty Cycle Timing
VDD/2
VDD/2
Outputs Rise/Fall Time
OUTPUT
2.0V(1.8V)
2.0V(1.8V) 0.8V(0.6V)
3.3V (2.5V)
0.8V(0.6V) Output-Output Skew OUTPUT VDD/2
OUTPUT
VDD/2
Input-Output Propagation Delay INPUT VDD/2
CLKOUT
VDD/2
Device-Device Skew Output, Part VDD/2
Output, Part
VDD/2
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
TEST CIRCUITS
Test Circuit
OUTPUTS
LOAD
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
Narrow SOP, TSSOP
Symbol Min. Max. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 5.80 6.20 0.40 1.27 1.27 TSSOP Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 0.45 0.75 0.65
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123E-09
Skew Zero Delay Buffer
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
Part/Order Number PL123E-09OC PL123E-09OC-R PL123E-09HOC PL123E-09HOC-R PL123E-09SC PL123E-09SC-R PL123E-09HSC PL123E-09HSC-R PL123E-09OI PL123E-09OI-R PL123E-09HOI PL123E-09HOI-R PL123E-09SI PL123E-09SI-R PL123E-09HSI PL123E-09HSI-R
Marking P123E-09 P123E-09 P123E-09H P123E-09H P123E-09 P123E-09 P123E-09H P123E-09H P123E-09 P123E-09 P123E-09H P123E-09H P123E-09 P123E-09 P123E-09H P123E-09H
16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin
Package Option TSSOP Tube TSSOP (Tape Reel) TSSOP Tube TSSOP (Tape Reel) Tube (Tape Reel) Tube (Tape Reel) TSSOP Tube TSSOP (Tape Reel) TSSOP Tube TSSOP (Tape Reel) Tube (Tape Reel) Tube (Tape Reel)
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
Solder reflow profile available
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page

Skew Zero Delay Buffer Frequency Range 10MHz 220MHz Zero input ou

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