Nine-Output 3.3V Buffer One-input nine-output buffer/driver Suppo

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Nine-Output 3.3V Buffer One-input nine-output buffer/driver Suppo

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PL123-09N
Nine-Output 3.3V Buffer
One-input nine-output buffer/driver Supports DIMMs four SO-DIMMs with additional output feedback external chip power consumption portable applications input-output delay Buffers frequencies from Output-output skew less than 3.3V, ±10% operation Available 16-Pin packages Industrial temperature available
DESCRIPTION
PL123-09N low-cost buffer distributing high-speed clocks with skew, jitter. part nine outputs. typical application driving SDRAM systems would eight outputs drive DIMMs, four SO-DIMMs, with remaining output used driving external feedback PLL. device operates 3.3V, MHz. part designed with three pairs power/ground pins minimize EMI, consumes less than MHz, ideal low-power mobile applications. available compact 150-mil 16-pin package. These parts intended input-tolerant applications.
BLOCK DIAGRAM
BUF_IN
OUTPUT1 OUTPUT2 BUF_IN OUTPUT3 OUTPUT4 OUTPUT5 OUTPUT6 OUTPUT7 OUTPUT8 OUTPUT9 OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT9 OUTPUT8 OUTPUT7 OUTPUT6 OUTPUT5
PL123-09N
DESCRIPTION
Signal BUF_IN OUTPUT[1:9] Description 3.3V Power Supply Voltage Ground Input Clock Output Clocks
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-09N
Nine-Output 3.3V Buffer
LAYOUT RECOMMENDATIONS
following guidelines assist with performance optimized design:
Signal Integrity Termination Considerations
Keep traces short! Trace Inductor. With capacitive load this equals ringing! Long trace Transmission Line. Without proper termination this will cause reflections looks like ringing Design long traces "striplines" "microstrips" with defined impedance. Match trace side avoid reflections bouncing back forth.
Decoupling Power Supply Considerations
Place decoupling capacitors close possible pin(s) limit noise from power supply Addition ferrite bead series with help prevent noise from other board sources Value decoupling capacitor frequency dependant. Typical values 0.1F designs using frequencies 50MHz 0.01F designs using frequencies 50MHz.
Typical CMOS termination Place Series Resistor close possible CMOS output CMOS Output Buffer
Typical buffer impedance line
CMOS Input
Series Resistor
value match output buffer impedance trace. Typical value
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-09N
Nine-Output 3.3V Buffer
ABSOLUTE MAXIMUM CONDITIONS
Supply Voltage Ground Potential -0.5V 4.6V Input Voltage 0.5V 4.6V Storage Temperature -65°C 150°C Junction Temperature. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015).> 2000V
OPERATING CONDITIONS
Parameter Description Min. Max. Unit
BUF_IN, OUTPUT[1:9]
Supply Voltage Commercial Operating Temperature (ambient temperature) Industrial Operating Temperature (ambient temperature) Load Capacitance, below Load Capacitance, above Input Capacitance Operating Frequency Power-up time reach minimum specified voltage (power ramps must monotonic)
0.05
LECTRICAL CHARACTERISTICS (Commercial Industrial Temperature Devices)
Parameter Description Test Conditions Min. Max. Unit
Input Voltage[1] Input HIGH Voltage Input Current Input HIGH Current Output Voltage[2] Output HIGH Voltage[2] Supply Current
66.67MHz with unloaded outputs
50.0 100.0
WITCHING CHARACTERISTICS (Commercial Industrial Temperature Devices)
Parameter Name Duty Cycle Rise Time Fall Time Output Output Skew[2] Propagation Delay, BUF_IN Rising Edge OUTPUT Rising Edge Description Measured 1.4V Measured between 0.8V 2.0V Measured between 0.8V 2.0V outputs equally loaded Measured VDD/2 Min. 40.0 Typ. 50.0 Max. 60.0 1.50 1.50 Unit
Notes: BUF_IN input threshold voltage VDD/2. Parameter guaranteed design characterization. 100% tested production. parameters specified with loaded outputs.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-09N
Nine-Output 3.3V Buffer
SWITCHING WAVEFORMS
Duty Cycle Timing
1.4V
1.4V
Outputs Rise/Fall Time OUTPUT
2.0V 0.8V
2.0V 0.8V
3.3V
Output-Output Skew OUTPUT 1.4V
OUTPUT
1.4V
Input-Output Propagation Delay INPUT VDD/2
OUTPUT
VDD/2
TEST CIRCUITS
Test Circuit
OUTPUTS
LOAD
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-09N
Nine-Output 3.3V Buffer
PACKAGE DRAWINGS
SOP-16L
Symbol Min. Max. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 5.80 6.20 0.40 1.27 1.27
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-09N
Nine-Output 3.3V Buffer
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-05/-0990 Fax: (510) 492-05/-0991
PART NUMBER
order number this device combination following: Part number, Package type Operating temperature range
Part/Order Number PL123-09NSC PL123-09NSC-R PL123-09NSI PL123-09NSI-R PL123-09NSCA PL123-09NSCA-R PL123-09NSIA PL123-09NSIA-R
Marking Green (Lead-Free) Package P123-09N 16-Pin P123-09N 16-Pin P123-09N 16-Pin P123-09N 16-Pin Green Package P123-09N 16-Pin P123-09N 16-Pin P123-09N 16-Pin P123-09N 16-Pin
Package Option Tube (Tape Reel) Tube (Tape Reel) Tube (Tape Reel) Tube (Tape Reel)
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
Solder reflow profile available
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page

Nine-Output 3.3V Buffer One-input nine-output buffer/driver Suppo

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