3.3V Zero Delay Buffer Zero input-output propagation delay, adjus

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3.3V Zero Delay Buffer Zero input-output propagation delay, adjus

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PL123-04
3.3V Zero Delay Buffer
Zero input-output propagation delay, adjustable capacitive load input Multiple configurations, "Available Configurations" table Multiple low-skew outputs operating range cycle-to-cycle jitter package 3.3V operation Commercial industrial temperature available
DESCRIPTION
PL123-04 PLL-based zero-delay buffer, used distribute four outputs. external feedback enables removing delay from external components. also provides adjustable input-to-output delay varying loading relative output loading. PL123-042 option allows user obtain x0.5 frequencies output bank. exact multiplier depends which output connected pin. Refer Available Configurations table below more details. These parts intended input-tolerant applications.
BLOCK DIAGRAM
Extra Divider (-042)
CLKA1 CLKA2
CLKA1 CLKA2
View
CLKB2 CLKB1
PL123-04
CLKB1 CLKB2
AVAILABLE CONFIGURATIONS
Device PL123-04 PL123-042 PL123-042 Feedback From Bank Bank Bank Bank Bank Frequency Reference Reference Reference Bank Frequency Reference Reference Reference
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-04
3.3V Zero Delay Buffer
DESCRIPTION
Name REF[1] CLKA1[2] CLKA2[2] CLKB1[2] CLKB2[2] Type Description Input reference frequency Clock output, Bank Clock output, Bank Ground Clock output, Bank Clock output, Bank 3.3V Supply feedback input
Notes: Weak pull-down. Weak pull-down outputs.
PLL's feedback path must closed connecting available four outputs. output driving will drive (internal) load plus additional loading placed this output pin. zero-delay applications, outputs, including connected output pin, must loaded equally. Varying loading between output pins adjust input-to-output delay.
MAXIMUM RATINGS
Supply Voltage Ground Potential.-0.5V 4.6V Input Voltage (Except REF).-0.5V VDD+0.5V Input Voltage REF.-0.5V 4.6V Storage Temperature.-65 Junction Temperature.150 Static Discharge Voltage (MIL-STD-883, Method 3015).
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-04
3.3V Zero Delay Buffer
LAYOUT RECOMMENDATIONS
following guidelines assist optimizing design: Signal Integrity Termination Considerations Keep traces short Trace Inductor. Adding capacitive load cause ringing. Long trace Transmission Line. Without proper termination this will cause reflections (causing ringing). Design long traces "striplines" "microstrips" with defined impedance. Terminate traces with characteristic impedance trace avoid reflections (see figure below). Decoupling Power Supply Considerations Place decoupling capacitors close possible pin(s) bypass noise from power supply Multiple pins should decoupled separately best performance. Value decoupling capacitor frequency dependant. Typical values 0.1F designs supporting frequencies below 50MHz (0.01F designs supporting frequencies above 50MHz).
Typical CMOS termination Place Series Resistor close possible CMOS output
CMOS Output Buffer (Typical buffer impedance line CMOS Input
Series Resistor Adjust value match output buffer impedance trace. Typical value
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-04
Max. Unit
3.3V Zero Delay Buffer
OPERATING CONDITIONS
Parameter Description Supply Voltage Commercial Operating Temperature (ambient temperature) Industrial Operating Temperature (ambient temperature) Load Capacitance, below Load Capacitance, above Input Capacitance Power-up time VDDs reach minimum specified voltage (power ramps must monotonic) Min. 0.05
Notes: Applies both clock inputs.
ELECTRICAL CHARACTERISTICS
Parameter Description Input Voltage Input HIGH Voltage Input Current Input HIGH Current Output Voltage[4] Output HIGH Voltage[4] MHz, Commercial Temp. MHz, Industrial Temp. 100-MHz Select inputs 66-MHz REF, Commercial Temp. 33-MHz REF, Commercial Temp. 66-MHz REF, Industrial Temp. 33-MHz REF, Industrial Temp. Test Conditions Min. Max. 50.0 100.0 12.0 25.0 45.0 32.0 18.0 35.0 20.0 Unit
mode) Power Down Supply Current
Supply Current (Unloaded Outputs)
Notes: Parameter guaranteed design characterization. 100% tested production.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-04
3.3V Zero Delay Buffer
SWITCHING CHARACTERISTICS
PaName rameter Output Frequency Output Frequency Duty Cycle Duty Cycle 30-pF load 15-pF load Measured 1.4V, FOUT 66.66 30-pF load Measured 1.4V, FOUT <50.0 15-pF load Measured between 0.8V 2.0V, 30-pF load Commercial Temperature Measured between 0.8V 2.0V, 30-pF load Industrial Temperature Measured between 0.8V 2.0V, 15-pF load Measured between 0.8V 2.0V, 30-pF load Commercial Temperature Measured between 0.8V 2.0V, 30-pF load Industrial Temperature Measured between 0.8V 2.0V, 15-pF load outputs equally loaded outputs equally loaded outputs equally loaded Measured VDD/2 Measured VDD/2 pins devices Measured 66.67 MHz, loaded outputs, 15-pF load Measured 66.67 MHz, loaded outputs, 30-pF load Measured 133.3 MHz, loaded outputs, 15-pF load Measured 66.67 MHz, loaded outputs 30-pF load Measured 66.67 MHz, loaded outputs 15-pF load Stable power supply, valid clocks presented pins
Test Conditions
Min. 40.0 45.0
Typ. 50.0 50.0
Max. 60.0 55.0 2.20 2.50 1.50 2.20 2.50 1.50 ±250
Unit
Rise Time
Fall Time
Output Output Skew same Bank Output Bank Output Bank Skew (-04) Output Bank Output Bank Skew (-042) Skew, Rising Edge Rising Edge Device Device Skew Cycle Cycle Jitter (-04) Cycle Cycle Jitter (-042) Lock Time
tLOCK
Notes: parameters specified with loaded outputs.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-04
3.3V Zero Delay Buffer
SWITCHING WAVEFORMS
Duty Cycle Timing
1.4V
1.4V
Outputs Rise/Fall Time OUTPUT Output-Output Skew OUTPUT
2.0V 0.8V
2.0V 0.8V
3.3V
1.4V
OUTPUT
1.4V
Input-Output Propagation Delay OUTPUT VDD/2
VDD/2
Device-Device Skew FBK, Device VDD/2
FBK, Device
VDD/2
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-04
3.3V Zero Delay Buffer
TEST CIRCUIT
Test Circuit
OUTPUTS
LOAD
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
8-Pin
Symbol
Dimension Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page
PL123-04
3.3V Zero Delay Buffer
ORDERING INFORMATION
part ordering, please contact Sales Department: 47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER order number this device combination following: Part number, Package type Operating temperature range
Part/Order Number PL123-04SC PL123-04SC-R PL123-042SC PL123-042SC-R PL123-04SI PL123-04SI-R PL123-042SIC PL123-042SIC-R PL123-04SCA PL123-04SCA-R PL123-042SCA PL123-042SCA-R PL123-04SIA PL123-04SIA-R PL123-042SICA PL123-042SICA-R
Marking
Package Option
Range Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Green (Lead-Free) Packages P123-04 8-Pin Tube P123-04 8-Pin (Tape P123-042 8-Pin Tube P123-042 8-Pin (Tape P123-04 8-Pin Tube P123-04 8-Pin (Tape P123-042 8-Pin Tube P123-042 8-Pin (Tape Green Packages P123-04 8-Pin Tube P123-04 8-Pin (Tape P123-042 8-Pin Tube P123-042 8-Pin (Tape P123-04 8-Pin Tube P123-04 8-Pin (Tape P123-042 8-Pin Tube P123-042 8-Pin (Tape
Reel) Reel) Reel) Reel) Reel) Reel) Reel) Reel)
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
Solder reflow profile available
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 7/19/07 Page

3.3V Zero Delay Buffer Zero input-output propagation delay, adjus

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