H51025-1.2 Quartus software includes command-line executables, ma

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Script-Based Design HardCopy Devices
H51025-1.2
Quartus software includes command-line executables, many which support interactive shell. Using shell, perform FPGA HardCopy design operations without using Quartus window-based GUI. This chapter provides introduction operations script-based HardCopy design using interactive shell. Topics covered this chapter include:
Overview scripting features Quartus software HardCopy design flow Applying location timing constraints Synthesis, place route HardCopy designs, Stratix prototypes Design verification analysis
Support Quartus Software
Quartus software provides different ways execute commands scripts, including:
Console window Scripts dialogue Command-line processing interactive shell
Console window Scripts dialogue both within Quartus described here. Instead, this chapter focuses Interactive shell that with Quartus command-line executables.
more information about command-line processing Quartus command-line executables batchfiles, makefiles, scripts, refer Command-Line Scripting chapter volume Quartus Handbook. more information Quartus implementation, refer Reference Manual Scripting chapter Quartus Handbook.
Altera Corporation June 2007
HardCopy Series Handbook, Volume
Interactive Shell
number Quartus executables with interactive shell user interface. These executables identified Table 6-1. interactive shell supports version 8.4.
Table 6-1. Quartus Command-Line Executables with Interactive Support Executable Name quartus_sh Description
basic interpreter shell. Supports assignment specification, compile operations, native operating system commands. more information, refer quartus_sh Command-Line Executables section Quartus Scripting Reference Manual. Quartus TimeQuest timing analyzer engine supports building timing graph design timing analysis commands. more information, refer quartus_sta Command-Line Executables section Quartus Scripting Reference Manual. Quartus Classic Timing Analyzer engine supports building timing graph design timing analysis commands. more information, refer quartus_tan Command-Line Executables section Quartus Scripting Reference Manual. Quartus database interface executable. Supports operations related design database such LogicLock, back-annotation, FPGA-HardCopy comparison HardCopy designs. more information, refer quartus_cdb CommandLine Executables section Quartus Scripting Reference Manual. Quartus Simulator. more information, refer quartus_sim Command-Line Executables section Quartus Scripting Reference Manual.
quartus_sta
quartus_tan
quartus_cdb
quartus_sim
Altera Corporation June 2007
Support Quartus Software
interactive shell command-line executables invoked using command-line switch. example, basic Quartus shell, type quartus_sh command prompt:
quartus_sh Info: Info: Running Quartus Shell Info: Info: Quartus Shell supports commands addition Info: Quartus commands. unrecognized commands Info: assumed external using Tcl's "exec" Info: command. Info: Type "exit" exit. Info: Type "help" view list Quartus packages. Info: Type "help -pkg <package name>" view list commands Info: available specified Quartus package. Info: Type "help -tcl" overview Quartus usages. Info: tcl>
Quartus implementation provides custom procedures perform Quartus operations. These procedures organized into packages based their functionality. Table lists these packages their availability. Some packages loaded default when executable invoked. Others must explicitly loaded before their procedures used. load particular package, load_package procedure. example, load flow package quartus_sh shell, following statement executed: tcl> load_package flow important note that executables support packages.
Table 6-2. Package Support Quartus Executables Executable Name quartus_sta Supported Package
device misc flow project report
(Part Loaded Default?
Loaded Loaded loaded Loaded Loaded Loaded Loaded
Altera Corporation June 2007
HardCopy Series Handbook, Volume
Table 6-2. Package Support Quartus Executables Executable Name quartus_sh Supported Package
device flow misc project report
(Part Loaded Default?
Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded Loaded
quartus_tan
advanced_timing device flow logiclock Misc project report timing timing_report
quartus_cdb
backannotate chip_editor device flow logiclock misc project report
quartus_sim
device flow misc project report simulator
brief description each packages referenced Table given Table 6-3.
find which packages loaded, command quartus_??? -tcl_eval help. example: quartus_sta -tcl_eval help.
Altera Corporation June 2007
Support Quartus Software
Table 6-3. Quartus Package Descriptions Package
advanced_timing backannotate chip_editor database_manager device flow logiclock misc project report simulator timing timing_report Back annotate assignments. Identify modify resource usage routing with Chip Editor. Manage version-comparable database files. device family information from device database. Compile project, command-line executables other common flows. Create manage LogicLock regions. Perform miscellaneous tasks. Create manage projects revisions make project assignments including timing assignments. information from report tables create custom reports. Configure perform simulations. Operate SignalTap Analyzer. Annotate timing netlist with delay information, compute report timing paths. List timing paths.
Description
Traverse timing netlist information about timing modes.
Quartus command-line executables shells supported Quartus operating systems, including Microsoft Windows, Linux, Unix platforms.
more information Quartus packages their available procedures, refer Packages Commands chapter Quartus Scripting Reference Manual.
Command-Line Processing
addition interactive shell, Quartus command-line executables support command-line switches executing scripts commands. When used with these switches, command-line executable quits when complete. command-line executables also provide switches performing specific Quartus operations. example, following c-shell script takes argument top-level design file entity name runs through entire HardCopy design flow.
!#/bin/csh quartus_sh -flow compile quartus_cdb -create_companion=%1_hcii quartus_sh -flow compile %1_hcii quartus_cdb -compare=%1_hcii
Altera Corporation June 2007
HardCopy Series Handbook, Volume
This example shows what perhaps, simplest execute HardCopy design flow. have developed applied design I/O, location timing constraints project, these constraints included during script execution.
more information Quartus executables command-line options, refer Command-Line Executables chapter Quartus Scripting Reference Manual Command-Line Scripting section volume Quartus Handbook. Quartus software supports both HardCopy first Stratix first design flows. Stratix first flow involves following:
HardCopy Design Flow
Compiling Stratix FPGA prototype Verifying Stratix FPGA prototype Migrating prototype design HardCopy design Compiling HardCopy design Transferring your HardCopy files Altera Design Center
Hardcopy first flow similar, starts with compiling HardCopy target device. Once HardCopy compile completes successfully, design migrated Stratix target. HardCopy design flow Quartus software shown Figure 6-1. begin design, create project revision Stratix FPGA prototype. Apply Quartus settings together with assignments timing constraints. Compile Stratix prototype revision (synthesis, place route, assembly) produce complete layout, with timing closure free from errors. perform additional functional timing verification necessary then implement verify prototype hardware. Once FPGA prototype verified, compile HardCopy design. Begin creating HardCopy companion revision FPGA prototype: Create HardCopy companion revision FPGA prototype. design settings constraints automatically migrated companion revision. Compile HardCopy revision. compile runs, Design Assistant checks errors. When compile completes, should correct errors resolve failures that appear Quartus reports.
Altera Corporation June 2007
HardCopy Design Flow
HardCopy Companion Revision Comparison tool compare HardCopy design against FPGA prototype. comparison tool checks structural equivalency consistency between revisions. there mismatches, prepare HardCopy design files transfer Altera Design Center. addition design verification Quartus software, flow generate files required perform Static Timing Analysis (STA) Synopsys' Primetime.
Figure 6-1. HardCopy Design Flow
Create Project
Source .vhd, .tdf .edf, .bdf Design Files
Make Global Assignments
Signal-Pin Assignment Files Prototype Stratix Design
Make Location Assignments
Timing Constraint Files
Make Timing Assignments
Compilation Report Files
Compile Stratix Prototype
Create HardCopy Companion Revision
Verify Stratix Prototype
Compile HardCopy Design
Compare Design Report File
Verify HardCopy Design
HardCopy Archive
Hand-Off Altera Design Center
Altera Corporation June 2007
HardCopy Design
Compilation Report Files
HardCopy Series Handbook, Volume
design flow Figure begins with Stratix FPGA prototype design migrates this design HardCopy device target, begins with HardCopy target migrates this design Stratix target FPGA prototyping. design flow both cases shown Figure 6-1.
more information HardCopy design flow alternative methods complete HardCopy designs using Quartus GUI, refer Quartus Support HardCopy Devices chapter Quartus Handbook HardCopy Design Considerations chapter volume HardCopy Series Handbook. following sections describe each step flow shown Figure explains each step completed using interactive shell.
Creating Project
Both FPGA HardCopy design Quartus software revolve around projects. must create project before begin working with design. project includes source design files (RTL schematics), Quartus tool settings, locations timing constraints. Although project contain many different revisions design, each revision have unique design constraints, target device settings, Quartus software settings. must explicitly open project before perform other operations project. must close current project switch different project revision. This section details different operations relating project management using commands.
Creating Stratix Prototype Project
create Stratix prototype project, project_new command. syntax this command tcl> project_new [-family <family>] [-overwrite] [-part <part>] [-revision <revision_name>] <project_name> only required argument this command project name, <project name>, although target device family, part code, revision name specified this time also. default, revision name same project name. device family part code later using set_global_assignment command. example, create
Altera Corporation June 2007
Creating Project
project called demo_design with default revision name demo_design unspecified target device family part, following command executed: tcl> project_new demo_design Creating project creates quartus settings file (QSF) Quartus Project file (QPF) current directory. addition, subdirectory created that used store Quartus database files. case demo_design project example, following files created project directory: demo_design.qpf demo_design.qsf demo_design.db_info
Opening Project
project created automatically opens when project_new command. future Quartus sessions, close project, must open project with command: project_open. syntax project_open command tcl> project_open [-current_revision] [-revision <revision_name>] <project_name> example, open default revision project demo_design, execute following command: tcl> project_open demo_design good practice have consistent names Stratix HardCopy revisions your project. This makes easy identify which revision which. example, naming your revisions projectname_fpga projectname_hcii would help easily identify which revision Stratix revision, which HardCopy revision.
Closing Project
Before ending Quartus project session, good practice close Quartus project using project_close command. This ensures that changes have made your project written Quartus file. syntax project_close command tcl> project_close [-dont_export_assignments]
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HardCopy Series Handbook, Volume
Project Example Script
following script shows commands opening closing project called demo_design with revision name, demo_design_fpga. project does already exist, created. This script makes project_exists project_open commands.
Example Script opening closing project Open Project demo_design. Project does Already Exist, Create [is_project_open] project_close [project_exists demo_design] project_open demo_design -revision demo_design_fpga else project_new demo_design -revision demo_design_fpga Include Other Commands Here Close project demo_design write changes settings demo_design.qsf project_close script
more information these other useful project-related commands, refer Project section Packages Commands chapter Quartus Scripting Reference Manual.
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Making Global Assignments
Making Global Assignments
Initializing HardCopy Design
HardCopy design, following operations required after Quartus project created:
Specify design source files (Verilog, VHDL, AHDL, EDIF, files) Specify Stratix prototype target family device name Specify HardCopy companion revision migration device Enable Design Assistant Make recommended HardCopy specific Quartus tool settings
addition these, other project settings affecting downstream tools, such synthesis place-and-route, made this time. operations listed above performed using set_global_assignment command. syntax this command tcl> set_global_assignment [-comment<comment>] [-disable] [-entity <entity_name>] -name <name> [-remove] [-section_id <section_id>] <value> most important parameters set_global_assignment command <name> <value>. <name> argument specifies Quartus global variable <value> value assigned that variable. steps initializing HardCopy design turn Design Assistant. When GUI, Design Assistant provides visual checklist running both Stratix HardCopy phases design. first-time users, this provide powerful guide successfully completing your HardCopy project.
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global variables HardCopy project listed Table 6-4.
Table 6-4. HardCopy Design Settings Global Variable Name <name>
VERILOG_FILE VHDL_FILE AHDL_FILE EDIF_FILE BDF_FILE FAMILY DEVICE TOP_LEVEL_ENTITY COMPANION_REVISION ENABLE_DRC_SETTINGS USE_TIMEQUEST_TIMING_ANALYZER SDC_FILE
Value Description <value>
Verilog file name. VHDL file name. Altera file name. EDIF file name. Altera schematic file name. Device family name, example, Stratix Prototype FPGA target device name. Top-level design entity module name. HardCopy target device name. HardCopy design revision name. Turn Design Assistant. TimeQuest default timing analyzer <ON>. File TimeQuest constraints <constraint_file.sdc>.
only need following settings when using Classic Timing Analyzer. Using Classic Timing Analyzer recommended. REPORT_IO_PATHS_SEPARATELY
Creates separate report panel input output timing results. domains constraints minimum maximum constraints paths).
Timing constraints checked completeness (all clock
DO_COMBINED_ANALYSIS
Timing analysis fast slow operating conditions best worst-case timing analysis, respectively. This must turned off. Verify recovery removal times asynchronous control reset signals. Clock latency included timing analysis asses clock-insertion timing clock skew.
IGNORE_CLOCK_SETTINGS ENABLE_CLOCK_LATENCY
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Making Global Assignments
DEVICE variables parts used Stratix prototype design HardCopy design. selected Stratix prototype device must compatible with selected HardCopy device make migration possible. Valid pairings these devices listed Table 6-5. variable, HardCopy part names listed Table used. DEVICE variables, Stratix part names include speed grade part. speed grade character code indicating industrial commercial speed indicator (number example, commercial part denoted using character speed grade two-character speed grade appended Stratix part name form value string DEVICE variable.
Table 6-5. Stratix Prototype Options HardCopy HardCopy Part
HC210F484C HC210W484C
(Part
Stratix Prototype Part
EP2S30F484C3 EP2S30F484C4 EP2S30F484C5 EP2S30F484I4 EP2S60F484C3 EP2S60F484C4 EP2S60F484C5 EP2S60F484I4 EP2S90H484C4 EP2S90H484C5
HC220F672C
EP2S60F672C3 EP2S60F672C4 EP2S60F672C5 EP2S60F672I4 EP2S90F780C4 EP2S90F780C5 EP2S130F780C4 EP2S130F780C5
HC220F780C
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Table 6-5. Stratix Prototype Options HardCopy HardCopy Part
HC230F1020C
(Part
Stratix Prototype Part
EP2S90F1020C3 EP2S90F1020C4 EP2S90F1020C5 EP2S90F1020I4 EP2S130F1020C3 EP2S130F1020C4 EP2S130F1020C5 EP2S130F1020I4 EP2S180F1020C3 EP2S180F1020C4 EP2S180F1020C5 EP2S180F1020I4
HC2401020C
EP2S180F1020C3 EP2S180F1020C4 EP2S180F1020C5 EP2S180F1020I4 EP2S180F1508C3 EP2S180F1508C4 EP2S180F1508C5 EP2S180F1508I4
HC240F1508C
following commands demonstrate setting DEVICE variables. tcl> set_global_assignment -name DEVICE EP2S90F1020C4 tcl> set_global_assignment -name HC230F1020C
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Making Global Assignments
Design Assistant
should turn Design Assistant beginning design process turning ENABLE_DRC_SETTINGS global variable. tcl> set_global_assignment -name ENABLE_DRC_SETTINGS Design Assistant runs concurrently with every step both prototype Stratix HardCopy design flows. When Design Assistant turned Quartus software checks ensure that project fully complies with HardCopy design rules requirements.
more information Design Assistant, refer Design Guidelines HardCopy Devices chapter volume HardCopy Series Handbook Quartus Support HardCopy Devices chapter Quartus Handbook.
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Example Script Making Global Assignments
example script below illustrates application global constraints HardCopy project.
Example Global Assignments Script HardCopy Design This Script Applies Settings EP2S90 Stratix prototype FPGA target HC230 HardCopy target Source Design File Settings =========================== set_global_assignment -name VERILOG_FILE demo_design.v set_global_assignment -name VERILOG_FILE example_ram.v Stratix Prototype FPGA Target Settings set_global_assignment -name FAMILY "Stratix set_global_assignment -name DEVICE EP2S90F1020C4 set_global_assignment -name TOP_LEVEL_ENTITY demo_design HardCopy Companion Revision Target Settings set_global_assignment -name COMPANION_REVISION_NAME demo_design_hardcopyii set_global_assignment -name HC230F1020 Design Assistant Assignments Settings Required HardCopy set_global_assignment -name ENABLE_DRC_SETTINGS set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR set_global_assignment -name REPORT_IO_PATHS_SEPARATELY following assignments Classic Timing Analyzer only used TimeQuest. set_global_assignment -name set_global_assignment -name DO_COMBINED_ANALYSIS set_global_assignment -name IGNORE_CLOCK_SETTINGS set_global_assignment -name set_global_assignment -name ENABLE_CLOCK_LATENCY Script
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Making Global Assignments
Making Assignments
Because complex rules governing programmable cells their availability specific pins packages, Altera highly recommends that assignments completed using Planning tool Assignment Editor Quartus GUI. These tools ensure that rules regarding each cell applied correctly. Quartus export script containing assignments specifications. assignments described here information only. more information location type assignments using Quartus Assignment Editor Planner tools, refer Assignment Editor chapter volume Quartus Handbook. this section, specification considered parts:
assignments type assignments
Assignments
Design signals assigned package balls using set_location_assignment command. syntax this command given below: tcl> set_location_assignment [-comment <comment>] [-disable] [-remove] <destination> <value> Here, <destination> package ball name <value> design signal name. FBGA packages, ball name follows form PIN_<coordinate>. example, assign design signal data_out[15] package ball AL17: tcl> set_location_assignment PIN_AL17 data_out[15]
Setting Type Parameters
type parameter specification, set_instance_assignment command used. syntax this command tcl> set_instance_assignment [-comment <comment>] [-disable] [-entity <entity_name>] [-from <source>] -name <name> [-remove] [-section_id <section_id>] [-to <destination>] <value>
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HardCopy Series Handbook, Volume
assignment name, <name>, should IO_STANDARD indicate that specification being applied. related signal specified <destination>. destination argument string providing details type, such levels standards. Table lists strings corresponding standards supported HardCopy devices.
Table 6-6. Standard Strings Type <name> LVTTL LVCMOS
"3.3-V PCI" "3.3-V PCI-X" "1.5 "1.8 "2.5 "1.5-V HSTL CLASS "1.5-V HSTL CLASS "1.8-V HSTL CLASS "1.8-V HSTL CLASS "DIFFERENTIAL 1.5-V HSTL CLASS "DIFFERENTIAL 1.5-V HSTL CLASS "DIFFERENTIAL 1.8-V HSTL CLASS "DIFFERENTIAL 1.8-V HSTL CLASS "DIFFERENTIAL 1.8-V SSTL CLASS "DIFFERENTIAL 1.8-V SSTL CLASS "DIFFERENTIAL SSTL-2" "DIFFERENTIAL 2.5-V SSTL CLASS "SSTL-18 CLASS "SSTL-18 CLASS "SSTL-2 CLASS "SSTL-2 CLASS LVDS HYPERTRANSPORT LVPCL
Description LVTTL LVCMOS
3.3-V 3.3-V 1.5-V 1.8-V 2.5-V QDRII SRAM 1.5-V QDRII SRAM 1.5-V QDRII SRAM/RLDRAM 1.8-V QDRII SRAM/RLDRAM 1.8-V Memory clock interface Memory clock interface Memory clock interface Memory clock interface DDR2 SDRAM DDR2 SDRAM SDRAM SDRAM DDR2 SDRAM DDR2 SDRAM SDRAM SDRAM 2.5-V differential signaling 2.5-V differential signaling Differential
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Making Global Assignments
specify number other parameters using set_instance_assignment command. Some more common parameters listed Table 6-7.
Table 6-7. Common Parameter Settings <name> setting weak_pull_up_resistor output_pin_load <value> setting
integer
Description
Implement weak pull-up resistor pin. Capacitive load output bidirectional pin. Units Implements fast output register cell adjacent LAB. Implement fast output enable register cell or/and adjacent LAB. Implements fast input register cell adjacent LAB. Drive strength output bidi pin.
fast_output_register
fast_output_enable_register
fast_input_register
current_strength_new
minimum_current
maximum_current stratixii_termination
differential On-chip termination "series ohms with calibration" impedance matching) "series ohms without calibration" pin. "series ohms with calibration" "series ohms without calibration"
more information availability HardCopy devices, refer Structures Features section volume HardCopy Series Handbook.
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HardCopy Series Handbook, Volume
Assignment Example Script
following script example specifies several different constraints.
Signal-Ball Assignments set_location_assignment PIN_AH5 addr_out[0] set_location_assignment PIN_AH6 addr_out[1] set_location_assignment PIN_AJ5 data_in[0] set_location_assignment PIN_AJ6 data_in[1] set_location_assignment PIN_AJ32 resetn set_location_assignment PIN_AM17 ref_clk Type Parameter Assignments set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment set_instance_assignment set_instance_assignment set_instance_assignment set_instance_assignment set_instance_assignment set_instance_assignment set_instance_assignment data_in[1] -name -name -name -name -name -name -name -name
"1.5-V HSTL CLASS "1.5-V HSTL CLASS "1.5-V HSTL CLASS "1.5-V HSTL CLASS LVDS resetn LVCMOS ref_clk
addr_out[0] addr_out[1] data_in[0] data_in[1]
fast_input_register data_in[0] fast_input_register data_in[1] fast_output_register addr_out[0] fast_output_register addr_out[1] output_pin_load addr_out[0] output_pin_load addr_out[1] current_strength_new 16mA addr_out[0] stratixii_termination "series ohms without calibration"\
Assigning Timing Constraints
Planning Design Timing Constraints
Timing constraints ensure that design compiled Quartus software meets specific timing requirements. When target FPGA, decide apply complete timing constraints, choosing instead timing problems your prototype system when they arise. HardCopy devices, however, cannot modified using reconfiguration timing problems, critically important that design fully constrained. Designs fully constrained would result significantly different timing characteristics between prototype Stratix FPGA HardCopy device. fully constraining design, Altera guarantee that both Stratix FPGA HardCopy device fully complies with your timing specifications.
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Assigning Timing Constraints
minimum timing constraints HardCopy design are:
Clock settings (FMAX) each every clock domain Minimum maximum delays paths, including asynchronous reset control signals
addition, good design practice develop timing constraints cover:
Specific cross-clock domain timing requirements False paths Multicycle paths
TimeQuest, timing constraints written TimeQuest format read from file. example file demo_design.sdc. "Using TimeQuest" page 6-30. Classic Timing Analyzer, timing constraints applied using dedicated commands assigning timing-specific attributes using set_instance_assignment command. This section provides overview timing constraint development using commands.
more information timing constraints, refer Timing Analysis section volume Quartus Handbook.
Specifying System Clocks
most basic constraints that should applied describe clock each clock domain. Parameters usually specified each clock are:
Clock period Latency assignments) Uncertainty (set_clock_uncertainty command)
Clock uncertainty specified with set_clock_uncertainty command models uncertainty clock period, including jitter, often used introduce some margin into target clock frequency. following example constraints illustrate clock definition design with clock domains, clk_a clk_b. this case, both clocks MHz, with different clock latency skew.
Example TimeQuest Constraints Defining Clocks clk_a clk_b create_clock -period 10.0 -name clk_a [get_ports clk_a] set_clock_latency -source -late clk_a set_clock_latency -source -early clk_a
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HardCopy Series Handbook, Volume
set_clock_uncertainty clk_a 0.25 create_clock -period 10.0 set_clock_latency -source set_clock_latency -source set_clock_uncertainty -name clk_b [get_ports clk_b] -late clk_b -early clk_b clk_b 0.25
Input/Output Timing
System clock parameters define setup hold timing register register paths within each clock domain. timing parameters used describe register, register timing. set_input_delay constraint used specify delay from source external chip input pin, relative defined clock. syntax this command given below. set_input_delay -clock <clock name> [-clock_fall] [-rise -fall] [-max -min] [-add_delay] [-reference_pin <pin port>] <delay value> <port list> <clock name> argument specifies reference clock delay. <port list> argument top-level input signal design, <delay value> external delay. external delay measured from positive (rising) edge <clock> unless -clock_fall argument specified. -min -max arguments used specify whether <delay value> minimum maximum external delay, respectively. set_output_delay constraint similar set_input_delay constraint except that specifies delay from output external destination relative clock. set_output_delay -clock <clock name> [-clock_fall] [-rise -fall] [-max -min] [-add_delay] [-reference_pin <pin port>] <delay value> <port list>
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Assigning Timing Constraints
example, following script specifies input output delays signals. Input data_in[0] minimum maximum external delays respectively. Output data_out[0] minimum maximum external delays respectively. external input delays data_in[0] relative positive edge clock ref_clk external output delays data_out[0] relative negative edge clock ref_clk.
Script Setting Timing Using set_input_delay set_output_delay set_input_delay -clock ref_clk -max [get_ports data_in[0]] set_input_delay -clock ref_clk -min [get_ports data_in[0]] set_output_delay -clock ref_clk -max [get_ports data_out[0]] set_output_delay -clock ref_clk -min [get_ports data_out[0]]
Creating Timing Exceptions
Timing exceptions used correct timing constraints covered clock settings timing settings. most common these multicycle paths false paths. TimeQuest, multicycle paths described using set_multicycle_path constraint. syntax this constraint set_multicycle_path [-setup][-hold][-start] Classic Timing Analyzer, multicycle paths described using set_multicycle_assignment command. syntax this command tcl> set_multicycle_assignment [-comment <comment>] [-disable] [-end] [-from <from_list>] [-hold] [-remove] [-setup] [-start] [-to <to_list>] <path_multiplier> either timing analyzer, multicycle assignments made with -setup argument, specify maximum number cycles, with -hold argument, specify minimum number cycles path. False paths describe paths that should included timing optimization analysis operations. Quartus software, there number ways describe false paths. default, Classic Timing Analyzer, feedback from output input side bidirectional I/O, read-while-write paths through memories, cross-clock domain paths timed during optimization timing analysis. default, Time Quest, cross-clock domain paths timed.
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HardCopy Series Handbook, Volume
change these default settings, refer Timing Settings section Quartus Support HardCopy Series Devices chapter volume Quartus Handbook. TimeQuest, constraint set_false_path used describe paths that should included timing optimization analysis. syntax this constraint tcl> set_false_path [-from <from list>] [-to list>] [-thru <thru list>] Classic Timing Analyzer, most common command controlling false paths set_timing_cut_assignment command. syntax this command tcl> set_timing_cut_assignment [-comment <comment>] [-disable] [-from <from_pin_list>] [-remove] [-to <to_pin_list>] paths between nodes <from_pin_list> nodes <to_pin_list> excluded from timing optimization analysis operations.
Example TimeQuest Constraints
Timing Assignments ================== create_clock -period 10.0ns -name ref_clk ref_clk set_clock_latency -late ref_clk set_clock_latency -early ref_clk set_clock_uncertainty -hold ref_clk 0.250ns set_clock_uncertainty -setup ref_clk 0.250ns Input delay (max) (min) data_in[1:0] set_input_delay -clock ref_clk -max data_in set_input_delay -clock ref_clk -min data_in Output delay (max) (min) data_out[1:0] set_output_delay -clock ref_clk -max data_out set_output_delay -clock ref_clk -min data_out Don't care about timing resetn net. false path set_false_path -from resetn
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Compiling Stratix Prototype Design
Example Classic Timing Analyzer Script
Timing Assignments ================== create_base_clock -fmax -target ref_clk ref_clk set_instance_assignment -name LATE_CLOCK_LATENCY ref_clk set_instance_assignment -name EARLY_CLOCK_LATENCY ref_clk set_clock_uncertainty -hold ref_clk 0.250ns set_clock_uncertainty -setup ref_clk 0.250ns Input delay (max) (min) data_in[1:0] set_input_delay -clk_ref ref_clk -max data_in 6.0ns set_input_delay -clk_ref ref_clk -min data_in 2.0ns Output delay (max) (min) data_out[1:0] set_output_delay -clk_ref ref_clk -max data_out 6.0ns set_output_delay -clk_ref ref_clk -min data_out 2.0ns Don't care about timing resetn net. false path set_timing_cut_assignment -from resetn
This section provided overview commands applying timing constraints.
more information application timing constraints using commands, refer Packages Commands chapter Quartus Scripting Reference Manual. Once global assignments, resource assignments, timing assignments have been specified, next step design process compile Stratix FPGA prototype design. execute_flow command provided this purpose supports various arguments affecting compilation process. syntax this command tcl> execute_flow [-analysis_and_elaboration] [-attempt_similar_placement] [-check_ios] [-check_netlist] [-compile] [-compile_and_simulate] [-early_timing_estimate] [-eco] [-export_database] [-fast_model] [-import_database]
Compiling Stratix Prototype Design
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switches relevant prototype Stratix HardCopy design listed Table 6-8.
Table 6-8. execute_flow Command Switches Switch analysis_and_elaboration attempt_similar_placement check_ios check_netlist compile compile_and_simulate early_timing_estimate export_database fast_model generate_functional_sim_netlist import_database Description
Perform synthesis mapping target Altera technology Runs Attempt Similar Placement Verify assignments Perform syntax checks netlist Execute Quartus compilation flow compile, also simulation Runs early timing estimator Executes Fitter compilation Exports Version-Compatible Database Runs Timing Analysis (fast mode analysis) Generate Simulation Netlist Imports Version-Compatible Database
important note that HardCopy switches execute_flow command HardCopy Stratix designs, HardCopy designs.
simplest execute_flow command -compile switch. tcl> execute_flow -compile Running execute_flow command this executes four stages Quartus compilation flow with default settings each stage:
Analysis Synthesis Fitter Timing Analysis Assembler
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Compiling HardCopy Design
Design Assistant Timing constraint checks they enabled Quartus Settings file. should check assignments avoid problems downstream compile operations. this, execute_flow compilation broken into three steps: tcl> execute_flow -analysis_and_elaboration tcl> execute_flow -check_ios tcl> execute_flow -compile
should noted that, interests clarity brevity, fragments given here incorporate error checking. However, good practice include code your scripts that checks success your design proceeds. case execute_flow procedure, return value used with catch command handle success failure. example below shows option doing this. Determine compilation successful print personalized message. {[catch {execute_flow -compile} result]} puts "\nResult: $result\n" puts "ERROR: Compilation failed. report files.\n" else puts "\nINFO: Compilation successful.\n"
more information execute_flow command, refer command description Packages Commands chapter Quartus Scripting Reference Manual. Once Stratix FPGA prototype design compiled verified, compile HardCopy revision design. This two-step process: Create HardCopy companion revision. Compile HardCopy companion revision.
Compiling HardCopy Design
create HardCopy version design, execute_hardcopyii command with -create_companion option: tcl> execute_hardcopyii -create_companion demo_design_hcii
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This command initializes database HardCopy revision creates file this example, demo_design_hcii.qsf), ensuring that constraints Stratix FPGA revision ported over. Next, current working revision Quartus project changed HardCopy revision design compiled HardCopy device target:
tcl> set_current_revision demo_design_hcii tcl> execute_flow -compile
with prototype Stratix revision, report files generated project directory each tools that executed.
Understanding Report Files
execute_flow command generates number report files project directory. These files summarize messages displayed console during compilation provide additional information about design. name each report file follows format <revision><tool short name>.summary <revision><tool short name>.rpt, where <revision> revision name current design. .summary file contains brief summary messages results from tool while .rpt file contains more detailed messages information. HardCopy project, sets report files generated: Stratix prototype FPGA revision HardCopy revision. Table describes different report files. report package provides powerful collection procedures customizing managing report files related Quartus fitter timing analysis engines.
more information customizing managing report files, refer Packages Commands report section Quartus Reference Manual.
Table 6-9. Stratix Compile Report File Descriptions Switch
<revision>.map.rpt
(Part Description
Tool
Analysis Synthesis
Synthesis settings, source files, messages, resource usage. Implementation equations device resource instantiations. Fitter settings, layout optimizations, resources, pin-out, messages. Implemented equations device resource instantiations after fitting. Design rule settings, violations, messages.
<revision>.map.eqn Analysis Synthesis <revision>.fit.rpt <revision>.fit.eqn <revision>.drc.rpt Fitter Fitter Design Assistant
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Comparing FPGA HardCopy Revisions
Table 6-9. Stratix Compile Report File Descriptions Switch
<revision>.upc.rpt <revision>.asm.rpt <revision>.rec.rpt <revision>.flow.rpt <revision>.sta.rpt
(Part Description
Tool
Timing Constraint Checker Assembler Companion Revision Comparison Flow TimeQuest
Constraint coverage information. Assembler settings, .pof .sof output file options, messages. status report structural comparison between HardCopy revision Stratix Prototype design. Resource summary execution time each tool flow. This report updated different tools flow complete. TimeQuest timing analysis report.
Comparing FPGA HardCopy Revisions
Before submitting HardCopy project Altera Design Center, should checked against Stratix prototype FPGA revision. this, execute_hardcopyii command with -compare option from quartus_sh shell: tcl> execute_hardcopyii -compare Running this command generates report file summary file project directory. These files called <revision_name>.rec.rpt <revision_name>.rec.summary. command checks verify that following items conform HardCopy design rules consistent between HardCopy Stratix revisions:
Source design files device netlist files User clock assignments Timing constraints (assignments) location type assignments parameters Memory implantation parameters implementation parameters Global resource properties Properties other device resources used
errors failures comparison reported .rec report files. example .rec file given below. Note that this example, design comparison checks HardCopy Companion Revision Comparison Summary table marked passed, indicating that HardCopy design Quartus software finished ready hand-off back-end engineering team Altera Design Center. must resolve failures that show Comparison Summary before proceed further with your design.
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HardCopy Companion Revision Comparison report demo_design_hardcopyii 15:30:07 2006 Version Build 06/20/2006 Service Pack Full Version Table Contents Legal Notice HardCopy Companion Revision Comparison Summary Atom Netlist Comparison Summary Information HardCopy Companion Revision Comparison Messages
HardCopy Companion Revision Comparison Summary +-+-+ HardCopy Companion Revision Comparison Status Analyzed 15:29:55 2006 Quartus Version Build 06/20/2006 Full Version Revision Name demo_dsign_hardcopyii Top-level Entity Name demo_design Family Stratix Compare Status Passed (14/14) Source Files Compared Passed (121/121) Assignments Compared Passed User Clocks Compared Passed (0/0) Resource Counts Compared Passed (5/5) Structure Compared Passed (130/130) Package Pins Compared Passed (1020/1020) Structure Compared Passed (1/1) Clocks Compared Passed (2/2) Timing Constraints Compared Passed (3/3) Information Compared Passed (10/10) Information Compared Passed (100/100) Global Resources Compared Passed (8/8) Atom Compared Passed (335084/335084) Atom Netlist Compared Passed (1/1) +-+-+
Performing Static Timing Analysis
Static Timing Analysis Quartus Software
global assignments made Stratix prototype HardCopy revisions ensure that Static Timing Analysis (STA) both fast slow operating conditions both setup hold timing verified.
Using TimeQuest
timing analysis independent compile process ways: execute_module -tool command timing analysis script quartus_sta from within basic quartus shell, quartus_sh.
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Performing Static Timing Analysis
quartus_sta interactive shell independently execute commands scripts prompt.
Using Classic Timing Analyzer
timing analysis independent compile process ways: execute_module -tool command timing analysis script quartus_tan from within basic quartus shell, quartus_sh. quartus_tan interactive shell independently execute commands scripts prompt.
more information running static timing analysis Quartus software, refer Timing Analysis section Quartus Handbook. commands related static timing analysis, refer Timing section Packages Commands Quartus Scripting Reference Manual.
Static Timing Analysis Primetime
Quartus software also generate files required Synopsys' PrimeTime. following example commands direct Quartus software generate PrimeTime files STA.
Script Generate PrimeTime File Output execute_module -tool -args -tq2pt execute_module -tool -args "-tool primetime -format verilog -timing_analysis"
files generated Quartus software organized subdirectory within project directory. example, after compiling Stratix prototype design (demo_design), following verilog (.vo) (.sdo) PrimeTime script (.tcl) created project directory.
timing\ primetime\ demo_design_v.sdo demo_design.pt.tcl demo_design.collections.sdc demo_design.constraints.sdc
script includes timing constraints applied during Quartus software compilation.
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HardCopy Example Script
following script draws together ideas discussed thus into top-level script quartus_sh shell. This script implements HardCopy design called demo_design. begins creating project, called demo_design, compiling Stratix FPGA prototype, creating HardCopy companion revision then compiling companion revision. Finally, revision comparison tool verify that both revisions consistent. this example, global, pin, timing assignment scripts read into top-level script using source command. sourced scripts listed after top-level script listing.
Top-Level Example Script demo_design.tcl
demo_design.tcl Top-level script executing HardCopy design quartus_sh load_package flow Open create Stratix FPGA prototype revision [is_project_open] project_close {[project_exists demo_design]} project_open demo_design else project_new demo_design Apply global design settings source global_assignments.tcl Apply assignments source pin_assignments.tcl Apply FPGA timing constraints source timing_assignments.tcl Compile Stratix FPGA prototype design execute_flow -compile #Create switch HardCopy target revision execute_hardcopyii -create_companion demo_design_hcii project_close project_open demo_design -revision demo_design_hcii Compile HardCopy design revision execute_flow -compile Check HardCopy revision make sure matches FPGA design execute_hardcopyii -compare
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HardCopy Example Script
Generate HardCopy Handoff Report execute_hardcopyii -handoff_report Archive HardCopy Handoff Files into file named "demo_design_hcii_handoff.qar" execute_hardcopyii -archive demo_design_hcii_handoff.qar Quit quartus_sh qexit demo_design.tcl
Global Assignments Script global_assignments.tcl
global_assignments.tcl script source top-level script, demo_design.tcl prepares global variables, target devices, revision names HardCopy project:
global_assignments.tcl Source Design File Settings =========================== set_global_assignment -name VERILOG_FILE demo_design.v set_global_assignment -name VERILOG_FILE example_ram.v Constraint File Settings TimeQuest ============================ set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER set_global_assignment -name SDC_FILE demo_design.sdc Stratix Prototype FPGA Target Settings set_global_assignment -name FAMILY "Stratix set_global_assignment -name DEVICE EP2S90F1020C4 set_global_assignment -name TOP_LEVEL_ENTITY demo_design HardCopy Companion Revision Target Settings set_global_assignment -name COMPANION_REVISION_NAME demo_design_hardcopyii set_global_assignment -name HC230F1020 Design Assistant Assignments Settings Required HardCopy set_global_assignment -name ENABLE_DRC_SETTINGS set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR set_global_assignment -name REPORT_IO_PATHS_SEPARATELY following assignments Classic Timing Analyzer only used TimeQuest. set_global_assignment -name set_global_assignment -name DO_COMBINED_ANALYSIS set_global_assignment -name IGNORE_CLOCK_SETTINGS
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set_global_assignment -name set_global_assignment -name ENABLE_CLOCK_LATENCY global_assignments.tcl
Assignments Script pin_assignments.tcl
pin_assignments.tcl script from top-level script, demo_design.tcl, specifies top-level design signal package ball assignments parameters:
pin_assignments.tcl set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment set_location_assignment
PIN_AH5 addr_out[0] PIN_AH6 addr_out[1] PIN_AJ5 data_in[0] PIN_AJ6 data_in[1] PIN_AJ32 resetn PIN_AM17 ref_clk
Type Parameter Assignments set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment -name IO_STANDARD set_instance_assignment set_instance_assignment set_instance_assignment set_instance_assignment -name -name -name -name
"1.5-V HSTL CLASS "1.5-V HSTL CLASS "1.5-V HSTL CLASS "1.5-V HSTL CLASS LVDS resetn LVCMOS ref_clk
addr_out[0] addr_out[1] data_in[0] data_in[1]
fast_input_register data_in[0] fast_input_register data_in[1] fast_output_register addr_out[0] fast_output_register addr_out[1]
set_instance_assignment -name output_pin_load addr_out[0] set_instance_assignment -name output_pin_load addr_out[1] pin_assignments.tcl
TimeQuest Constraint File demo_design.sdc
TimeQuest reads file demo_design.sdc applies timing constraints system clock, ref_clk, I/O-to-core timing specifications.
constraints.sdc create_clock -period 10.0 -name ref_clk [get_ports ref_clk] set_clock_latency -late ref_clk set_clock_latency -early ref_clk set_clock_uncertainty -hold ref_clk 0.250 set_clock_uncertainty -setup ref_clk 0.250 Input delay (max) (min) data_in[1:0] set_input_delay -clock ref_clk -max [get_ports data_in]
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Summary
set_input_delay -clock ref_clk -min [get_ports data_in] Output delay (max) (min) data_out[1:0] set_output_delay -clock ref_clk -max [get_ports data_out] set_output_delay -clock ref_clk -min [get_ports data_out] Don't care about timing resetn net. false path set_false_path -from [get_ports resetn] timing_assignments.tcl
Timing Assignments Script timing_assignments.tcl
using Classic Timing Analyzer, timing_assignments.tcl script from top-level script, demo_design.tcl. This script applies timing constraints system clock, ref_clk, I/O-to-core timing specifications.
timing_assignments.tcl create_base_clock -fmax 10.0ns -target ref_clk ref_clk set_instance_assignment -name LATE_CLOCK_LATENCY ref_clk set_instance_assignment -name EARLY_CLOCK_LATENCY ref_clk set_clock_uncertainty -hold ref_clk 0.250ns set_clock_uncertainty -setup ref_clk 0.250ns Input delay (max) (min) data_in[1:0] set_input_delay -clk_ref ref_clk -max data_in 6.0ns set_input_delay -clk_ref ref_clk -min data_in 2.0ns Output delay (max) (min) data_out[1:0] set_output_delay -clk_ref ref_clk -max data_out 6.0ns set_output_delay -clk_ref ref_clk -min data_out 2.0ns Don't care about timing resetn net. false path set_timing_cut_assignment -from resetn timing_assignments.tcl
Summary
This chapter introduced script-based design HardCopy devices using Quartus interactive shell. This approach provides with alternative GUI-based design certain situations such remote-terminal Quartus execution, design flow automation, even simply more comfortable operating scripting environment.
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Document Revision History
Table 6-10 shows revision history this chapter.
Table 6-10. Document Revision History Date Document Version
June 2007, v1.2 December 2006 v1.1 Minor text edits. Updates Quartus software version 6.1.0 Added information command-line executable quartus_sta, newly available Quartus software version 6.1.0, recommended HardCopy design timing analysis. Updated Figure 6-1. Updated Table 6-1, Table 6-2, Table 6-3. Added revision history. Formerly chapter content change. Initial release Script-Based Design Hardcopy Devices. medium update chapter, changes Quartus software version release.
Changes Made
Summary Changes
March 2006 October 2005 v1.0
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H51025-1.2 Quartus software includes command-line executables, ma

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