H51012-2.4 Configuring FPGA process loading design data into devi

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Power-Up Modes Configuration Emulation HardCopy Series Devices
H51012-2.4
Configuring FPGA process loading design data into device. Altera's SRAM-based Stratix® Stratix, APEX20KC, APEX 20KE FPGAs require configuration each time device powered After device powered down, configuration data within Stratix Stratix, APEX device lost must loaded again power There several ways configure these FPGAs. details various configuration schemes available these FPGAs explained Configuration Handbook. HardCopy® series devices mask-programmed cannot configured. However, addition capability being instantly upon power (like traditional ASIC device), these devices mimic behavior FPGA during configuration process necessary. This chapter addresses various power-up options HardCopy series devices. This chapter also discusses configuration emulated HardCopy series devices while retaining benefits seamless migration provides examples replace FPGAs system with HardCopy series devices.
HardCopy Power-Up Options
HardCopy series devices feature three variations instant power-up modes configuration emulation power-up mode. They follows:
Instant Instant after Configuration emulation FPGA configuration sequence must choose power-up option when submitting design database Altera migrating HardCopy series device. Once HardCopy series devices manufactured, power-up option cannot changed.
HardCopy some HardCopy Stratix devices support configuration emulation. Refer "Configuration Emulation FPGA Configuration Sequence" page 20-9 more information.
Altera Corporation June 2007
20-1
HardCopy Series Handbook, Volume
HardCopy HardCopy Stratix devices retain functionality VCCSEL PORSEL pins from prototyping Stratix Stratix FPGAs. signals affect HardCopy series power-up behavior using power option. Refer Stratix Device Handbook Stratix Device Handbook proper these additional signals.
Instant Options
Instant traditional power-up scheme most ASIC non-volatile devices. instant mode fastest power-up option HardCopy series device used when HardCopy series device powers independently while other components board still require initialization configuration. Therefore, must verify signals that propagate from HardCopy series device (for example, reference clocks other input pins) stable affect HardCopy series device operation. There variations instant power-up modes available HardCopy devices.
Instant added delay) Instant after (additional delay)
Instant Added Delay)
instant power-up mode, once power supplies ramp above HardCopy series device's power-on reset (POR) trip point, device initiates internal sequence. When this sequence complete, HardCopy series device transitions initialization phase, which releases CONF_DONE signal pulled high. Pulling CONF_DONE signal high indicates that HardCopy series device ready normal operation. Figures 20-1 20-3 show instant timing waveform relationships configuration signals, VCC, user pins with respect HardCopy series device's normal operation mode. During power-up sequence, internal weak pull-up resistors pull user pins high. Once initialization phase complete, pins released. Similar FPGA, nIO_pullup transitions high, weak pull-up resistors disabled. Refer table that provides recommended operating conditions handbook specific device. value internal weak pull-up resistors pins Operating Conditions table specific FPGA's device handbook.
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Altera Corporation June 2007
HardCopy Power-Up Options
Instant After 50-ms Delay
instant after 50-ms delay power-up mode similar instant power-up mode. However, this case, device waits additional following internal sequence before releasing CONF_DONE pin. This option useful other devices board (such microprocessor) must initialized prior normal operation HardCopy series device. on-chip oscillator generates 50-ms delay after power-up sequence. During sequence delay period, user pins driven high internal, weak pull-up resistors. Just like instant mode, these pull-up resistors affected nIO_pullup pin. Similar APEX FPGAs, HardCopy APEX devices have nIO_pullup function. Their internal, weak pull-up resistors enabled during power-up initialization phase.
FPGA, initialization phase occurs immediately after configuration where registers reset, PLLs used initialized, pins used enabled device transitions into user mode. When HardCopy series device uses instant instant after 50-ms modes, configuration sequence necessary, HardCopy series device transitions into initialization phase after power-up sequence immediately after 50-ms delay. Figures 20-1 20-3 show instant timing waveform relationships configuration signals, VCC, user pins with respect HardCopy series device's normal operation mode. Tables 20-1 20-3 define timing parameters each HardCopy series device waveforms, also show effect PORSEL power must driven externally these waveforms apply. Figure 20-1 shows instant power-up waveform, where HardCopy device powered nCONFIG, nSTATUS, CONF_DONE driven externally.
Altera Corporation June 2007
20-3
HardCopy Series Handbook, Volume
Figure 20-1. Timing Waveform Instant Option Notes (1), (2), (3), (4),
(ALL) nCONFIG nSTATUS CONF_DONE User INIT_DONE
"don't care" "don't care" "don't care" "don't care" "don't care" High-Z User Mode
tPOR
tADD
Notes Figure 20-1:
(ALL) represents either power pins last power powered specified operating conditions. HardCopy power pins must powered within specifications described under Socketing sections. nCONFIG, nSTATUS, CONF_DONE must driven externally this waveform apply. User pins tri-stated driven before during power Socketing sections more details. nIO_pullup affect state user pins during initialization phase. INIT_DONE optional that enabled FPGA using Quartus software. HardCopy series devices carry over INIT_DONE functionality from prototyped FPGA design. nCEO asserted about same time CONF_DONE released. However, must driven externally this waveform apply.
alternative power-up waveform Figure 20-1 nCONFIG externally held longer than PORSEL delay. This delays initialization sequence small amount indicated Figure 20-2. addition, Figure 20-2 instant power-up waveform where nCONFIG momentarily held nSTATUS CONF_DONE driven externally.
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Altera Corporation June 2007
HardCopy Power-Up Options
Figure 20-2. Timing Waveform Instant Option Where nCONFIG Held After Power Notes (1), (2), (3), (4), (5),
(ALL) nCONFIG nSTATUS CONF_DONE User INIT_DONE
"don't care" "don't care" "don't care" "don't care" High-Z User Mode
tPOR Longer
tCF2ST1
tADD
Notes Figure 20-2:
This waveform applies nCONFIG held longer than tPOR delay. (ALL) represents either power pins last power powered specified operating conditions. HardCopy power pins must powered within specifications described under Socketing sections. nCONFIG, nSTATUS, CONF_DONE must driven externally this waveform apply. User pins tri-stated driven before during power Socketing sections more details. nIO_pullup affect state user pins during initialization phase. INIT_DONE optional that enabled FPGA using Quartus software. HardCopy devices carry over INIT_DONE functionality from prototyped FPGA design. nCEO also asserted about same time CONF_DONE released. However, must driven externally this waveform apply.
Pulsing nCONFIG signal FPGA re-initializes configuration sequence. nCONFIG signal HardCopy series device also restarts initialization sequence. Figure 20-3 shows instant behavior configuration signals user pins nCONFIG pulsed while supplies already powered stable.
Altera Corporation June 2007
20-5
HardCopy Series Handbook, Volume
Figure 20-3. Timing Waveform Instant Option When Pulsing NConfig Notes (1), (2), (3), (4),
(ALL) nCONFIG nSTATUS CONF_DONE User INIT_DONE
"don't care" "don't care" High User Mode
tCF2ST0
tCF2ST1
tADD
Notes Figure 20-3:
(ALL) represents either power pins last power powered specified operating conditions. HardCopy power pins must powered within specifications described under Socketing sections. nSTATUS CONF_DONE must driven externally this waveform apply. nIO_pullup affect state user pins during initialization phase. INIT_DONE optional that enabled FPGA using Quartus software. HardCopy devices carry over INIT_DONE functionality from prototyped FPGA design. nCEO also asserted about same time CONF_DONE released. However, must driven externally this waveform apply.
FPGA, INIT_DONE signal remains high several clock cycles after nCONFIG signal asserted, after which time INIT_DONE goes low. HardCopy series device, INIT_DONE signal starts low, shown Figure 20-3, regardless logic state nCONFIG signal. INIT_DONE signal transitions high only after CONF_DONE signal transitions high.
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Altera Corporation June 2007
HardCopy Power-Up Options
Tables 20-1 through 20-3 show timing parameters instant mode. These tables also show time taken completing instant power-up sequence Figure 20-1 page 20-4 HardCopy series devices. This option typical ASIC's functionality.
Table 20-1. Timing Parameters Instant Mode HardCopy Devices Parameter
tCF2ST0 tCF2ST1
Description PORSEL delay
nCONFIG
Condition
Typical
Units
Instant After added delay 1100
nSTATUS
nCONFIG high nSTATUS high
Additional delay
CONF_DONE delay
User mode delay
Note Table 20-1:
This parameter similar Stratix FPGA specifications. Refer Configuration Handbook more information.
Table 20-2. Timing Parameters Instant Mode HardCopy Stratix Devices Parameter
tCF2ST0 tCF2ST1
Description PORSEL delay
nCONFIG
Condition
Typical
Units
Instant After added delay
nSTATUS
nCONFIG high nSTATUS high
Additional delay
CONF_DONE delay
User mode delay
Note Table 20-2
This parameter similar Stratix FPGA specifications. Refer Configuration Handbook more information.
Altera Corporation June 2007
20-7
HardCopy Series Handbook, Volume
Table 20-3. Timing Parameters Instant Mode HardCopy APEX Devices Parameter
tCF2ST0 tCF2ST1
Description
delay nCONFIG nSTATUS nCONFIG high nSTATUS high
Condition
Typical
Units
Instant After added delay
Additional delay
CONF_DONE delay
User mode delay
Note Table 20-3:
This parameter similar APEX FPGA specifications. Refer Configuration Handbook more information.
correct operation HardCopy series device using instant option, pull nSTATUS, nCONFIG, CONF_DONE pins VCC. HardCopy series devices, these pins designed with weak internal resistors pulled VCC. Many FPGA configuration schemes require pull-up resistors these pins, they already present board. some HardCopy series device applications, remove these external pull-up resistors. Altera recommends leaving external pull-up resistors board following conditions exists.
more information, refer Designing with 1.5-V Devices chapter Stratix Device Handbook.
There more than HardCopy series and/or FPGA board HardCopy design uses configuration emulation design uses MultiVolt configurations
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Altera Corporation June 2007
HardCopy Power-Up Options
FPGA, enable INIT_DONE Quartus software. used INIT_DONE FPGA prototype, HardCopy series device retains function.
HardCopy series devices, INIT_DONE settings option masked-programmed into device. must submit these settings Altera with final design prior migrating HardCopy series device. INIT_DONE option other option pins (for example, DEV_CLRn DEV_OE) available Fitter Device Options sections Quartus report file. HardCopy HardCopy Stratix devices, PORSEL setting delays sequence similar prototyping FPGA. more information PORSEL settings FPGA, refer Configuration Handbook.
some FPGA configuration schemes, inputs DCLK DATA[7.0] float configuration device removed from board. HardCopy series devices, these pins designed with weak, internal pull-up resistors, pins left unconnected board.
Configuration Emulation FPGA Configuration Sequence
configuration emulation mode, HardCopy series device emulates behavior APEX Stratix FPGA during configuration phase. When this mode used, HardCopy device uses configuration emulation circuit receive configuration streams. When configuration data received, HardCopy series device transitions into initialization phase releases CONF_DONE pulled high. Pulling CONF_DONE high signals that HardCopy series device ready normal operation. optional open-drain INIT_DONE output used, normal operation delayed until this signal released HardCopy series device. HardCopy some HardCopy Stratix devices support configuration emulation mode.
During emulation sequence, user pins pulled high internal, weak pull-up resistors. Once configuration emulation initialization phase completed, pins released. Similar FPGA, nIO_pullup driven high, weak pull-up resistors disabled. value internal weak pull-up resistors pins found Operating Conditions table specific FPGA's device handbook.
Altera Corporation June 2007
20-9
HardCopy Series Handbook, Volume
Similar APEX FPGAs, HardCopy APEX devices have nIO_pullup function. Their internal weak pull-up resistors enabled during power initialization phase. Similar Stratix APEX FPGAs, HardCopy Stratix HardCopy APEX devices enter initialization phase immediately after successful configuration sequence. this time, registers reset, PLLs used initialized, pins used enabled device transitions into user mode.
application configuration emulation mode occurs when multiple programmable devices cascaded configuration chain only device replaced with HardCopy series device. this case, programming control signals clock signals used program FPGA must also used HardCopy series device. this done, HardCopy series device remains configuration emulation phase, emulation sequence never ends, HardCopy CONF_DONE remains de-asserted. proper configuration data stream data clock necessary HardCopy series device accurate emulation behavior. Figure 20-4 shows waveform configuration signals user signals using configuration emulation mode.
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Altera Corporation June 2007
HardCopy Power-Up Options
Figure 20-4. Timing Waveform Configuration Emulation Mode Notes (1), (2), (3),(4),(5)
(ALL) nCONFIG nSTATUS
CONF_DONE DCLK DATA
tDSU
User
tPOR
User Mode
INIT_DONE
tCF2ST1 tST2CK
Notes Figures 20-4:
(ALL) represents either power pins last power powered specified operating conditions. HardCopy power pins must powered within specifications described under Socketing sections. nCONFIG, nSTATUS, CONF_DONE must driven externally this waveform apply. User pins tri-stated driven before during power Socketing sections more details. nIO_pullup affect state user pins during initialization phase. INIT_DONE optional that enabled FPGA using Quartus software. HardCopy devices will carry over INIT_DONE functionality from prototyped FPGA design. nCEO also asserted about same time CONF_DONE released. However, must driven externally this waveform apply.
Altera Corporation June 2007
20-11
HardCopy Series Handbook, Volume
Configuration Emulation Timing Parameters
Tables 20-4 20-5 provide timing parameters configuration emulation mode.
Table 20-4. Timing Parameters Configuration Emulation Mode HardCopy Stratix Devices Parameter
tCF2ST1
Note Units
Description
PORSEL delay
Data setup time
Condition
nCONFIG high nSTATUS nSTATUS DCLK
User mode delay
Notes Table 20-4:
HC1S80, HC1S60, HC1S25 devices support emulation mode. These parameters similar Stratix FPGA specifications. Refer Configuration Handbook more information.
Table 20-5. Timing Parameters Configuration Emulation Mode HardCopy APEX Devices Parameter
tCF2ST1
Description
delay Data setup time
Typical
Units
nCONFIG high nSTATUS nSTATUS DCLK
User mode delay
Notes Table 20-5:
These parameters similar APEX FPGA specifications. Refer Configuration Handbook more information.
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Altera Corporation June 2007
HardCopy Power-Up Options
Benefits Configuration Emulation
Configuration emulation HardCopy series devices provides several advantages, including following:
Removes necessity changes software, especially FPGA configured using microprocessor. having change software benefits designer because microprocessor software changes demand significant system verification qualification efforts, which also impact development time. Allows HardCopy series devices co-exist with other FPGAs cascaded chain. None components need modified added, design changes board required. Additionally, configuration software changes need made. Supports configuration options available FPGA.
this example, single configuration device originally configured APEX FPGAs. Figure 20-5, HardCopy APEX device replaces APEX FPGA.
Altera Corporation June 2007
20-13
HardCopy Series Handbook, Volume
Figure 20-5. Emulation Configuration Sequence
HardCopy APEX Device
MSEL0 MSEL1
DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device DCLK DATA nINIT_CONF nCASC
nCEO
APEX Device
MSEL0 MSEL1
DCLK DATA0 nSTATUS CONF_DONE nCONFIG
nCEO
HardCopy series device configuration emulation mode requires same configuration control signals FPGA that replaced. configuration emulation mode, HardCopy series device responds exactly same FPGA. CONF_DONE signal HardCopy series device asserted exactly same time FPGA.
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Altera Corporation June 2007
Power-Up Options Summary When Designing With HardCopy Series Devices
Power-Up Options Summary When Designing With HardCopy Series Devices
When designing board prototyping FPGA with intent eventually replacing with HardCopy device, there three power-up options that should consider.
Instant Instant after Configuration emulation FPGA configuration sequence
must choose power-up option when submitting design database Altera migrating HardCopy series device. Once HardCopy series devices manufactured, power-up option cannot changed. HardCopy some HardCopy Stratix devices support configuration emulation mode.
HardCopy HardCopy Stratix devices retain functionality VCCSEL PORSEL pins from prototyping Stratix Stratix FPGAs. HardCopy HardCopy Stratix devices, PORSEL setting delays sequence similar prototyping FPGA.
more information PORSEL settings FPGA, refer Configuration Handbook. nCEO pins functional HardCopy series devices. must held proper operation nCEO pin. driven low, nCEO will asserted after initialization completed CONF_DONE released. HardCopy device, delays initialization driven low. Like Stratix device, nCEO HardCopy device powered VCCIO. used INIT_DONE FPGA prototype, HardCopy series device retains function. HardCopy series devices, INIT_DONE settings option masked-programmed into device. These settings must submitted Altera with final design prior migrating HardCopy series device. INIT_DONE option other option pins (for example, DEV_CLRn DEV_OE) available Fitter Device Options sections Quartus report file. HardCopy devices support user-supplied start-up clock option available Stratix devices. HardCopy device uses internal clock power-up circuitry. startup clock selection option configuring FPGA, which Quartus software under Device Options.
Altera Corporation June 2007
20-15
HardCopy Series Handbook, Volume
HardCopy devices support device-wide reset (DEV_CLRn) device-wide output enable (DEV_OE). HardCopy settings follow prototyping FPGA setting, which Quartus software under Device Options. correct operation HardCopy series device using instant option, pull nSTATUS, nCONFIG, CONF_DONE pins VCC. HardCopy series devices, these pins designed with weak, internal resistors pulled VCC. Many FPGA configuration schemes require pull-up resistors these pins, they already present board. some HardCopy series device applications, remove these external pullup resistors. Altera recommends leaving external pull-up resistors board following conditions exists:
There more than HardCopy series and/or FPGA board HardCopy design uses configuration emulation design uses MultiVoltI/O configurations
more information, refer Designing with 1.5-V Devices chapter Stratix Device Handbook. some FPGA configuration schemes, inputs DCLK DATA[7.0] float configuration device removed from board. HardCopy series devices, these pins designed with weak internal pull-up resistors, pins left unconnected board. When designing board with Stratix prototype device companion HardCopy device, most configuration pins required Stratix device required HardCopy device. maximize counts with HardCopy device utilization, Altera recommends minimizing power-up configuration pins that carry over from Stratix device into HardCopy device. More information found Migrating Stratix Device Resources HardCopy Devices chapter. HardCopy devices support MSEL settings used FPGA. required change these settings board when replacing prototyping FPGA with HardCopy series device. HardCopy devices MSEL pins these locations connected package. acceptable drive these pins required prototyping Stratix device.
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Altera Corporation June 2007
Power-Up Option Selection Examples
Pulsing nCONFIG signal FPGA re-initializes configuration sequence. nCONFIG signal HardCopy series device also restarts initialization sequence. HardCopy device JTAG locations match their corresponding FPGA prototypes. Like FPGAs, JTAG pins have internal weak pull pull downs four input pins TMS, TCK, TDI, TRST. There requirement change JTAG connections board when replacing prototyping FPGA with HardCopy series device. More information JTAG pins corresponding Boundary-Scan Support chapter each device.
Power-Up Option Selection Examples
HardCopy series device power-up option mask-programmed. Therefore, important that board design verified ensure that HardCopy series device power-up option chosen will work properly. This section provides recommendations selecting power-up option provides some examples. Table 20-6 shows comparison applicable FPGA HardCopy power options.
Table 20-6. FPGA Configuration Modes HardCopy Series Power-Up Schemes (Part Device Family Power Scheme Stratix
Instant Instant after Passive serial (PS) Active serial (AS) Fast passive parallel (FPP) Passive parallel synchronous (PPS) Passive parallel asynchronous (PPA) Joint Test Action Group (JTAG) Remote local update
Stratix
APEX HardCopy APEX 20KE APEX 20KC
HardCopy Stratix
HardCopy APEX
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
Table 20-6. FPGA Configuration Modes HardCopy Series Power-Up Schemes (Part Device Family Power Scheme Stratix
Remote local update Remote local update Notes Table 20-6:
HardCopy devices support emulation mode. HC1S80, HC1S60, HC1S25 devices support emulation mode. remote/local update feature Stratix devices supported HardCopy Stratix devices.
Stratix
APEX HardCopy APEX 20KE APEX 20KC
HardCopy Stratix
HardCopy APEX
Power-up option recommendations depend following board configurations:
Single HardCopy series device replacing single FPGA board more HardCopy series devices replacing more FPGA multiple-device configuration chain HardCopy series devices replacing FPGAs multiple-device configuration chain
multiple-device configuration chain, more than FPGA board obtains configuration data from same source.
Replacing FPGA With HardCopy Series Device
Altera recommends using instant instant after mode when replacing FPGA with HardCopy series device regardless board configuration scheme. Table 20-7 gives summary HardCopy series device power-up options when single HardCopy series device replaces single FPGA board.
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Altera Corporation June 2007
Power-Up Option Selection Examples
Table 20-7 does include HardCopy options because HardCopy devices only support instant instant after modes.
Table 20-7. Summary Power-Up Options HardCopy Series Device Replacing FPGA Configuration Scheme
with configuration device(s) download cable with enhanced configuration devices PPA, PPS, FPP, with microprocessor
HardCopy APEX Options
Instant Instant after available
HardCopy Stratix Options
Comments
configuration device(s) must removed from board. configuration device(s) must removed from board. microprocessor code changed, design should instant instant after mode. However, microprocessor still needs drive logic value HardCopy nCONFIG Configuration emulation mode used delays initialization board device.
Instant Instant after Instant Instant after Emulation
Emulation
JTAG configuration
Instant after Emulation
Instant after Emulation
Notes Table 20-7:
Download cable used either MasterBlasterTM, Blaster, ByteBlasterII, ByteBlasterMVhardware. parallel programming modes, DATA[7.1] pins have weak pull resistors HardCopy series device, which optionally enabled disabled through metallization. DCLK DATA[0] pins have internal weak pull-up resistors. HC1S80, HC1S60, HC1S25 devices support emulation mode.
Replacing More FPGAs With More HardCopy Series Devices Multiple-Device Configuration Chain
Altera recommends using instant instant after mode when replacing FPGA with HardCopy series device, regardless configuration scheme. Table 20-8 gives summary HardCopy series device power-up options when single HardCopy series device replaces single FPGA multiple-device configuration chain.
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
When using instant instant after mode, HardCopy series device could user-mode ready before other configured devices board. important verify that signals that communicate from HardCopy series device stable will affect HardCopy series device other device operation while devices still power configuration stage. example, HardCopy series design used reference clock that available until after other devices fully powered HardCopy series device will operate properly unless PLLs reset. Table 20-8 does include HardCopy options because HardCopy devices only support instant instant after modes.
Table 20-8. Power-Up Options More HardCopy Series Devices Replacing FPGAs Multiple-Device Configuration Chain (Part Configuration Scheme
with configuration device(s) download cable with enhanced configuration device
HardCopy APEX Options
Emulation Instant Instant after
HardCopy Stratix Options
Emulation Instant Instant after
Comments
Instant instant after modes used following APEX Stratix device tied logic board configuration data modified remove HardCopy series device configuration data. configuration sequence then skips HardCopy series device. microprocessor code changed, design should instant instant after mode. However, microprocessor still needs drive logic value HardCopy series device nCONFIG pin.
PPA, PPS, FPP, with microprocessor
Emulation
Emulation
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Altera Corporation June 2007
FPGA HardCopy Configuration Migration Examples
Table 20-8. Power-Up Options More HardCopy Series Devices Replacing FPGAs Multiple-Device Configuration Chain (Part Configuration Scheme
JTAG configuration
HardCopy APEX Options
Emulation
HardCopy Stratix Options
Emulation
Comments
HardCopy series device BYPASS mode JTAG programming data modified remove HardCopy configuration information, instant instant after modes used.
Notes Table 20-8:
Download cable used either MasterBlaster, Blaster, ByteBlaster ByteBlasterMV hardware. HC1S80, HC1S60, HC1S25 devices support emulation mode. HardCopy series device last device configuration chain, Altera recommends using instant modes. parallel programming modes, DATA[7.1] pins have weak pull resistors HardCopy series device, which optionally enabled disabled through metallization. DCLK DATA[0] pins also have weak pull-up resistors.
Replacing FPGAs with HardCopy Series Devices Multiple-Device Configuration Chain
When Stratix Stratix, APEX FPGAs replaced HardCopy HardCopy Stratix, HardCopy APEX devices, respectively, Altera recommends using instant instant after mode, regardless configuration scheme. Once HardCopy series devices replace FPGAs, configuration devices used configure FPGAs should removed from board. Microprocessor code, applicable, should changed account HardCopy series device power-up scheme. JTAG chain perform other JTAG operations except configuration.
FPGA HardCopy Configuration Migration Examples
following examples HardCopy series devices replace FPGAs that different FPGA configuration schemes.
HardCopy Series Device Replacing Stand-Alone FPGA
this example, single HardCopy series device uses instant power-up option, shown Figure 20-7. configuration device, redundant, removed, further board changes necessary. pull-up resistors nCONFIG, nSTATUS, CONF_DONE pins removed, should left board configuration emulation multiple-voltage standards used. could also instant after power-up mode this example.
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
Figures 20-6 20-7 show HardCopy series device replaces FPGA previously configured with Altera configuration device. Figure 20-6. Configuration Stand-Alone FPGA
Note
FPGA
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL nCEO N.C.
Configuration Device
DCLK DATA nCASC nINIT_CONF
N.C.
Figure 20-7. HardCopy Series Device Replacing Stand-Alone FPGA
Note
HardCopy Series Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL nCEO N.C.
Notes Figures 20-6 20-7:
details configuration interface connections, refer Configuration Handbook. handbook includes information MSEL pins mode. nINIT_CONF (available enhanced configuration EPC2 devices) internal pull-up resistor that always active. Therefore, nINIT_CONF/nCONFIG line does require external pull-up resistor. nINIT_CONF does need connected functionality used. nINIT_CONF used available, resistor pull nCONFIG VCC. Enhanced configuration EPC2 devices have internal programmable pull-up resistors pins. Refer Configuration Handbook more details this application FPGAs. HardCopy series devices have internal weak pull-up resistors nSTATUS, nCONFIG, CONF_DONE pins.
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Altera Corporation June 2007
FPGA HardCopy Configuration Migration Examples
HardCopy Series Device Replacing FPGA Cascaded Configuration Chain
Figure 20-8 shows design where configuration data Stratix devices stored single configuration device, FPGAs connected multiple-device configuration chain. second device chain replaced with HardCopy Stratix device, shown Figure 20-9.
more information Stratix FPGA configuration schemes, refer Configuration Handbook.
Figure 20-8. Configuration Multiple FPGAs Cascade Chain
Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device DCLK DATA nCASC nINIT_CONF
N.C. nCEO
nCEO
nCEO
Notes Figure 20-8:
pull-up resistors connected same supply voltage configuration device. enhanced configuration devices EPC2 devices have internal programmable pull-up resistors pins. Refer Configuration Handbook more details. nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices. Refer Configuration Handbook more details.
Configuration with HardCopy Series Device Cascade Chain
Figure 20-9 shows same cascade chain Figure 20-8, second FPGA chain been replaced with HardCopy Stratix device.
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
Figure 20-9. Replacing FPGA with HardCopy Equivalent Cascade Chain
Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
HardCopy Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device DCLK DATA nCASC nINIT_CONF
N.C. nCEO
nCEO
nCEO
Notes Figure 20-9:
pull-up resistors connected same supply voltage configuration device. enhanced configuration devices EPC2 devices have internal programmable pull-up resistors pins. Refer Configuration Handbook more details. nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices. Refer Configuration Handbook more information. HC1S80, HC1S60, HC1S25 devices support emulation mode cannot used this method.
this example, HardCopy Stratix device only configured using configuration emulation mode. configuration device cannot removed, still required other Stratix devices chain. While HardCopy Stratix device does need data stored configuration device, data configuration device modified reflect this. emulation mode ensures that HardCopy series device nCEO asserted correctly after emulation configuration sequence. nCEO enables next device chain receive correct configuration data from configuration device. Additionally, with configuration emulation mode, need make changes board.
Configuration With HardCopy Series Device Removed From Cascade Chain
alternative method configure FPGAs board with both HardCopy series devices FPGAs remove HardCopy series device from cascade chain. Figure 20-10 shows devices connected with HardCopy series device removed from chain. data configuration device should modified exclude HardCopy series device configuration data. HardCopy series device three power-up options.
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Altera Corporation June 2007
FPGA HardCopy Configuration Migration Examples
Figure 20-10. Configuration With HardCopy Series Device Removed From Cascade Chain
Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
HardCopy Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device DCLK DATA nCASC nINIT_CONF
N.C. nCEO
N.C. nCEO
nCEO
Notes Figure 20-10:
pull-up resistors connected same supply voltage configuration device. enhanced configuration devices EPC2 devices have internal programmable pull-up resistors pins. Refer Configuration Handbook more details. nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices. Refer Configuration Handbook more information. HC1S80, HC1S60, HC1S25 devices support emulation mode cannot used this method.
Eliminating HardCopy series device from configuration chain requires following changes board:
HardCopy series device must tied GND. FPGA that driven HardCopy series nCEO must driven nCEO FPGA that precedes HardCopy series device chain.
HardCopy Series Device Replacing FPGA Configured Using Microprocessor
HardCopy series device replace FPGAs that configured using microprocessor, shown Figures 20-12 20-13. While instant mode most efficient, designers also instant after configuration emulation mode. Figure 20-11 shows application where APEX FPGAs configured using microprocessor configuration scheme.
more information configuration scheme, refer Configuration Handbook.
Altera Corporation June 2007
20-25
HardCopy Series Handbook, Volume
Figure 20-11. Configuring FPGAs Using Microprocessor
APEX 20KE APEX 20KC Device Memory ADDR DATA[7.0] MSEL CONF_DONE nSTATUS Microprocessor nCEO MSEL0
APEX 20KE APEX 20KC Device MSEL0 MSEL CONF_DONE nSTATUS nCEO N.C.
DATA[7.0] DCLK nCONFIG
DATA[7.0] DCLK nCONFIG
Note Figure 20-11:
Connect pull-up resistors supply that provides acceptable input signal devices chain.
When HardCopy series device replaces last FPGA configuration sequence shown Figure 20-12), instant instant after mode. However, must modify microprocessor code eliminate configuration data last FPGA configuration chain.
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FPGA HardCopy Configuration Migration Examples
Figures 20-12 20-13 show HardCopy APEX device replacing APEX FPGAs either first last configuration chain. Figure 20-12. Replacement Last FPGA Chain With HardCopy Series Device
APEX 20KE APEX 20KC Device Memory ADDR DATA[7.0] MSEL CONF_DONE nSTATUS Microprocessor nCEO N.C. MSELO
HardCopy APEX Device MSELO
MSEL CONF_DONE nSTATUS nCEO N.C.
DATA[7.0] DCLK nCONFIG
DATA[7.0] DCLK nCONFIG
Figure 20-13. Replacement First FPGA Chain With HardCopy Series Device
HardCopy APEX Device Memory ADDR DATA[7.0] MSEL CONF_DONE nSTATUS Microprocessor nCEO MSELO
APEX 20KE APEX 20KC Device MSELO
MSEL CONF_DONE nSTATUS nCEO N.C.
DATA[7.0] DCLK nCONFIG
DATA[7.0] DCLK nCONFIG
Note Figures 20-12 20-13:
Connect pull-up resistors supply that provides acceptable input signal devices chain.
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HardCopy Series Handbook, Volume
HardCopy series device first device chain opposed second shown Figure 20-13), must take following into consideration, depending HardCopy power-up option used.
Instant mode-The microprocessor program code must modified remove configuration code relevant HardCopy series device. microprocessor must delay sending first configuration data word FPGA until nCEO HardCopy series device asserted. microprocessor then loads first configuration data word into FPGA. Instant after mode-The boot-up time microprocessor must greater than HardCopy series device asserts nCEO after 50-ms delay which, turn, enables following FPGA. microprocessor send first configuration data word FPGA after FPGA enabled. Emulation mode-This option should used microprocessor code pertaining configuration above devices cannot modified.
HardCopy Stratix Device Replacing FPGA Configured JTAG Chain
this example, circuit connectivity maintained there changes made board. HardCopy series device either following power-up options when applicable.
Instant mode-Use instant power mode microprocessor code modified that treats HardCopy series device non-configurable device. microprocessor achieve this issuing BYPASS instruction HardCopy series device. With HardCopy series device BYPASS mode, configuration data passes through downstream FPGAs. Configuration emulation mode-Use configuration emulation power mode microprocessor code pertaining configuration above devices cannot modified. HC1S80, HC1S60, HC1S25 devices support this mode.
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FPGA HardCopy Configuration Migration Examples
Figure 20-14 shows example where there multiple Stratix FPGAs. These devices connected using JTAG pins each device, programmed using JTAG port. on-board microprocessor generates configuration data. Figure 20-14. Configuring FPGAs JTAG Chain Using Microprocessor
Note
Stratix Device
Stratix Device nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
Stratix Device nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
Memory ADDR DATA
Microprocessor
nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
Notes Figure 20-14:
Stratix Stratix, APEX devices placed within same JTAG chain device programming configuration. Connect nCONFIG, MSEL0, MSEL1, MSEL2 pins support non-JTAG configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0, MSEL1, MSEL2 ground. Pull DATA0 DCLK either high low. must connected driven successful JTAG configuration.
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Figure 20-15 shows example where first Stratix device JTAG chain replaced HardCopy Stratix device. Figure 20-15. Replacement First FPGA JTAG Chain With HardCopy Series Device
Note
Stratix Device nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
HardCopy Stratix Device Memory ADDR DATA nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
Stratix Device nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
Microprocessor
Notes Figure 20-15:
Stratix Stratix, APEX devices placed within same JTAG chain device programming configuration. Connect nCONFIG, MSEL0, MSEL1, MSEL2 pins support non-JTAG configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0, MSEL1, MSEL2 ground. Pull DATA0 DCLK either high low. must connected driven successful JTAG configuration.
HardCopy Device Replacing Stratix Device Configured With Microprocessor
When replacing Stratix FPGA with HardCopy device, HardCopy device only instant instant after modes. This example does require changes board. However, microprocessor code must modified treat HardCopy device non-configurable device. Figure 20-16 shows example with Stratix devices configured using microprocessor MAX® device configuration scheme.
more information Stratix configuration, refer Configuration Handbook.
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FPGA HardCopy Configuration Migration Examples
Figure 20-16. Multiple-Device Configuration Using Microprocessor Device
Memory
ADDR DATA[7.0]
Stratix Device
MSEL[3.0] CONF_DONE nSTATUS nCEO
Stratix Device
MSEL[3.0] CONF_DONE nSTATUS nCEO N.C.
External Host (MAX Device Microprocessor)
DATA[7.0] nCONFIG DCLK DATA[7.0] nCONFIG DCLK
Note Figure 20-16:
Connect pull-up resistor supply that provides acceptable input signal devices chain. voltage meets standard's specification device external host.
Figure 20-17 shows first Stratix device replaced HardCopy device. this case, microprocessor code must modified send configuration data only second device (the Stratix device) configuration chain. microprocessor only send this data after asserted first device (the HardCopy device).
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Figure 20-17. Replacement First FPGA Configuration Chain With HardCopy Series Device
Memory
ADDR DATA[7.0]
HardCopy Device
MSEL[3.0] CONF_DONE nSTATUS nCEO
Stratix Device
MSEL[3.0] CONF_DONE nSTATUS nCEO N.C.
External Host (MAX Device Microprocessor)
DATA[7.0] nCONFIG DCLK DATA[7.0] nCONFIG DCLK
Notes Figure 20-17:
Connect pull-up resistor supply that provides acceptable input signal devices chain. voltage meets standard's specification device external host. DATA[7.0] pins used HardCopy device, they preserve assignment direction from Stratix device, allowing drop-in replacement.
Conclusion
HardCopy series devices emulate configuration sequence while maintaining seamless migration benefits HardCopy methodology. Instant mode, which simplest available options, provides ASIC-like operation power This mode used most cases without regard original FPGA configuration mode without hardware and/or software changes. some cases, however, software revision and/or board re-design necessary guarantee that correct configuration data sent remaining programmable devices. Such modifications easily made early stages board design process determined that more FPGAs will replaced with equivalent HardCopy series device. Board-design techniques like jumper connectors resistors enable such modifications without necessity re-design board. instant after mode suitable cases where delay necessary accommodate configuration device become operational, allow more pre-determined events completed before HardCopy series device asserts CONF_DONE pin.
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Document Revision History
Finally, emulation mode option choose software hardware modifications possible. such cases, HardCopy series device co-exists with other FPGAs.
Document Revision History
Table 20-9 shows revision history this chapter.
Table 20-9. Document Revision History (Part Date Document Version
June 2007, v2.4 December 2006 v2.3 2006, v2.2 March 2006, v2.1 Minor text edits. Added revision history.
Changes Made
Summary Changes
Updated Tables 20-1, 20-3, 2-5. Formerly chapter Re-organized HardCopy Power-Up Options section eliminate redundancy. Updated Figures 20-1, 20-2, 20-3. UpdatedTables 20-1 20-5, Table 20-7. Added Power Options Summary When Designing With HardCopy Series Devices section.
October 2005, v2.0
Moved from Chapter Chapter Hardcopy Series Device Handbook
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HardCopy Series Handbook, Volume
Table 20-9. Document Revision History (Part Date Document Version
January 2005, v2.0
Changes Made
Chapter title changed Power-Up Modes Configuration Emulation HardCopy Series Devices. Added HardCopy device information. Updated external resistor requirements depending chip configuration. Added reference some control option pins that carry over functions from FPGA design affect HardCopy power Updated information which HardCopy devices support emulation mode. Added Table 15-9 which lists what power options supported FPGAs their HardCopy counterpart. Added "Replacing FPGA With HardCopy Series Device", "Replacing More FPGAs With More HardCopy Series Devices MultipleDevice Configuration Chain", "Replacing FPGAs with HardCopy Series Devices Multiple-Device Configuration Chain" sections, including Tables 15-10 15-11, highlighting power recommendations each HardCopy series family.
Summary Changes
June 2003, v1.0
Initial release Chapter Power-Up Modes Configuration Emulation HardCopy Series Devices.
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H51012-2.4 Configuring FPGA process loading design data into devi

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