HardCopy® APEXdevices extend flexibility high-density FPGAs cost-effec

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HardCopy® APEXdevices extend flexibility high-density FPGAs cost-effec

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H51007-2.2
HardCopy® APEXdevices extend flexibility high-density FPGAs cost-effective, high-volume production solution. migration process from Altera® FPGA HardCopy APEX device offers seamless migration high-density system-on-a-programmable-chip (SOPC) design low-cost alternative device with minimal risk. Using HardCopy APEX devices, Altera's SOPC solutions leveraged from prototype production, while reducing costs speeding time-to-market. significant benefit HardCopy devices that customers need involved device migration process. Unlike application-specific integrated circuit (ASIC) development, HardCopy design flow does require generation test benches, test vectors, timing functional simulation. HardCopy migration process only requires Quartus® software-generated output files from fully functional APEX 20KE APEX 20KC device. Altera performs migration delivers functional prototypes seven weeks. risk-free alternative ASICs, HardCopy APEX devices customizable, full-featured devices created Altera's proprietary design migration methodology. They based Altera's industry-leading high-density device architecture area-efficient sea-of-logic-elements (SOLE) core. HardCopy APEX devices retain same features APEX 20KE APEX 20KC devices, which combine strength LUT-based product-term-based devices conjunction with same embedded memory structures. routing resources that were programmable APEX device family replaced custom interconnect, resulting considerable size reduction subsequent cost saving. SRAM configuration cells original FPGA replaced HardCopy APEX devices metal elements, which define function each logic element (LE), embedded memory, cell device. These resources connected each other using same metallization layers. Once HardCopy APEX device been manufactured, functionality device fixed programming possible. Altera performs migration original FPGA design equivalent HardCopy APEX device using proprietary design migration flow.
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
migration FPGA HardCopy APEX device begins with user design that been implemented APEX 20KE APEX 20KC device. Table 16-1 shows device equivalence HardCopy APEX 20KE APEX 20KC devices.
Table 16-1. HardCopy APEX 20KE APEX Device Equivalence HardCopy APEX Device
HC20K1500 HC20K1000 HC20K600 HC20K400
APEX 20KE Device
EP20K1500E EP20K1000E EP20K600E EP20K400E
APEX 20KC Device
EP20K1500C EP20K1000C EP20K600C EP20K400C
ensure HardCopy device performance functionality, APEX design must completely debugged before committing design HardCopy device migration.
HardCopy APEX device implementation begins with extracting Quartus software-generated SRAM Object File (.sof) converting connectivity information into structural Verilog netlist. This netlist then placed routed similar fashion gate array. There dedicated routing channels. router exploit available metal layers four) route over cells other functional blocks. Altera's proprietary architecture design methodology will guarantee virtually 100% routing APEX 20KE APEX 20KC design compiled fitted successfully using Quartus software. Place route timing-driven will comply with timing constraints original FPGA design specified Quartus software. Figure 16-1 shows diagram HardCopy APEX device architecture.
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Altera Corporation June 2007
Figure 16-1. HardCopy APEX Device Architecture
Elements
Strip auxiliary gates (SOAG)
PLLs
strip auxiliary gates (SOAG) Altera proprietary feature designed into HardCopy APEX device used during HardCopy device implementation process. SOAG structures configured into several different types functions through metallization. example, high fanout signals require adequate buffering, buffers built SOAG cells this purpose. HardCopy APEX devices include same advanced features APEX 20KE APEX 20KC devices, such enhanced standard support, content-addressable memory (CAM), additional global clocks, enhanced ClockLock circuitry. Table 16-2 lists features included HardCopy APEX devices.
Table 16-2. HardCopy APEX Device Features (Part Feature
MultiCore system integration Hot-socketing support 32-/64-bit, 33-MHz 32-/64-bit, 66-MHz MultiVolt operation Full support Full support Full compliance Full compliance 1.8-V, 2.5-V, 3.3-V VCCIO VCCIO selected bank bank 5.0-V tolerant with external resistor
HardCopy Devices
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
Table 16-2. HardCopy APEX Device Features (Part Feature
ClockLock support
HardCopy Devices
Clock delay reduction clock multiplication Drive ClockLock output off-chip External clock feedback ClockShift circuitry LVDS support four PLLs ClockShift, clock phase adjustment
Dedicated clock input pins Eight standard support 1.8-V, 2.5-V, 3.3-V, 5.0-V 3.3-V PCI-X 3.3-V GTL+ LVCMOS LVTTL True-LVDS LVPECL data pins LVDS LVPECL clock pins HSTL class PCI-X SSTL-2 class SSTL-3 class Dual-port FIFO
Memory support
HardCopy APEX devices tested using automatic test pattern generation (ATPG) vectors prior shipment. fully synchronous designs near 100%, fault coverage achieved through built-in full-scan architecture. ATPG vectors allow designer focus simulation design verification. Because configuration HardCopy APEX devices built-in during manufacture, they cannot configured in-system. However, APEX 20KE APEC 20KC device configuration sequence must emulated, HardCopy APEX device this capability.
device features APEX 20KE APEX 20KC devices available HardCopy APEX devices. detailed description these device features, refer APEX Programmable Logic Device Family Data Sheet APEX 20KC Programmable Logic Device Family Data Sheet.
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Altera Corporation June 2007
Differences Between HardCopy APEX APEX FPGAs
Differences Between HardCopy APEX APEX FPGAs
Several differences must considered before design ready implementation HardCopy technology:
HardCopy APEX devices only customizable time they manufactured. Make sure that original APEX 20KE APEX 20KC device undergone thorough testing end-system before deciding proceed with migration HardCopy APEX device, because changes made HardCopy APEX device after been manufactured. ESBs that configured will power-up un-initialized HardCopy APEX device. FPGA possible configure, "pre-load," memory part configuration sequence, then overwrite when device normal functional mode. This pre-loaded memory feature FPGA available HardCopy devices. design contains with assumed data values power-up, then HardCopy APEX device will operate expected. design uses this feature, should re-compiled without memory pre-load. ESBs configured fully supported. JTAG boundary scan order HardCopy APEX device different compared APEX device. HardCopy BSDL file that describes re-ordered boundary scan chain should used.
BSDL files HardCopy APEX devices different from corresponding APEX 20KE APEX 20KC devices. Download correct HardCopy BSDL file from Altera's website www.altera.com.
advanced 0.18-m aluminum metal process used support both APEX 20KE APEX 20KC devices. performance improvement achieved size reduction metal interconnect optimization more than offsets need copper this case. Altera guarantees that target HardCopy APEX device will provide same better performance corresponding APEX 20KE APEX 20KC device.
Power-up Mode Configuration Emulation
Unlike their FPGA counterparts, HardCopy APEX devices need configured. However, facilitate seamless migration, configuration emulated these devices. There three modes which
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
HardCopy APEX device prepared operation after power instant instant after configuration emulation. Each mode described below.
instant mode, HardCopy APEX device available shortly after device receives power. on-chip power-on-reset (POR) circuit will reset registers. CONF_DONE output will tri-stated once power-on reset elapsed. configuration device configuration input signals necessary. instant after mode, HardCopy APEX device performs similar fashion Instant mode, except that there additional delay (nominal), during which time device held reset stage. CONF_DONE output pulled during this time then tri-stated after have elapsed. configuration devices configuration input signals necessary this option. configuration emulation mode, HardCopy APEX device undergoes emulation full configuration sequence configured external processor device. this mode, CONF_DONE signal tri-stated after correct number clock cycles. This mode useful where there some dependency configuration sequence (for example, multi-device configuration processor initialization). this mode, device expects configuration control data input signals.
Speed Grades
Because HardCopy APEX devices customized, speed grading performed. HardCopy APEX devices will meet timing requirements original FPGA fastest speed grade. Generally, HardCopy APEX devices will have higher fMAX than corresponding FPGA, speed increase will vary design-by-design basis. HardCopy migration process requires several Quartus software-generated files. These output files listed explained below.
Quartus IIGenerated Output Files
SRAM Object File (.sof) contains necessary information needed configure FPGA Compiler Report File (.csf.rpt) parsed extract useful information about design Verilog atom-based netlist file (.vo) used check HardCopy netlist information file (.pin) contains user signal names configuration information
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Altera Corporation June 2007
Document Revision History
Delay Information File (.sdo) used check original FPGA timing completed HardCopy timing requirements file describes necessary timing information design. template this text file available download from Altera website www.altera.com.
migration process consists several steps. First, netlist constructed from SOF. Then, netlist checked ensure that built-in scan test structures will operate correctly. netlist then into place-and-route engine, design interconnect generated. Static timing analysis ensures that timing constraints met, static functional verification techniques employed ensure correct device migration. After successfully completing these stages, physical verification device takes place, metal mask layers taped fabricate HardCopy APEX devices.
Document Revision History
Table 16-3 shows revision history this chapter.
Table 16-3. Document Revision History Date Document Version
June 2007, v2.2 December 2006 v2.1 March 2006 January 2005 v2.0 June 2003 v1.0 Minor text edits. Updated revision history. Formerly chapter content change. Update device names other minor textual changes Initial release Chapter Description, Architecture Features, HardCopy Device Handbook
Changes Made
Summary Changes
Altera Corporation June 2007
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HardCopy Series Handbook, Volume
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Altera Corporation June 2007

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