H51006-2.2 HardCopy® APEXdevices enable high-density APEX 20KE de

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Introduction HardCopy APEX Devices
H51006-2.2
HardCopy® APEXdevices enable high-density APEX 20KE device technology used high-volume applications where significant cost reduction desired. HardCopy APEX devices physically functionally compatible with APEX 20KC APEX 20KE devices. They combine time-to-market advantage, performance, flexibility APEX 20KE devices with ability move high-volume, low-cost devices production. migration process from APEX 20KE device HardCopy APEX device fully automated, with designer involvement limited providing Quartus® software-generated output files. HardCopy APEX devices manufactured using 0.18-m CMOS six-layer-metal process technology:
Features.
Preserves functionality configured APEX 20KC APEX 20KE device Pin-compatible with APEX 20KC APEX 20KE devices Meets exceeds timing configured APEX 20KE APEX 20KC devices Optional emulation original programmable logic device (PLD) programming sequence High-performance, low-power device MultiCore architecture integrating embedded memory look-up table (LUT) logic used register-intensive functions Embedded system blocks (ESBs) used implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, content-addressable memory (CAM) Customization performed through metallization layers
Altera Corporation June 2007
15-1
HardCopy Series Handbook, Volume
High-density architecture:
400,000 million typical gates (Table 15-1) 51,840 logic elements (LEs) 442,368 bits that used without reducing available logic
Table 15-1. HardCopy APEX Device Features Feature
Maximum system gates Typical gates ESBs Maximum bits Phase-locked loops (PLLs) Maximum macrocells Maximum user pins Note Table 15-1:
Note HC20K600
1,537,000 600,000 24,320 311,296 2,432
HC20K400
1,052,000 400,000 16,640 212,992 1,664
HC20K1000
1,772,000 1,000,000 38,400 327,680 2,560
HC20K1500
2,392,000 1,500,000 51,840 442,368 3,456
embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes 57,000 additional gates.
.and More Features
Low-power operation:
1.8-V supply voltage (Table 15-2) MultiVolt support 1.8-, 2.5-, 3.3-V interfaces ESBs offering power-saving mode
Flexible clock management circuitry with four phase-locked loops (PLLs):
Built-in low-skew clock tree eight global clock signals ClockLock feature reducing clock delay skew ClockBoost feature providing clock multiplication division ClockShift feature providing clock phase delay shifting
Powerful features:
Compliant with peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation bits
15-2
Altera Corporation June 2007
.and More Features
Support high-speed external memories, including double-data rate (DDR), synchronous dynamic (SDRAM), zero-bus-turnaround (ZBT) static (SRAM) input output LVDS channels Fast times complex logic MultiVolt support 1.8-V, 2.5-V, 3.3-V interfaces Individual tri-state output enable control each Output slew-rate control reduce switching noise Support advanced standards, including LVDS, LVPECL, PCI-X, AGP, CTT, SSTL-3 SSTL-2, GTL+, HSTL Class Supports hot-socketing operation
Table 15-2. HardCopy APEX Device Supply Voltages Feature
Internal supply voltage (VCCINT) MultiVolt interface voltage levels (VCCIO) Note Table 15-2:
HardCopy APEX devices 5.0-V tolerant using external resistor.
Voltage
HardCopy APEX device implementation features:
Customized interconnect each design HardCopy APEX devices preserve APEX device MegaLAB structure, LEs, ESBs, element (IOE), PLLs, LVDS circuitry four metal layers customizable customer designs Completely automated proprietary design migration flow Testability analysis Automatic test pattern generation (ATPG) Automatic place route Static timing analysis Static functional verification Physical verification
Altera Corporation June 2007
15-3
HardCopy Series Handbook, Volume
Tables 15-3 through 15-6 show HardCopy APEX device ball-grid array (BGA) FineLine package options, counts, sizes.
Table 15-3. HardCopy APEX Device Package Options Count Note Device
HC20K400 HC20K600 HC20K1000 HC20K1500
652-Pin
Table 15-4. HardCopy APEX Device FineLine Package Options Count Note Device
HC20K400 HC20K600 HC20K1000 HC20K1500 Note Tables 15-3 15-4:
counts include dedicated input clock pins.
672-Pin
1,020-Pin
Table 15-5. HardCopy APEX Device Package Sizes Feature
Pitch (mm) Area (mm2) Length width
652-Pin
1.27 2,025 45.0 45.0
Table 15-6. HardCopy APEX Device FineLine Package Sizes Feature
Pitch (mm) Area (mm2) Length width
672-Pin
1.00
1,020-Pin
1.00 1,089
15-4
Altera Corporation June 2007
Document Revision History
Document Revision History
Table 15-7 shows revision history this chapter.
Table 15-7. Document Revision History Date Document Version
June 2007, v2.2 December 2006 v2.1 March 2006 January 2005 v2.0 June 2003 v1.0 Minor text edits. Updated revision history. Formerly chapter content change. Update device names other minor textual changes Initial release Chapter Introduction HardCopy APEX Devices, HardCopy Device Handbook
Changes Made
Summary Changes
Altera Corporation June 2007
15-5
HardCopy Series Handbook, Volume
15-6
Altera Corporation June 2007

H51006-2.2 HardCopy® APEXdevices enable high-density APEX 20KE de

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