April 2005, MegaCore Version 1.0.0 This document addresses known
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SerialLite MegaCore Function
April 2005, MegaCore Version 1.0.0
This document addresses known errata documentation changes version 1.0.0 SerialLite MegaCore® function. Errata design functional defects errors. Errata cause SerialLite MegaCore function deviate from published specifications. Documentation changes include typos, errors, unclear descriptions omissions from current published specifications product documents. These documentation changes clarifications will incorporated into upcoming release SerialLite MegaCore function.
SerialLite MegaCore Function v1.0.0 Issues
Altera identified following issues that affect SerialLite MegaCore function v1.0.0: "The Link Does Come Over Long Cable Distances" page "Flow Control Issue Regular User Data Port" page "The Quartus Software Does Merge Transmit Phase-Lock Loops (PLLs) Multiple Function Instantiations" page Parameter Invalid Value Toolbench" page "Slow Link Synchronization with VHDL Models" page "The NumPriorityPackets Parameter Missing Demonstration Testbench Parameter Text File" page "User-Defined Payload Mode Does Support Packets Greater than Bytes" page "The Demonstration Testbench Parameter List User Guide Does Match Text File" page "The Demonstration Testbench Fails When Generated Quartus Software" page
"The Demonstration Testbench Does Achieve Link Synchronization" page
Altera Corporation ES-031805-1.0
Preliminary
SerialLite MegaCore Function
"The Demonstration Testbench Fails Unbalanced Configurations" page "The ModelSim 6.0c Software Produces Compilation Error When Loading Demonstration Testbench" page "The ModelSim 6.0c Software Produces Fatal Error With Condition Coverage altera_mf.v File" page "The Serial Loopback Documented" page "Limitations Signal Priority Port" page
Link Does Come Over Long Cable Distances
updated LSM_LINKSM file, including timeout logic, available. size counter determined idle_count_size parameter. LSM_LINKSM file, idle_count_size parameter that small value, change recompile your variation.
Affected Configurations
This issue affects variations which wire delay causes link time out.
Design Impact
long cable distances, miles example, link never comes default idle_count_size
Workaround
Submit mySupport request. Altera will e-mail updated LSM_LINKSM file with parameterized IDLE counter. this file replace file sub-directory SerialLite MegaCore function installation directory. size counter determined idle_count_size parameter. default, parameter create 8-bit IDLE counter. that counter small still, increase value parameter recompile.
Solution Status
This issue will fixed adding parameter next release SerialLite MegaCore function.
Preliminary
Altera Corporation
SerialLite MegaCore Function v1.0.0 Issues
Flow Control Issue Regular User Data Port
Flow control link management packets (LMPs) transmitted after regular user data FIFO buffer exceeds fill level threshold, causing FIFO buffer overflow over time. problem incorrect parameterization regular user data port SCFIFO megafunction, used MegaCore function. Originally, FIFO buffers were only meant support depths elements.
Affected Configurations
This issue affects variations that have flow control regular user data port parameters enabled, which receiver regular user data port FIFO buffers have depths greater than elements.
Design Impact
FIFO buffer thresholds used generate flow control compared that upper bits mismatched with SCFIFO megafunction, causing flow control generation signal stated, thus flow control never happen.
Workaround
Reduce size regular data port FIFO buffers 128-elements deep. Submit mySupport request. Altera will e-mail files that include fixes this issue. directory where installed SerialLite MegaCore function includes sub-directory called lib. files overwrite files that sub-directory. Regenerate variation.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
Altera Corporation
Preliminary
SerialLite MegaCore Function
Quartus Software Does Merge Transmit Phase-Lock Loops (PLLs) Multiple Function Instantiations
Quartus® software reports no-fit designs where more than SerialLite MegaCore function instantiated each quad bank serial inputs outputs (I/Os). Quartus software consumes ALTGXB transmitter instantiation, does merge transmit PLLs even same reference clock connected each instantiation.
Affected Configurations
This issue affects single-lane dual-lane variations that include more instantiations than device ALTGXB transmitter PLLs.
Design Impact
Only single instantiation used quad bank serial I/Os.
Workaround
SerialLite wrapper modified instantiate multiple SerialLite protocol core engines connected single ALTGXB transmitter PLL. ALTGXB transmitter configured match desired number lanes. Each protocol core instantiation then connects associated bits ALTGXB transmitter PLL. Submit mySupport request help with this workaround.
Solution Status
This issue will fixed next release SerialLite MegaCore function, requiring Quartus software version 5.1.
Parameter Invalid Value Toolbench
Toolbench sets praif_almost_full parameter negative value, instead positive value, when large number channels selected.
Affected Configurations
This issue affects variations that have Number Lanes parameter value greater than five, that small priority packet sizes.
Preliminary
Altera Corporation
SerialLite MegaCore Function v1.0.0 Issues
Design Impact
Model generation synthesis fail when Number Lanes parameter greater. praif_almost_full parameter derived from priority port FIFO buffer size minus eight, intended compensate pipeline delay. This parameter represents highest fill value after which, transaction received, link goes down. However, formula used Toolbench praif_almost_full parameter generates FIFO buffer that small (negative value) that cannot handle worst-case receiver latency, leading overflows loss data.
Workaround
priority packets, follow these steps: Open Toolbench-produced wrapper file text editor. Find line that sets praif_almost_full parameter. Change Toolbench-computed value adding four current value.
data packets, follow these steps: Enable priority port. Change maximum packet length from (default) 256. Disable priority port. stays text box, grayed out.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
Slow Link Synchronization with VHDL Models
Functional Simulation model intended accelerate synchronization. However, VHDL model does include this enhancement synchronizes after approximately counter used during link synchronization internal cycles
Altera Corporation
Preliminary
SerialLite MegaCore Function
accelerated link synchronization. netlist hardware takes 20,000 internal cycles allow lock occur. VHDL model synchronization period matches results obtained hardware testing.
Affected Configurations
This issue affects variations which VHDL chosen language during creation Functional Simulation model.
Design Impact
Simulation takes extended period time synchronize.
Workaround
Submit mySupport request, include Quartus archive containing VHDL model produced Toolbench. support team will generate VHDL Functional Simulation model with accelerated link synchronization.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
NumPriorityPackets Parameter Missing Demonstration Testbench Parameter Text File
demonstration testbench included with SerialLite MegaCore function features configuration parameters, these parameters listed testbench text file produced Toolbench. However, NumPriorityPackets parameter does appear text file when both regular priority data ports active.
Affected Configurations
This issue affects variations that have both regular data port priority data port parameters enabled.
Design Impact
This issue does impact design. However, because parameter missing from text file, value internally defaults one-causing testbench transmit only single priority packet.
Preliminary
Altera Corporation
SerialLite MegaCore Function v1.0.0 Issues
Workaround
wish send more than priority packet, must manually NumPriorityPackets value <variation>_tb_params.txt file.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
User-Defined Payload Mode Does Support Packets Greater than Bytes
demonstration testbench, packets transmitted received contain incrementing payload user-controlled payload types. user-controlled payload manually turned testbench, packet array must filled with payload data. However, variable agen.v amon.v files improperly sized; should 16-bit vector access Kbyte array, instead 8-bit vector meaning that only bytes accessed. Thus, packets over bytes corrupted when transmitted, checked properly when received.
Affected Configurations
This issue affects variations that regular data port parameter.
Design Impact
user-controlled payload option demonstration testbench used, packet sizes greater than bytes, data errors will occur packet being transmitted.
Workaround
user-controlled payload option demonstration testbench packet sizes over bytes.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
Altera Corporation
Preliminary
SerialLite MegaCore Function
Demonstration Testbench Parameter List User Guide Does Match Text File
demonstration testbench included with SerialLite MegaCore function features configuration parameters. However, parameter names testbench text file, produced Toolbench, match exactly names given SerialLite MegaCore Function User Guide. example, user guide uses NUM_PRIORITY_PACKETS, while text file uses NumPriorityPackets.
Affected Configurations
This issue affects variations MegaCore function.
Solution Status
parameter names will corrected next release SerialLite MegaCore Function User Guide.
Demonstration Testbench Fails When Generated Quartus Software
ModelSim 6.0c software produces error when running demonstration testbench. Functional Simulation model created Quartus software version contains additional parameters ALTGX macro. When simulated with older macro file, simulation generates error because parameter missing from older Altera® simulation library.
Affected Configurations
This issue affects demonstration testbenches generated Quartus software that with ModelSim 6.0c software. testbench works when generated Quartus software. ModelSim 6.0c software Altera libraries precompiled within simulation, does experience problems with Quartus 5.0-generated files.
Design Impact
simulation produces following error: Error: (vsim-3043) slite_broadcast.vo(36699): Unresolved reference 'allow_gxb_merging' ni0O1i.allow_gxb_merging.
Preliminary
Altera Corporation
SerialLite MegaCore Function v1.0.0 Issues
Workaround
Change references Altera libraries, $QUARTUS_ROOTDIR\eda\sim_lib generated _vlog_arg.txt file.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
Demonstration Testbench Does Achieve Link Synchronization
Hardware testing uses initial reset conditions; Functional Simulation models randomly assign power-up level flops instead reset path. hardware, initial value flop after power always zero. simulation, value flop after power one. power-up level affects link state machine, link fails synchronize.
Affected Configurations
This issue could affect Functional Simulation models.
Design Impact
simulation experiences extended initialization sequence that results timeout. hardware affected, works intended.
Workaround
Submit mySupport request, include Quartus archive containing your MegaCore variation files generated Toolbench. support team will generate Functional Simulation model which randomization power-up levels disabled.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
Altera Corporation
Preliminary
SerialLite MegaCore Function
Demonstration Testbench Fails Unbalanced Configurations
Verilog demonstration testbench included with SerialLite MegaCore function loops high-speed serial interface from transmitter (TX_OUT[]) receiver instantiation (RX_IN[]). receiver transmitter MegaCore functions have matching configurations (for example: CRC-32 payload protection transmitter, payload protection receiver), testbench fails.
Affected Configurations
This issue affects variations MegaCore function.
Design Impact
demonstration testbench reports error, indicates that testbench failed.
Workaround
workaround available this issue. unbalanced configurations, must create environment that uses independent SerialLite MegaCore functions.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
ModelSim 6.0c Software Produces Compilation Error When Loading Demonstration Testbench
ModelSim 6.0c software produces error when loading demonstration testbench. command vlog used compile file called sl_param.v, found MegaCore library directory. This file then called testbench using: `include "sl_param.v". reference actual MegaCore directory included could different user's environment. vlog command allows directory directly specified within testbench when using ModelSim 5.8d software, directory specified ModelSim 6.0c software.
Preliminary
Altera Corporation
SerialLite MegaCore Function v1.0.0 Issues
Affected Configurations
This issue affects demonstration testbenches that with ModelSim 6.0c ModelSim 6.0c software. testbench works with ModelSim 5.8d software.
Design Impact
simulation produces following error: Error: near "parameter": expecting: LIBRARY CONFIG Error: C:/Modeltech_60c/win32/vlog failed.
Workaround
Copy sl_param.v file from MegaCore installation directory, your directory remove file reference from MegaCore generated _vlog_arg.txt file.
Solution Status
This issue will fixed next release SerialLite MegaCore function.
ModelSim 6.0c Software Produces Fatal Error With Condition Coverage altera_mf.v File
ModelSim 6.0c software produces fatal error when loading demonstration testbench. command vlog used compile file called altera_mf.v, found MegaCore library directory.
Affected Configurations
This issue affects demonstration testbenches that with ModelSim 6.0c software. testbench works with ModelSim 6.0c software because altera_mf.v does need compiled. Also, older versions software-such ModelSim 5.8d version-are affected.
Design Impact
simulation produces following error:
Model Technology ModelSim vlog 6.0c Compiler 2005.02 2005
Compiling module lcell
Altera Corporation
Preliminary
SerialLite MegaCore Function
Compiling module global Compiling module carry Compiling module cascade Compiling module carry_sum Compiling module Compiling module soft Compiling module opndrn Compiling module row_global Compiling module prim_gdff Compiling module dffea Compiling module dffeas Compiling module ALTERA_DEVICE_FAMILIES Fatal: Unexpected signal: Error: Verilog Compiler exiting
Workaround
Edit tool command language (Tcl) script remove conditional coverage, -cover from vlog command. Change line _tb.do script vlog -cover $VLOGDefineClause $VlogArgFile
Solution Status
This issue will fixed ModelSim 6.0d software.
Serial Loopback Documented
Serial loopback dynamically enabled channel-by-channel basis using RX_SLPBK port. When RX_SLPBK signal high, blocks that active when signal remain active. Although serial loopback enabled, data still being output TX_OUT[] port. When this set, data TX_OUT[] looped back onto RX_IN[] port, overriding user data.
Affected Configurations
This issue affects variations MegaCore function.
Design Impact
serial loopback inadvertently value that does match your design intent.
Preliminary
Altera Corporation
SerialLite MegaCore Function v1.0.0 Issues
Workaround
Once understand purpose this pin, value based your design requirements.
Solution Status
This will described next release SerialLite MegaCore Function User Guide.
Limitations Signal Priority Port
SerialLite MegaCore Function User Guide's description signal priority port implies that user logic must stop writing SerialLite MegaCore function when THDAV signal deasserted. THDAV signal asserted once buffer empty, pushing store-and-forward behavior user logic, resulting much lower bandwidth. user logic strictly follows THDAV, cannot begin load second packet until first been transmitted, even though there buffers. This requirement limits priority packet bandwidth that port. interface optimized kind performance need.
Affected Configurations
This issue affects variations that have priority port parameter enabled.
Design Impact
THDAV port THENA port common setup), effective bandwidth priority port hover around 50%.
Workaround
user logic continue writing after negation signal (when enabled) mark (the must stalled until reasserted).
Solution Status
port's description will clarified next release SerialLite MegaCore Function User Guide.
Altera Corporation
Preliminary
SerialLite MegaCore Function
Contact Information Revision History
Table Revision History Version
more information, Altera's mySupport website www.altera.com/mysupport click Create Service Request. Choose Product Related Request form. Table shows revision history.
Date
April 2005
Details Change
First release SerialLite MegaCore Function errata sheet v1.0.0.
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Copyright 2005 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
Preliminary
Altera Corporation
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