Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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Athlon64 Processor Product Data Sheet
Compatible with Existing 32-Bit Code Base Including support SSE, SSE2, SSE3*, MMXTM, 940-Pin Package Specific Features 3DNow!technology legacy instructions Refer Functional Data Sheet, SSE3 supported Rev. later processors 940-Pin Package, order# 31412, functional, Runs existing operating systems drivers electrical, mechanical details 940-pin Local APIC on-chip package processors. AMD64 Technology Packaging AMD64 technology instruction extensions 940-pin lidded ceramic micro 64-bit integer registers, 48-bit virtual addresses, 1.27-mm pitch 40-bit physical addresses 31x31-row array Eight additional 64-bit integer registers total) Eight additional 128-bit SSE/SSE2/SSE3 registers 40mm 40mm ceramic substrate total) Ceramic attach Multi-Core Architecture Integrated Memory Controller Single-core dual-core options Low-latency, high-bandwidth Discrete cache structures each core 144-bit SDRAM 100, 133, 166, 64-Kbyte 2-Way Associative ECC-Protected Data Cache 64-bit operations cycle, 3-cycle latency 64-Kbyte 2-Way Associative Parity-Protected Instruction Cache With advanced branch prediction 16-Way Associative ECC-Protected Cache Exclusive cache architecture-storage addition caches Mbyte cache Machine Check Architecture Includes hardware scrubbing major ECCprotected arrays Power Management Multiple low-power states System Management Mode (SMM) ACPI compliant, including support processor performance states some models Supports eight registered DIMMs checking with double-bit detect single-bit correct
Electrical Interfaces HyperTransporttechnology: LVDS-like differential, unidirectional SDRAM: SSTL_2 JEDEC specification Clock, reset, test signals also SDRAM-like electrical specifications. HyperTransportTechnology Devices 16-bit link supporting speeds (1600 MT/s) Gigabytes/s each direction
Publication Issue Date:
30431 2007
Revision:
3.16
Advanced Micro Devices
Athlon64 Processor Product Data Sheet
30431
Rev. 3.16
2007
939-Pin Package Specific Features
Refer Functional Data Sheet, 939-Pin Package, order# 31411, functional, electrical, mechanical details 939-pin package processors. Packaging 939-pin lidded micro 1.27-mm pitch 31x31-row array 40mm 40mm organic substrate Organic attach
Socket Processor Specific Features
Refer Socket Processor Functional Data Sheet, order# 31117, functional mechanical details socket processors. Refer Family Processor Electrical Data Sheet, order# 31119, electrical details socket processors. Packaging Lidded micro 1.27-mm pitch 31x31 grid array Compliant with RoHS Directive 2002/95/EC) with lead used only small amounts specifically exempted applications Integrated Memory Controller Low-latency, high-bandwidth 144-bit DDR2 SDRAM controller operating Supports four unbuffered DIMMs checking with double-bit detect single-bit correct Electrical Interfaces HyperTransporttechnology: LVDS-like differential, unidirectional DDR2 SDRAM: SSTL_1.8 JEDEC specification Clock, reset, test signals also DDR2 SDRAM-like electrical specifications HyperTransportTechnology Devices 16-bit link supporting speeds (2000 MT/s) Gigabytes/s each direction
Integrated Memory Controller Low-latency, high-bandwidth 144-bit SDRAM 100, 133, 166, Supports four unbuffered DIMMs checking with double-bit detect single-bit correct Electrical Interfaces HyperTransporttechnology: LVDS-like differential, unidirectional SDRAM: SSTL_2 JEDEC specification Clock, reset, test signals also SDRAM-like electrical specifications HyperTransportTechnology Devices 16-bit link supporting speeds (2000 MT/s) Gigabytes/s each direction
Athlon64 Processor Product Data Sheet
30431
Rev. 3.16
2007
(1207) Processor Specific Features
Refer (1207) Processor Functional Data Sheet, order# 41696 functional mechanical details (1207) processors. Refer Family Processor Electrical Data Sheet, order# 31119 electrical details (1207) processors. Intended pairs platform. Electrical Interfaces HyperTransporttechnology: LVDS-like differential, unidirectional DDR2 SDRAM: SSTL_1.8 JEDEC specification Clock, reset, test signals also DDR2 SDRAM-like electrical specifications Packaging Lidded Land Grid Array package grid array Compliant with RoHS Directive 2002/95/EC) with lead used only small amounts specifically exempted applications Integrated Memory Controller Low-latency, high-bandwidth 144-bit DDR2 SDRAM Supports unbuffered DIMMs HyperTransportTechnology Devices Three links, 16-bits each direction, each supports 2000 MT/s GB/s each direction Each link supports connections devices, three available links connect another Athlon64 (1207) processor.
Athlon64 Processor Product Data Sheet
30431
Rev. 3.16
2007
Revision History
Date
2007 September 2006 August 2006 June 2006
Revision
3.16 3.14 3.12 3.08
Description
Sixth public release. Added (1207) processor specific features. Fifth public release. Removed change bars. Added RoHS compliance statement. Added asterisk note SSE3. Fourth public release. Added socket processor specific features SSE3 support. Added revision history. Third public release. Changed 2-page format. Added 940-pin 939-pin package specific features. Second public release. Multiple changes eight chapters. Initial public release.
June 2004
3.05
February 2004 September 2003
3.03 3.00
2006, 2007 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. information contained herein preliminary advance nature subject change without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, Arrow logo, Athlon, combinations thereof, 3DNow! trademarks Advanced Micro Devices, Inc. HyperTransport licensed trademark HyperTransport Technology Consortium. trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.

Compatible with Existing 32-Bit Code Base Including support SSE, SSE2,

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