Four 16C950 High performance UART channels 8-bit Pass-through Local (P
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OXuPCI954 DATA SHEET
Four 16C950 High performance UART channels 8-bit Pass-through Local (PCI Bridge) IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver) Efficient 32-bit, MHz, multi-function target-only controller, fully compliant Local Specification Power Management Specification Software compatible with OXmPCI954 UARTs fully software compatible with 16C550-type devices UART operation external clock source. with crystal oscillator Baud rates Mbps external clock mode Mbps asynchronous mode 128-byte deep FIFO transmitter receiver Flexible clock prescaler, from 31.875 Automated in-band flow control using programmable Xon/Xoff both directions Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR#
Integrated High Performance Quad UARTs, 8-bit Local Bus/Parallel Port, (Universal Voltage) Interface.
Programmable RS485 turnaround delay Arbitrary trigger levels receiver transmitter FIFO interrupts automatic in-band out-of-band flow control Infra-red (IrDA) receiver transmitter operation 9-bit data framing, well bits Detection data receiver FIFO Global Interrupt Status readable FIFO levels facilitate implementation efficient device drivers. Local registers provide status/control device functions multi-purpose pins, which configured input interrupt pins `wake-up' Auto-detection wide range optional MICROWIREcompatible EEPROMs, re-configure device parameters Function access, pre-configure each function prior handover generic device drivers Operation memory mapping operation (PCI Universal Voltage) Extended operating temperature range: -40° 176-pin LQFP package
DESCRIPTION
OXuPCI954 single chip solution PCI-based serial parallel expansion add-in cards. dual function device, where function offers four ultra-high performance OX16C950 UARTs, function configurable either 8-bit local bi-directional parallel port. Each UART channel OXuPCI954 fastest available PC-compatible UART, offering data rates Mbps 128-byte deep transmitter receiver FIFOs. deep FIFOs reduce overhead allow utilization higher data rates. Each UART channel software compatible with widely used industry-standard 16C550 devices (and compatibles), well OX16C95x family high performance UARTs. addition increased performance FIFO size, UARTs also provide full OX16C95x enhanced features including automated in-band flow control, readable FIFO levels, etc. enhance device driver efficiency reduce interrupt latency, internal UARTs have multi-port features such shadowed FIFO fill levels, global interrupt source register Good-Data Status, readable four adjacent DWORD registers visible logical functions space memory space. Expansion serial ports beyond four channels possible using 8-bit pass-through Local function. This provides general address/data interrupt capability discrete UART part, such Oxford Semiconductor OX16C954. Other controllers could used provide capabilities beyond additional UART ports. addressable space provided Local increased bytes, divided into four chip-select regions. This flexible expansion scheme caters cards with serial ports using external 16C950, 16C954 compatible devices, composite applications such combined serial parallel port expansion cards. Serial port cards with ports with serial ports parallel port) designed without redefining device timing parameters. parallel port IEEE 1284 compliant SPP/EPP/ECP parallel port that fully supports existing Centronics interface. parallel port enabled place local bus. external transceiver required parallel port operation device 3.3V sourced. full flexibility, default configuration register values overwritten using optional MICROWIRE compatible serial EEPROM. This EEPROM also used provide function access pre-configure devices local bus/parallel port, prior configuration accesses before control handed (generic) device drivers. OXuPCI954 used replace OXmPCI954 application where quad UARTs local bus/parallel port functionality required.
Oxford Semiconductor, Inc. 1900 McCarthy Boulevard, Suite Milpitas, 95035
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Oxford Semiconductor, Inc. 2007 http://www.oxsemi.com OXuPCI954 DataSheet DS-0058 -Sep 2007
OXFORD SEMICONDUCTOR, INC.
OXuPCI954
Improvements OXuPCI954 over Discrete Solutions
Higher degree integration OXuPCI954 device offers four internal 16C950 highperformance UARTs 8-bit local bi-directional parallel port. Multi-function device OXuPCI954 multi-function device enable users load individual device drivers internal serial ports, drivers peripheral devices connected local drivers internal parallel port. Quad Internal OX16C950 UARTs OXuPCI954 device contains four ultra-high performance UARTs, which increase driver efficiency using features such 128-byte deep transmitter receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt flow control trigger levels readable FIFO levels. Data rates Mbps. Improved access timing Access internal UARTs require zero wait state. read transaction from internal UART complete within five clock cycles write transaction internal UART complete within four clock cycles. Reduces interrupt latency OXuPCI954 device offers shadowed FIFO levels Interrupt status registers internal UARTs pins. This reduces device driver interrupt latency. Power management OXuPCI954 device complies with Power Management Specification Microsoft Communications Device-class Power Management Specification (2000). Both functions offer extended capabilities Power Management. This achieves significant power savings enabling device drivers power down functions. function this through switching channel clock, power state Wake-up (PME# generation) requested either functions. function this inputs UARTs power-state modem line inputs UARTs power-state function this MIO[2] input. Optional EEPROM OXuPCI954 device reconfigured from external EEPROM end-user's requirements. However, this required many applications default values sufficient typical applications. overrun detection mechanism built into EEPROM controller prevents system from `hanging' incorrectly programmed EEPROM.
REVISION HISTORY
Revision 2007 2007 First publication. Feature revision, including removal D3cold Modification
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TABLE CONTENTS
3.1.1
OXuPCI954 Device Modes Block Diagram Information-176-Pin LQFP
Mode Quad UARTs 8-bit Local Mode Quad UARTs Parallel Port. Descriptions
5.2.1 5.3.1 5.3.2 5.3.3 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.6.1 5.6.2 5.6.3
Configuration Operation. Target Controller
Operation. Configuration Space Configuration Space Register Accessing Logical Functions. Access Internal UARTs Access 8-bit Local Access Parallel Port Accessing Local Configuration Registers Local Configuration Control Register `LCC' (Offset 0x00). Multi-purpose Configuration Register `MIC' (Offset 0x04) Local Timing Parameter Register `LT1' (Offset 0x08) Local Timing Parameter Register `LT2' (Offset 0x0C) UART Receiver FIFO Levels `URL' (Offset 0x10) UART Transmitter FIFO Levels `UTL' (Offset 0x14). UART Interrupt Source Register `UIS' (Offset 0x18) Global Interrupt Status Control Register `GIS' (Offset 0x1C) Interrupts. Power Management. Power Management Function Power Management Function Universal Voltage Unique Option Function
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.3.1 6.3.2 6.4.1 6.5.1 6.5.2 6.5.3 6.6.1
Internal OX16C950 UARTs.
Operation Mode Selection Mode Mode Extended Mode Mode Mode Mode Register Description Tables UART Reset Configuration Hardware Reset Software Reset. Transmitter Receiver FIFOs FIFO Control Register `FCR' Line Control Status False Start Detection. Line Control Register `LCR'. Line Status Register `LSR' Interrupts Sleep Mode. Interrupt Enable Register `IER'. External-Free Release Page
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6.6.2 Interrupt Status Register `ISR'. 6.6.3 Interrupt Description 6.6.4 Sleep Mode Modem Interface 6.7.1 Modem Control Register `MCR'. 6.7.2 Modem Status Register `MSR' Other Standard Registers 6.8.1 Divisor Latch Registers `DLL DLM'. 6.8.2 Scratch Register `SPR' Automatic Flow Control 6.9.1 Enhanced Features Register `EFR'. 6.9.2 Special Character Detection. 6.9.3 Automatic In-band Flow Control 6.9.4 Automatic Out-of-band Flow Control 6.10 Baud Rate Generation. 6.10.1 General Operation. 6.10.2 Clock Prescaler Register `CPR'. 6.10.3 Times Clock Register `TCR' 6.10.4 External Clock Mode 6.10.5 Crystal Oscillator Circuit 6.11 Additional Features 6.11.1 Additional Status Register `ASR' 6.11.2 FIFO Fill Levels `TFL RFL' 6.11.3 Additional Control Register `ACR' 6.11.4 Transmitter Trigger Level `TTL' 6.11.5 Receiver Interrupt. Trigger Level `RTL' 6.11.6 Flow Control Levels `FCL' `FCH' 6.11.7 Device Identification Registers 6.11.8 Clock Select Register `CKS' 6.11.9 Nine-bit Mode Register `NMR'. 6.11.10 Modem Disable Mask `MDM'. 6.11.11 Readable `RFC'. 6.11.12 Good-data Status Register `GDS' 6.11.13 Port Index Register `PIX' 6.11.14 Clock Alteration Register `CKA'. 6.11.15 RS485 Delay Enable `RS485_DLYEN' 6.11.16 RS485 Delay Count `RS485_DLYCNT'.
Local bus.
Overview. Operation. Configuration Programming
8.1.1 8.1.2 8.1.3 8.1.4 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6
Bidirectional Parallel Port.
Operation Mode Selection. Mode Mode. Mode Mode Parallel Port Interrupt. Register Description Parallel Port Data Register `PDR'. FIFO Address RLE. Device Status Register `DSR'. Device Control Register `DCR' Address register `EPPA'. Data Registers `EPPD1-4'. External-Free Release Page
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8.3.7 8.3.8 8.3.9 8.3.10 8.3.11
OXuPCI954
Data FIFO Test FIFO Configuration Register Configuration Register Extended Control Register `ECR' Specification Zone Header Zone Local Configuration Registers Zone Identification Registers. Zone Configuration Registers. Zone Power Management DATA (and DATA_SCALE Zone) Zone Function Access. Electrical Characteristics Timings Local Serial Ports.
9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6
Serial EEPROM
10.1 11.1 11.2 11.3
Operating Conditions
Electrical Characteristics.
13.1
Timing Waveforms. Package Information
176-Pin LQFP
Ordering Information.
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OXUPCI954 DEVICE MODES
OXuPCI954 supports modes operation. These modes summarized following table. Device Mode Mode Selection MODE MODE Functionality Function Quad UARTs Function 8-bit local Function Quad UARTs Function Parallel Port
OXuPCI954 pin-compatible with OX16PCI954 OXmPCI954, same other aspects.
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BLOCK DIAGRAM
MODE FIFOSEL
Config. Interface SOUT[3:0] SIN[3:0]
Function Quad UARTs
RTS[3:0] DTR[3:0] CTS[3:0] DSR[3:0]
AD[31:0] C/BE[3:0]# Interface Data Control
DCD[3:0] RI[3:0]
PCI_CLK FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PERR# IDSEL RST# INTA# PME# Interface
Interrupt Logic
Pins
MIO[10:0]
PD[7:0]
ACK# BUSY Parallel Port SLCT ERR# SLIN# INIT# AFD# XTLI XTLO OSCDIS XTLSEL UART_Clk_Out Local_Bus Clock Baud Rate Generator Function STB#
LBA[7:0] LBCS[3:0] LBD[7:0] Local LBWR#
EE_DI EEPROM Interface
EE_CS EE_CK EE_DO
LBRD# LBRST
DATA_DIR
OXuPCI954 Block Diagram
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INFORMATION-176-PIN LQFP
Mode Quad UARTs 8-bit Local
connect these pins: 136, 137, 138,
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3.1.1
Mode Quad UARTs Parallel Port
connect these pins: 112, 113, 114, 115, 116, 117, 124, 136, 137, 138,
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Descriptions
actual pinouts OXuPCI954 device (for various modes), refer Section Information. direction table page Interface Modes 149, 150, 151, 154, 155, 157, 158, 160, 164, 165, 167, 168, 169, 170, 171, 174, 161, 175,
Dir1 P_I/O
Name AD[31:0]
Description Multiplexed Address/Data
P_I/O P_I/O P_OD P_OD
C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PERR# IDSEL RST# INTA# PME#
Command/Byte enable system clock (33MHz) Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialization device select system reset interrupt Power management event
Serial Port Pins Modes
Dir1
Name FIFOSEL
O(h) SOUT[3:0] IrDA_Out[3:0]
Description FIFO select. backward compatibility with 16C550, 16C650 16C750 devices UARTs' FIFO depth when FIFOSEL low. FIFO size increased when FIFOSEL high. unlatched state this readable software. FIFO size also setting FCR[5] when LCR[7] set, putting device into Enhanced mode. These four pins present modes they serve functions, follows: UART serial data outputs. UART IrDA data output when MCR[6] corresponding channel Enhanced mode. These four pins present modes they serve functions, follows: UART serial data inputs. UART IrDA data input when IrDA mode enabled (see above). Page
I(h) I(h) DS-0058 SIN[3:0] IrDA_In[3:0]
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Serial Port Pins Modes
Dir1 I(h)
Name DCD[3:0]#
Description Active-low modem data-carrier-detect input These four pins present modes they serve three functions, follows: Active-low modem data-terminal-ready output. automated DTR# flow control enabled, DTR# asserted deasserted receiver FIFO reaches falls below programmed thresholds, respectively. RS485 half-duplex mode, DTR# programmed reflect state transmitter empty automatically control direction RS485 transceiver buffer (see register ACR[4:3]). Transmitter clock (baud rate generator output). isochronous applications, transmitter clock asserted DTR# pins (see register CKS[5:4]). Active-low modem request-to-send output. automated RTS# flow control enabled, RTS# deasserted reasserted whenever receiver FIFO reaches falls below programmed thresholds, respectively. Active-low modem clear-to-send input. automated CTS# flow control enabled, upon deassertion CTS# pin, transmitter will complete current character enter idle mode until CTS# reasserted. Note: inband flow control characters transmitted regardless state CTS# pin. These four pins present modes they serve functions, follows: Active-low modem data-set-ready input. automated DSR# flow control enabled, upon deassertion DSR# pin, transmitter will complete current character enter idle mode until DSR# reasserted. Note: inband flow control characters transmitted regardless state DSR# pin. External receiver clock isochronous applications. Rx_Clk_In selected when CKS[1:0] `01'. Active-low modem Ring-Indicator input External transmitter clock. This clock used transmitter (and indirectly receiver) when CKS[6]='1'.
O(h)
DTR[3:0]#
O(h)
485_En[3:0]
O(h) O(h)
Tx_Clk_Out[3:0] RTS[3:0]#
I(h)
CTS[3:0]#
I(h) DSR[3:0]#
I(h) I(h) I(h)
Rx_Clk_In[3:0] RI[3:0]# Tx_Clk_In[3:0]
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Clock Interface Pins Modes
Dir1
Name XTLO XTLI OSCDIS
Description Crystal oscillator output when OSCDIS `0'. External clock source input when OSCDIS Crystal oscillator input when OSCDIS `0', 20MHz. when OSCDIS Oscillator disable. When internal crystal oscillator enabled crystal needs attached XTLI/XTLO. XTLSEL must according crystal frequency that used 20Mhz). When internal crystal oscillator disabled external oscillator source 60MHz) input XTLO. XTLI XTLSEL must Defines frequency crystal attached XTLI/XTLO (when OSCDIS `0')
XTLSEL
8-bit Local Mode 114, 115, 116, 105, 106, 108, 118, 119, 120, 100, 101, 102,
Dir1 O(h) O(h) O(h) O(h) I/O(h)
Name UART_CLK_Out LBRST LBRST# LBDOUT LBCLK LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBD[7:0]
Description Buffered crystal output. This clock drive external UARTs connected local bus. enabled disabled software. Local active-high reset. Local active-low reset. Local data enable. This used external transceivers; high when LBD[7:0] output mode when they input mode. Buffered clock. enabled disabled software. Local active-low Chip-Select (Intel mode). Local active-low Data-Strobe (Motorola mode). Local active-low write-strobe (Intel mode). Local Read-not-Write control (Motorola mode). Local active-low read-strobe (Intel mode). Permanent high impedance (Motorola mode). Local address signals. Local data signals.
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Parallel Port Mode
Dir1 I(h)
Name ACK#
Description Acknowledge (SPP mode). ACK# asserted (low) peripheral indicate that successful data transfer taken place. Identical function ACK# (EPP mode). Paper Empty. Activated printer when runs paper. Busy (SPP mode). BUSY asserted (high) peripheral when ready accept data. Wait (EPP mode). Handshake signal interlocked IEEE 1284 compliant cycles. Select (SPP mode). Asserted host select peripheral. Address strobe (EPP mode) provides address read write strobe. Peripheral selected. Asserted peripheral when selected. Error. Held peripheral during error condition. Initialize (SPP mode). Commands peripheral initialize. Initialize (EPP mode). Identical function mode. Auto Feed (SPP mode, open-drain). Data strobe (EPP mode) provides data read write strobe. Strobe (SPP mode). Used peripheral latch data currently available PD[7:0]. Write (EPP mode). Indicates write cycle when read cycle when high Parallel data bus. Parallel port data enable. This should used external transceivers signaling; high when PD[7:0] output mode when they input mode.
I(h) I(h) I(h) I(h)
INTR# BUSY WAIT# SLIN# ADDRSTB# SLCT ERR# INIT# INIT# AFD# DATASTB# STB# WRITE# PD[7:0] PDOUT
OD(h) O(h)
I(h) I(h) OD(h) O(h) OD(h) O(h)
OD(h) O(h)
100, 101, 102,
I/O(h)
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Multi-purpose External Interrupt Pins Modes Dir1 Name MODE I/O(h) MIO0 I/O(h) I/O(h) I/O(h) MIO1 MIO2 PME_In MIO[10:3]
Description
Multi-purpose drive high low, assert interrupt. Output Driving `0'. left No-connect. Multi-purpose drive high low, assert interrupt long LCC[6:5] "00"). Output Driving (when LCC[6:5] `00') left No-Connect. Multi-purpose When LCC[7] this drive high low, assert interrupt. Input power management event. When LCC[7] this input assert function PME#. Multi-purpose pins. drive high low, assert interrupt.
125, 126, 127, 128, EEPROM Pins Modes
Dir1 IU(h)
Name EE_CK EE_CS EE_DI
EE_DO
Description EEPROM clock. EEPROM active-high Chip Select. EEPROM data with internal pull-up. When serial EEPROM connected, this should pulled using 1-10k resistor. When EEPROM used internal pull-up sufficient. connected external EEPROM's EE_DO used). EEPROM data out. connected external EEPROM's EE_DI used).
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Miscellaneous Pins
Dir1
Name MODE
Description Mode selector Function Quad UART. Function 8-bit local bus. Function Quad UART. Function Parallel port.
Power Ground 107, 131,
Type
Name
Description Power Supply (3.3
140, 156, 162,
Universal Voltage Defines (clamping) voltage Buffers. connected connector. Power Supply Ground
110, 121, 129, 141, 143, 145, 152, 153, 159, 166,
Table Descriptions Direction P_I/O P_OD I(h) IU(h) I/O(h) O(h) OD(h) input output PCITristates bi-directional open drain Input Input Input with internal pull-up Bi-Directional Output Output Open drain Open drain connect Ground Voltage Only Only Only Only LVTTL level LVTTL level, tolerant LVTTL level, tolerant LVTTL level, tolerant Standard Output tolerant (High Voltage BI-Direct output mode) Standard Open-drain Output tolerant (High Voltage BI-Direct open-drain mode)
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CONFIGURATION OPERATION
drivers then access functions assigned addresses usual fashion, with improved data throughput provided PCI. Each function operates though separate device. However there Local Configuration Registers that used enable signals interrupts, configure timings, improve efficiency multi-port drivers. This architecture enables separate drivers installed each function. Generic port drivers hooked functions individually, more efficient multi-port drivers hook both functions, accessing Local Configuration Registers from either. registers default after reset suitable values typical applications such port serial, combo 4-port serial/1port parallel add-in cards. However, identification, control timing registers redefined using optional serial EEPROM.
OXuPCI954 multi-function, target-only device, compliant with Local Specification, Revision Power Management Specification, Revision 1.1. OXuPCI954 affords maximum configuration flexibility treating internal UARTs, local parallel port separate logical functions. Each function configuration space therefore recognized configured BIOS separately. functions used configured Mode Selection shown Section OXuPCI954 Device Modes. OXuPCI954 configured system start-up software during bootstrap process that follows reset. system scans reads vendor device identification codes from devices finds. then loads device-driver software according this information configures I/O, memory interrupt resources. Device
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TARGET CONTROLLER
Operation
responds following access while OXuPCI954 reading from serial EEPROM. OXuPCI954 performs medium-speed address decoding defined specification. asserts DEVSEL# signal clocks after FRAME# first sampled transaction frames which address chip. internal UARTs accessed with zero wait states inserted. Fast back-to-back transactions supported OXuPCI954 target, master perform faster sequences write transactions UARTs local when inter-frame turn-around cycle required. device supports combination byte-enables Configuration Registers Local Configuration Registers. byte-enable asserted, that byte unaffected write operation undefined data returned upon read. OXuPCI954 performs parity generation checking transactions defined standard. Note this entirely unrelated serial data parity which handled within UART functional modules themselves. parity error occurs during address phase, device will report error standard asserting SERR# signal. However that address/command combination decoded valid access, will still complete transaction though parity check correct. OXuPCI954 does support kind caching data buffering addition that already provided within UARTs transmit receive data FIFOs. general, registers UARTs local prefetched because there side-effects read.
OXuPCI954
Configuration access: OXuPCI954 responds type configuration reads writes IDSEL signal asserted address selecting configuration registers function device will respond configuration transaction asserting DEVSEL#. Data transfer then follows. other configuration transaction will ignored OXuPCI954. reads/writes: address compared with addresses reserved Base Address Registers (BARs). address falls within assigned ranges, device will respond transaction asserting DEVSEL#. Data transfer follows this address phase. UARTs 8-bit local controller, only byte accesses possible. accesses these regions, controller compares AD[1:0] with byte-enable signals defined specification. access always completed; however correct signal present transaction will have effect. Memory reads/writes: These treated same transactions, except that memory ranges used. Memory access single-byte regions always expanded DWORDs OXuPCI954. other words, OXuPCI954 reserves DWORD byte single-byte regions. device allows user define active byte lane using LCC[4:3] that Big-Endian systems hardware swap byte lane automatically. Memory mapped access single-byte regions, OXuPCI954 compares asserted byte-enable with selected byte-lane LCC[4:3] completes operation match occurs, otherwise access will complete normally bus, will have effect either internal UARTs local controller. other cycles (64-bit, special cycles, reserved encoding etc.) ignored.
Configuration Space
OXuPCI954 dual-function device, where each logical function configuration space. required fields standard header implemented, plus Power Management Extended Capability register set. format configuration space shown following tables. general, writes registers that implemented ignored, reads from unimplemented registers return
OXuPCI954 will complete transactions disconnect-with-data, i.e. device will assert STOP# signal alongside TRDY#, ensure that Master does continue with burst access. exception this Retry, which will signaled response
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5.2.1
Configuration Space Register
Predefined Region
Configuration Register Description
Device Status BIST
Vendor Command
Class Code Revision Header Type Reserved Reserved Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Reserved Subsystem Subsystem Vendor Reserved Reserved Cap_Ptr Reserved Reserved Reserved Interrupt Interrupt Line
Offset Address
User Defined Region Power Management Capabilities (PMC) Data Reserved Next Cap_ID Control/Status Register (PMCSR)
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Configuration Space Default Values Function
Register Name Function Reset Value Modes Mode Mode Quad UART (Optional Unique Bar) 0x1415 0x9501 (0x9504)* 0x0000 0x0290 0x01 0x070006 0x80 0x00000001 (0x00000001)* 0x00000000 (0x00000001)* 0x00000001 (0x00000001)* 0x00000000 (0x00000001)* Used (0x00000001)* Used (0x00000000)* 0x1415 0x0000 0x40 0x00 0x01 (INTA only) 0x01 0x00 0x6C02 0x0000 0x00
OXuPCI954
Program Read/Write EEPROM
Vendor Device Command Status Revision Class Code Header Subsystem Vendor Subsystem Cap. Interrupt Line Interrupt Next Capabilities Control/Status Register Data Register
W(Bit (Data Scale)
device supports unique mode EEPROM. this mode, each UART accessible base address register. Otherwise, UARTs accessible through base address register. Device must return 0x9504 when unique mode EEPROM, downloading into configuration space.
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Configuration Space Default Values Function
Register Name Mode 8-BIT LOCAL Vendor Device Command Status Revision Class Code Header Subsystem Vendor Subsystem Cap. Interrupt Line Interrupt Next Capabilities Control/Status Register Data Register 0x1415 0x9511 0x0000 0x0290 0x01 0x068000 0x80 0x00000001 0x00000000 0x00000001 0x00000000 Used Used 0x1415 0x0000 0x40 0x00 0x01 0x01 0x00 0x6C02 0x0000 0x00 0x00000001 0x070101 0x9513 Function Reset Value Modes Mode PARALLELPORT
OXuPCI954
Program Read/Write EEPROM W(Bit (Data Scale)
Accessing Logical Functions
Access UARTs, local parallel port achieved standard Memory mapping, addresses defined Base Address Registers (BARs) configuration space. BARs configured system allocate blocks Memory space logical functions, according size required function. addresses allocated then used access functions. mapping these BARs, which dependent upon mode device, shown following tables. Function Quad UARTs Common Space (default) Internal UARTs (I/O mapped) Internal UARTs (Memory mapped) Local configuration registers (I/O mapped) Local configuration registers (Memory mapped) Unused Unused Quad UARTs Unique mode* Internal UART0 (I/O Mapped) Internal UART1 (I/O Mapped) Internal UART2 (I/O Mapped) Internal UART3 (I/O Mapped) Local configuration registers (I/O mapped) Internal UARTs/ Local configuration registers (Memory mapped)
Unique Mode enabled though EEPROM setting MIC(26). EEPROM must also Device function 0x9504.
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Function Local
Parallel port Local (I/O mapped) Parallel port base registers Local (Memory mapped) Parallel port extended registers Local configuration registers (I/O mapped) Local configuration registers (Memory mapped) Unused Unused unique option device been enabled (via EEPROM), BAR0 BAR3 used address each UART individually space, BAR5 used address UARTs Memory Space. function reserves 8-byte blocks space BAR0 BAR3 4Kbyte block memory space BAR5. Once access Memory access enable bits Command register (configuration space) set, UARTs accessed according following tables. UART Register Offset from UARTs Base Address Function0 space (hex) UART0 UART1 UART2 UART3 (BAR0) (BAR1) (BAR2) (BAR3)
5.3.1
Access Internal UARTs
Memory Space
Base Address Registers internal UARTs dependent upon whether unique option been enabled Function Section "Unique Option" further Details. When unique option enabled (default), then function used access internal UARTs. function reserves 32-byte block space 4Kbyte block memory space. Once access Memory access enable bits Command register (configuration space) set, UARTs accessed according following tables. UART Register UART Register Offset from Base Address Function0 space (hex) UART0 UART1 UART2 UART3 Offset from Base Address Function0 Memory space (hex)
UART Register
Offset from Base Address Function0 Memory space (hex) UART0 UART1 UART2 UART3
Table Address Internal UARTs (I/O Memory)
Note Since memory space reserved full address used decoding, there number aliases UARTs allocated memory region.
Note that unique mode operation, local registers memory space occupy same Base Address Register (BAR5) internal UARTs Memory Space. selects region accessed. Access addresses will directed internal UARTs, access addresses will directed local registers.
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always zero, only chip select line LBCS0# selected. this case address offset 00-1Fh asserts LBCS0# other chip-select lines remain inactive permanently. With default values, address local address accesses same internal UARTs (when UARTs common Base Address).
5.3.2
Access 8-bit Local
When local enabled (Mode access works similar fashion internal UARTs. function reserves block space block memory space. block size user definable range bytes, memory range fixed 4Kbytes.
space
order minimize usage space, block size BAR0 Function1 user definable range bytes. Having assigned address range, user define adjacent address bits decode four chip selects internally. This facility allows glueless implementation local connecting four external peripheral chips. address range lower address chip-select decoding (Lower-Address-CS-Decode) defined Local Configuration register (see [26:20] Section 6.4.4). 8-bit local eight address lines (LBA[7:0]) that correspond maximum address space. maximum allowable block size allocated space (i.e. bytes), then access space byte aligned, LBA[7:0] equal AD[7:0] respectively. When user selects address range which less than bytes, corresponding upper address lines will logic zero. region divided into four chip-select regions when user selects second uppermost non-zero address chip-select decoding. example 32bytes space reserved, local address lines A[4:0] active remaining address lines zero. generate four chip-selects user should select Lower-Address-CS-Decode. this case A[4:3] will used internally decode chip-selects, asserting LBCS0# when address offset 00-07h, LBCS1# when offset 08-0Fh, LBCS2# when offset 10-17h, LBCS3# when offset 18-1Fh. region divided into chip-select regions selecting uppermost address decode chip selects. above example, user select Lower-Address-CS-Decode, thus using A[5:4] internally decode chip selects. this example LBA5 always zero, only chip-select lines LBCS0# LBCS1# will decoded into, asserting LBCS0# when address offset 000Fh LBCS1# when offset 10-1Fh. region allocated single chip-select region assigning address beyond selected range Lower-Address-CS-Decode (but above A8). above example, user selects LowerAddress-CS-Decode, A[6:5] will used internally decode chip-selects. this example LBA[7:5] DS-0058
Memory Space
memory base address registers have allocated fixed size 4Kbytes address space. Since local address lines OXuPCI954 only implements DWORD aligned accesses memory space, bytes addressable space chip select expanded Unlike access, memory access upper address lines always active internal chip-select decoding logic ignores user setting Lower-Address-CS-Decode (LT2[26:23]) uses AD[11:10] decode into chip-select regions. When local accessed memory space, A[9:2] asserted LBA[7:0]. chip-select regions defined below. Local Chip-Select (Data-Strobe) LBCS0# (LBDS0#) LBCS1# (LBDS1#) LBCS2# (LBDS2#) LBCS3# (LBDS3#) Offset from Function1 (Memory space) Lower Address Upper Limit 000h 3FCh 400h 7FCh 800h BFCh C00h FFCh
Table Address Local (Memory)
Note: description given memory accesses Inteltype configuration local bus. Motorola-type configuration, chip select pins redefined data strobe pins. this mode local offers address lines four data-strobe pins.
5.3.3
Access Parallel Port
When parallel port enabled (Mode access parallel port works definitions usual, except that there BARs corresponding sets registers defined operate IEEE1284 EPP/ECP bidirectional parallel port. user change space block size BAR0 over-writing default values LT2[25:20] using serial EEPROM. example, user reduce allocated space BAR0 bytes setting LT2[22:20] `001'. block size allocated BAR1 fixed Bytes. Legacy parallel ports expect upper register mapped 0x400 above base block, therefore BARs Page
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fixed with this relationship, generic parallel port drivers used operate device modes. Example: BAR0 0x00000379 bytes address 0x378) BAR1 0x00000779 bytes address 0x778)
OXuPCI954
this relationship used, custom drivers will needed.
Accessing Local Configuration Registers
local configuration registers device specific registers which accessed from either function. They mapped Memory Base Addresses typically BAR2 BAR3 each function. exception when device operates unique mode, which access local registers function will through BAR4 BAR5. transactions, access limited byte reads/writes. Memory Transactions, accesses Word Dword accesses, however little-endian systems such Intel 80x86 byte order will reversed. following table lists definitions local registers, with offsets (from Base Address Register) defined each local register.
5.4.1
Local Configuration Control Register `LCC' (Offset 0x00)
This register defines control ancillary functions such Power Management, external clock reference signals serial EEPROM. individual bits described below. Bits Description Mode Status. These bits return state Mode pin. Reserved. Returns `X'. Enable UART clock output. When this set, buffered version UART clock output "UART_CLK_Out". When this low, UART_CLK_Out permanently low. Endian Byte-Lane Select memory access 8-bit peripherals. Select Data[7:0] Select Data[23:16] Select Data[15:8] Select Data[31:24] Memory access OXuPCI954 always DWORD aligned. When accessing 8-bit regions like internal UARTs, 8-bit local parallel port, this option selects active byte lane. both architectures little endian, default value will used systems, however, some non-PC architectures need select byte lane. Power-down filter time. These bits define value internal filter time power-down interrupt request power management circuitry Function0. Once Function0 ready into power down mode, OXuPCI954 will wait specified filter time Function0 still power-down request mode, assert interrupt (see Section 5.6). power-down request disabled seconds seconds seconds Function1 MIO2_PME Enable. value enables MIO2 PME_Status PMCSR register, hence assert PME# enabled. value disables MIO2 from setting PME_Status (see Section 5.6). Reserved. These bits used test purposes. device driver must write zeros these bits. EEPROM Clock. read write EEPROM, toggle this generate EEPROM clock (EE_CK pin). External-Free Release Read/Write
EEPROM
Reset
23:8
0000h
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Bits Description EEPROM Chip Select. When EEPROM chip-select EE_CS activated (high). When EE_CS de-active (low). EEPROM Data Out. writes EEPROM, this output input-data EEPROM. This output EE_DO clocked into EEPROM EE_CK. EEPROM Data reads from EEPROM, this input output-data EEPROM connected EE_DI pin. EEPROM Valid. indicates that valid EEPROM program present Reload configuration from EEPROM. Writing this re-loads configuration from EEPROM. This self-clearing after EEPROM read EEPROM Overrun Indication (when set). conjunction with (Valid EEPROM) this indicates whether successful EEPROM download taken place. Successful download will have EEPROM_VALID EEPROM OVERRUN Reserved Read/Write
EEPROM
OXuPCI954
Reset
5.4.2
Multi-purpose Configuration Register `MIC' (Offset 0x04)
This register configures operation multi-purpose pins `MIO[11:0], well providing Enhanced Mode Features, follows. Bits Description MIO0 Configuration Register (When Device Mode `001'/'101'). MIO0 non-inverting input MIO0 inverting input MIO0 output driving MIO0 output driving When parallel port enabled, (Device Mode `001'/'101'), MIO[0] unused will remain forcing output mode. MIO1 Configuration Register (When LCC[6:5] `00'). MIO1 non-inverting input MIO1 inverting input MIO1 output driving MIO1 output driving When power-down mode Function enabled (LCC[6:5] `00'), MIO1 unused will remain forcing output mode. MIO2 Configuration Register (When LCC[7]='0'). MIO2 non-inverting input MIO2 inverting input MIO2 output driving MIO2 output driving When LCC[7] set, MIO2 re-defined PME_Input. polarity will controlled MIC[4]. sets sticky PME_Status Function1. MIO3 Configuration Register. MIO3 non-inverting input MIO3 inverting input MIO3 output driving External-Free Release
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Read/Write
Reset
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Bits Description MIO3 output driving MIO4 Configuration Register. MIO4 non-inverting input MIO4 inverting input MIO4 output driving MIO4 output driving MIO5 Configuration Register. MIO5 non-inverting input MIO5 inverting input MIO5 output driving MIO5 output driving MIO6 Configuration Register. MIO6 non-inverting input MIO6 inverting input MIO6 output driving MIO6 output driving MIO7 Configuration Register. MIO7 non-inverting input MIO7 inverting input MIO7 output driving MIO7 output driving MIO8 Configuration Register. MIO8 non-inverting input MIO8 inverting input MIO8 output driving MIO8 output driving MIO9 Configuration Register. MIO9 non-inverting input MIO9 inverting input MIO9 output driving MIO9 output driving MIO10 Configuration Register. MIO10 non-inverting input MIO10 inverting input MIO10 output driving MIO10 output driving Reserved. device driver must write zeros these bits. UART `Unique BAR' mode EEPROM When (1), sets Function such that each UART accessed through Base Address Register. write transactions must affect status this bit. Reserved Reserved. Reserved. device driver must write zeros these bits. Parallel Port Filter Disable When disables noise filters parallel port data lines status lines. Filters enabled default. Relevant only when Mode
OXuPCI954
EEPROM
Read/Write
Reset
11:10
13:12
15:14
17:16
19:18
21:20
25:22
0000
29:30
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5.4.3
Local Timing Parameter Register `LT1' (Offset 0x08)
Local Timing Parameter registers (LT1 LT2) define operation timing parameters used local bus. timing parameters programmed 4-bit registers define assertion/de-assertion local control signals. value programmed these registers defines number clock cycles after Reference Cycle when events occur, where Reference Cycle defined clock cycles after master asserts IRDY# signal. following arrangement provides flexible approach users define desired timing their peripheral devices. timings refer Memory mapped access BAR0 BAR1 Function1. Bits Description Read Chip-select Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins asserted (low) during read operation from local bus.1 These bits unused Motorola-type interface. Read Chip-select De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins de-asserted (high) during read from local bus. These bits unused Motorola-type interface. Write Chip-select Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins asserted (low) during write operation local bus. These bits unused Motorola-type interface. Write Chip-select De-assertion (Intel-type interface). Defines number clock cycles after reference cycle when LBCS[3:0]# pins de-asserted (high) during write operation local bus. Read-not-Write De-assertion during write cycles (Motorola-type interface). Defines number clock cycles after reference cycle when LBRDWR# de-asserted (high) during write local bus. Read Control Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBRD# asserted (low) during read from local bus. Read Data-strobe Assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins asserted (low) during read from local bus. Read Control De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBRD# deasserted (high) during read from local bus. Read Data-strobe De-assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins de-asserted (high) during read from local bus. Write Control Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBWR# asserted (low) during write local bus. Write Data-strobe Assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins asserted (low) during write local bus. DS-0058 External-Free Release Page Read/Write
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Reset
parallel port)
11:8
15:12
19:16
parallel port)
23:20
parallel port)
27:24
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Bits 31:28 Description Write Control De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBWR# deasserted (high) during write local bus. Write Data-strobe De-assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins de-asserted (high) during write cycle local bus.
Note Only values range (0-10 decimal) valid. Other values reserved. notes following page.
OXuPCI954
Read/Write
EEPROM
Reset
5.4.4
Bits 11:8
Local Timing Parameter Register `LT2' (Offset 0x0C)
Description Write Data Assertion. This register defines number clock cycles after Reference Cycle when pins actively drive data during write operation local bus. Write Data De-assertion. This register defines number clock cycles after Reference Cycle when pins high-impedance during write operation local bus. Read Data Assertion. This register defines number clock cycles after Reference Cycle when pins actively drive data read operation from local bus. Read Data De-assertion. This register defines number clock cycles after Reference Cycle when pins high-impedance during beginning read cycle from local bus. Reserved. Space Block Size BAR0 Function1. Reserved Bytes Bytes Bytes Bytes Bytes Bytes Bytes Read/Write
EEPROM
Reset parallel port) `100' (=`010' parallel port)
15:12 19:16 22:20
26:23
28:27
Local Chip-select Parameter `Lower-Address-CS-Decode'. space 8-bit local 1000 0000 1001 0001 1010 0010 1011 0011 1100 0100 1101 0101 1110 0110 1111 0111 Reserved Local Software Reset. When this Local reset activated. When this Local reset de-activated. Local Clock Enable. When this Local clock (LBCK) enabled. When this LBCK permanently low. External-Free Release
`0001' (=`0010' parallel port)
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Bits Description Local Clock buffered clock. Interface Type. When (=0), Local configured Intel-type operation, otherwise configured Motorola-type operation. Note that when Mode[1:0] `01', this hard wired Read/Write
EEPROM
OXuPCI954
Reset
Note Note Note
Only values range (0-10 decimal) valid. Other values reserved writing higher values causes interface retry accesses local unable complete transaction clock cycles. Lower-Address-CS-Decode parameter described Section 5.3.2 Section These bits unused Memory access 8-bit local which uses fixed decoding allocate regions chip selects. further information local bus, Section Local Bus, UARTs parallel port reset with reset. Addition, user issue Software Reset Command.
LT2[15:0] enable card designer control data during idle periods. default values will configure local data pins remain forcing (LT2[7:4] Fh). LT[15:8] programmed place highimpedance beginning read cycle back forcing read cycle. systems that require data stay high-impedance, card designer should write appropriate value range LT2[7:4]. This will place data high impedance write cycle. Whenever value programmed LT2[7:4] does equal local controller will ignore setting LT2[15:8] data will high-impedance outside write cycles. this case card designer should place external pull-ups data pins LBD[7:0]. While configuration data read from external EEPROM, pins remain high-impedance state. timing registers define local timing parameters based signal changes relative reference cycle which defined clock cycles after IRDY# asserted first time frame. following parameters fixed relative reference cycle.
local address pins LBA[7:0] asserted during reference cycle. write operation, local data available during reference cycle, however buffers change direction programmed LT2[3:0]. Motorola type write operation, Read-not-Write (LBRDWR#) asserted (low) during reference cycle. read cycle this remains high throughout duration operation. default settings registers provide clock cycle address chip-select control signal set-up time, clock cycle address chipselect from control signal hold time, clock cycles pulse duration read write control signals clock cycle data hold time. These parameters acceptable using external OX16C950 OX16C954 devices connected local bus, Intel mode. Some redefinition will required operated Motorola mode. user should take great care when programming local timing parameters. example, defining value chip-select assertion which larger that value defined chip-select de-assertion defining chipselect assertion value which greater than control signal assertion will result obvious invalid local cycles.
5.4.5
UART Receiver FIFO Levels `URL' (Offset 0x10)
receiver FIFO level internal UARTs shadowed Local configuration registers follows: Bits 15:8 23:16 31:24 Description UART0 Receiver FIFO Level (RFL[7:0]) UART1 Receiver FIFO Level (RFL[7:0]) UART2 Receiver FIFO Level (RFL[7:0]) UART3 Receiver FIFO Level (RFL[7:0]) Read/Write
EEPROM
Reset 0x00h 0x00h 0x00h 0x00h
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5.4.6
UART Transmitter FIFO Levels `UTL' (Offset 0x14)
transmitter FIFO level internal UARTs shadowed Local configuration registers follows: Bits 15:8 23:16 31:24 Description UART0 Transmitter FIFO Level (TFL[7:0]) UART1 Transmitter FIFO Level (TFL[7:0]) UART2 Transmitter FIFO Level (TFL[7:0]) UART3 Transmitter FIFO Level (TFL[7:0]) Read/Write
EEPROM
Reset 0x00h 0x00h 0x00h 0x00h
5.4.7
UART Interrupt Source Register `UIS' (Offset 0x18)
UART Interrupt Source register described below: Bits 11:6 17:12 23:18 26:24 Description UART0 Interrupt Source Register (ISR[5:0]) UART1 Interrupt Source Register (ISR[5:0]) UART2 Interrupt Source Register (ISR[5:0]) UART3 Interrupt Source Register (ISR[5:0]) Reserved UART0 Good-Data Status UART1 Good-Data Status UART2 Good-Data Status UART3 Good-Data Status Global Good-Data Status. This logical bits i.e. Good-Data Status internal UARTs set. Read/Write
EEPROM
Reset
Good-Data status given internal UART when following conditions met: reads level0 (no-interrupt pending), level (receiver data available), level (receiver time-out) level (transmitter empty) interrupt LSR[7] clear there parity error, framing error break FIFO LSR[1] clear over-run error occurred
device driver software reads receiver FIFO levels (URL) followed this register, then Good-Data status given channel set, driver remove number bytes indicated FIFO level without need read line status register that channel. This feature enhances driver efficiency. given channel, Good-Data status set, then software driver should examine corresponding bits. example low, then driver should examine bits down obtain ISR[5:0] UART2. indicates level higher interrupt, interrupt change state modem lines detection flow control characters. device driver-software should then take appropriate measures would other 550/950 driver. When indicates level (receiver status) interrupt then driver examine Line Status Register (LSR) relevant channel. Since reading clears LSR[7], device driver-software should either flush empty contents receiver FIFO, otherwise Good-Data status will longer valid. UART Receiver FIFO Level (URL), UART Transmitter FIFO Level (UTL), UART Interrupt Source register (UIS) Global Interrupt Status register (GIS) allocated adjacent address offsets (10h 1Ch) Base Address Register. device driver-software read above registers single burst read operation. location offset registers such that FIFO levels usually read before status registers that status characters indicated receiver FIFO levels valid. DS-0058 External-Free Release Page
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5.4.8
Bits
Global Interrupt Status Control Register `GIS' (Offset 0x1C)
Description UART Interrupt Status. These bits reflect internal interrupt states UART3 UART0 respectively.1 MIO0 Status (When device mode This reflects state internal MIO[0]. internal MIO[0] reflects non-inverted inverted state MIO0 pin.2 When device mode this reflects state Parallel Port Interrupt. parallel port interrupt asserted INTA#. MIO1 Status (LCC[6:5]=`00'). This reflects state internal MIO[1]. internal MIO[1] reflects non-inverted inverted state MIO1 pin.2 Function Power-down Interrupt (LCC[6:5] `00'). this mode this sticky bit. When set, indicates power-down request issued Function would normally have asserted interrupt set. Reading this clears MIO[10:2] Status. These bits reflect state internal MIO[10:2]. internal MIO[10:2] reflect non-inverted inverted state MIO[10:2] pins respectively.2 Reserved. Returns `X'. UART Interrupt Mask. When these bits enable each internal UART assert interrupt respectively. When cleared (=0) they prevent respective UART from asserting interrupt.3 MIO[0] Interrupt Mask (When device mode When (=1) this enables MIO0 assert interrupt. When cleared (=0) prevents MIO0 from asserting interrupt.2 Parallel Port Interrupt Mask (When device mode =1). When (=1) this enables parallel port assert interrupt. When cleared (=0) prevents parallel port from asserting interrupt. MIO[1] Interrupt Mask (LCC[6:5]=`00'). When (=1) this enables MIO1 assert interrupt. When cleared (=0) prevents MIO1 from asserting interrupt.2 Function Power-down Interrupt Mask (LCC[6:5] `00'). When (=1) this enables power-down logic Function0 assert interrupt. When cleared (=0) prevents power-down logic Function from asserting interrupt. Interrupt Mask. When (=1) these bits enable each MIO[10:2] assert interrupt respectively. When cleared (=0) they prevent respective pins from asserting interrupt.2 Reserved Read/Write
EEPROM
Reset 0x0h
XXXh XXXh
14:6 19:16
30:22
Note Note
3FFh
GIS[3:0] inverse UIS[18], UIS[12], UIS[6] UIS[0] respectively. Systems that require local parallel port need read this register identify source interrupt long they read (offset 18h) register. returned value either direct state corresponding inverse configured Multi-purpose Configuration register `MIC' (offset 0x04). internal assert interrupt, inversion feature define each external interrupt defined active-low active-high, controlled register. When MIO[0] been set-up input output, this made generate interrupt when MIO[0] Interrupt Mask (bit (=1). This enables MIO[0] assert interrupt.
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When MIO[1] been set-up input output, this made generate interrupt when MIO[1] Interrupt Mask (bit (=1). This enables MIO[1] assert interrupt. Note UART Interrupt Mask register bits after hardware reset enable interrupt from internal UARTs. This will cater generic device-driver software that does access Local Configuration Registers. default setting UART Interrupt Mask bits changed using serial EEPROM. Note that even though default UART interrupts enabled this register, since after reset registers individual UARTs disables interrupts, interrupt will asserted after hardware reset. Interrupts Mask register bits after hardware reset enable interrupt from pins from boot default setting Interrupt Mask bits changed using serial EEPROM.
Note
Interrupts
field determine which any) interrupt used each function. programs system interrupt router logically connect this interrupt system-specific interrupt vector (IRQ). then writes this routing information Interrupt Line field function's configuration space. Device driver software must then hook interrupt using information Interrupt Line field. Interrupt status sources interrupt available using register Local Configuration Register set, which accessed using Memory accessed from both logical functions. This facility enables each function snoop interrupts asserted from other function regardless interrupt routing. interrupt from each UART channel enabled using register register that UART. interrupt enabled active, then device will drive interrupt low. Generic device driver software will register enable interrupts. OXuPCI954 offers additional interrupt masking ability using GIS[19:16] (see Section 5.4.8). internal UART channel assert interrupt interrupt enabled GIS[19:16]. interrupts enabled disabled individually using register Local configuration registers. When enabled, external device assert interrupt driving that pin. sense external interrupt pins (active-high active-low) defined register. parallel port also assert interrupt (but this will effectively disable MIO[0] interrupt).
Interrupts systems level-sensitive shared. There sources interrupts OXuPCI954, each UART channel from Multi-Purpose pins (MIO10 MIO0). parallel port MIO[0] share same interrupt status (GIS[4]). Power Management power-down interrupt internal UARTs (Function0) MIO[1] share status GIS[5]. local uses pins pass interrupts controller. interrupts routed interrupt pin, INTA# Both Function Function interrupts assert INTA# line. default routings modified writing Interrupt field configuration registers using serial EEPROM facility. example, disable interrupt pin, functional Interrupts only appear INTA line. Interrupt field normally considered hard-wired read-only value PCI. indicates system software which interrupt any) used function. interrupt only modified using serial EEPROM facility, card developers must invoke combination which violates specification. doubt, default routings should used. following table relates Interrupt field device used. Interrupt Device Used None INTA# Reserved
During system initialization process device configuration, system-specific software reads interrupt
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connector PME#
Power Management
PME#
OXuPCI954 compliant with Power Management Specification Revision 1.1. This indicated both functions their Power Management Capabilities Register (PMC), which defaults 6C02(h). Each logical function implements Power Management registers supports power states D3hot. power state supported functions. PME# generation from D3hot available, wakeup from D3cold supported. These features summarized following table. Power State State Supported PME# Generation Supported
PME# Isolator Circuitry
5.6.1
Power Management Function
Provided that necessary controls have been device's local configuration registers (LCC GIS), internal UARTs programmed issue powerdown requests and/or `wakeup' requests (power management events), function Function configured monitor activity serial channels, issue power-down interrupt when UARTs inactive interrupts pending both transmitters receivers idle). When serial channels indicating powerdown request, only then will internal power management circuitry wait period time programmed into Power-Down Filter Time. This time defined local configuration register, LCC[7:5]). powerdown requests remain valid this time (this means that serial channels still inactive) then OXuPCI954 will issue powerdown interrupt this function's interrupt pin, this option enabled. Alternatively, device driver poll function powerdown status field local configuration register GIS[5] determine powerdown request. powerdown filter stops UARTs from issuing many powerdown interrupts whenever UARTs activity intermittent. Upon power down interrupt, device driver change power-state device (function required. Note that power-state function only changed device driver point will OXuPCI954 change power state. powerdown interrupt merely informs device driver that this logical function ready power down. Before placing device into lower power states, driver must provide means function generate `wakeup' (power management) event. Whenever device driver changes function powerstate state device takes following actions: internal clock internal UARTs shut down. interrupts disabled regardless values contained registers. Access Memory BARs disabled. However, access configuration space still enabled.
uninitialized initialized D3hot D3cold Notes: PMSCR register indicates satisfy value requirements Power management accomplished handling power-down power-up ("power management event") requests. These asserted relevant function's interrupt PME# respectively. Each function assert PME# independently. Power-down requests defined Power Management specifications. They devicespecific features require custom device driver implementation. device driver either implement power-down itself special interrupt powerdown features offered device determine when function device ready power-down. worth noting that PME# can, certain cases, activate PME# signal when power removed from device. This will cause wake from Lowpower state D3(cold). ensure full cross-compatibility with system board implementations, isolator recommended (See diagram). Power Management capabilities required, PME# treated no-connect.
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device driver optionally assert/de-assert selected (design dependent) pins switch-off VCC, disable other external clocks, activate shut-down modes. device only issue wakeup request power management event, PME#) enabled this function's PME_En bit, bit-8 Power Management Register PMCSR. PME# assertion immediate does powerdown filter timer. operates even powerdown filter time disabled. Like powerdown, wakeup requests function generated serial channel. means generate wakeup events from these sources must prior placing this function into powerdown states (including setting PME_En bit). each UART, when device (function powerstate only activity serial channel's line (the trailing edge pulse) will generate wakeup event. When device (function power-state then wake-ups configurable. this case, change state modem line (which enabled 16C950specific mask bit) change state serial input line (again, enabled 16C950-specific mask bit) issue wake request PME# pin. worth noting that after hardware reset these mask bits cleared enable wake assertion from modem lines line when powerstate wake operation from requires least mask enabled, device driver example disable masks with exception Ring Indicator, only modem ring wake computer. case wake request from serial input line EXT_DATA_IN (from power state then clock that channel turned serial data framing maintained. When function issues wake request from serial channels, PME_Status this function's power management registers (PMCSR[15]) will set. This sticky which will only cleared writing While PME_En (PMCSR[8]) remains set, PME_Status will continue assert PME# inform device driver that power management wake event occurred. After wake event signaled, device driver expected return this function powerstate.
OXuPCI954
5.6.2
Power Management Function
Provided that necessary controls have been device's local configuration registers (MIC GIS), Multi_Purpose pins (MIO[10:3]) programmed issue powerdown requests only MIO[2] generate `wakeup' requests (power management events), function parallel port local function capable issuing powerdown requests power management events placed power state through power management involving pins. state pin(s) that issues powerdown request controlled register. This active high active low. This state same state that asserts function interrupt normal functionality. assertion pins will result function powerdown request being made immediately. There powerdown filtering time associated with function powerdown request issued function's interrupt pin, this option enabled. Upon power down interrupt, device driver change power-state device (function required. Note that power-state function only changed device driver point will OXuPCI954 change power state. powerdown interrupt merely informs device driver that this logical function ready power down. Before placing device into lower power states, driver must provide means function generate `wakeup' (power management) event. Whenever device driver changes function powerstate state device takes following actions: Parallel port placed power mode. Local function placed power mode. interrupts disabled regardless values contained registers. Access Memory BARs disabled. However, access configuration space still enabled. Function only issue wakeup request (power management event) enabled this function's PME_En bit, Power Management Register, PMCSR[8]. Wakeup requests function only generated Multi_Purpose MIO[2]. Prior placing this function into powerdown states wakeup events from this source must enabled.
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state MIO[2] that results wakeup requests determined settings local configuration register MIC. soon correct logic invoked than power management event (wakeup) asserted. PME# event immediate. When function issues wake request, PME_Status this function's power management LCC[6:5] GIS[21] Power-down Filter Time
OXuPCI954
registers (PMCSR[15]) will set. This sticky which will only cleared writing While PME_En (PMCSR[8]) remains set, PME_Status will continue assert PME# inform device driver that power management wake event occurred. After wake event signaled, device driver expected return this function power-state. Operation Function power-down interrupt disabled. MIO[1] assert interrupt GIS[21] set. Function power-down interrupt disabled. GIS[5] reflects state internal power-down mode polling operation. MIO[1] interrupt disabled. Function power-down enabled. GIS[5] reflects state internal power-down mode. MIO[1] interrupt disabled.
Table Function (UARTs) Power Down Interrupt Settings LCC[7] MIC[5:4] MIO2 Rising MIO2 Falling Function1 PME_Status Remains unchanged Gets Remains unchanged Gets Remains unchanged
Table Function (Local Bus) Wake-up Configuration
5.6.3
Universal Voltage
OXuPCI954 fully compatible with both 3.3V interfaces. support universal voltage (3.3V 5V), buffers OXuPCI954 must supplied with power from (IO) pins connector. more details, refer selections Section 3.2.
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Unique Option Function
Note: When using EEPROM enable unique mode function Device function must also programmed 0x9504 EEPROM.
When `unique mode' option enabled EEPROM, setting local register MIC(26)=1. Base Address Register Region Function changes follows. Space Dword Numbers Description UART UART UART UART Local Registers Quad UARTs Local Registers Memory Space type bytes) bytes) bytes) bytes) bytes) Memory 4Kbytes
NOTE that `Unique Mode' only affects region Function0. Function affected maintains configuration device mode pins.
this case, BAR0 BAR3 reserve bytes space allow access registers UART UART respectively. Base Address local registers defined BAR4, BAR5 becomes Memory Base Address register both internal UARTs Local Registers. purposes device drivers recognizing this configuration, Device "9504" must reserved function EEPROM required change Device function "9504" additionally downloading into Configuration Zone function when unique mode enabled. Access UARTs Local Registers Memory Space: unique mode, serves Memory Base Address Register internal UARTs Local Registers. When accessing BAR5, address determines access UARTs Local Registers. With fields define which UART access, fields define which UART register access. With fields define BYTE offset local registers; 00000b register, 00100h register. both cases, fields utilized zeros. This because DWORD used hold single byte Memory Space.
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INTERNAL OX16C950 UARTS
Each four UART channels OXuPCI954 operates individually OX16C950 high-performance serial port. Each channel full registers, share common clock FIFOSEL pin. After device reset, common configuration state loaded into four channels, after this time each operated individually through 8-byte block addressable space.
Operation Mode Selection
Each channel backward compatible with 16C450, 16C550, 16C654 16C750 UARTs. operation ports depends number mode settings, which referred throughout this section. modes, conditions corresponding FIFO depth tabulated below: UART Mode Extended 9501 FIFO size FCR[0] Enhanced mode (EFR[4]=1) FCR[5] (guarded with LCR[7] FIFOSEL
Note mode configuration identical configuration
Table UART Mode Configuration increased writing FCR[5]. Note that access FCR[5] protected LCR[7]. i.e., FCR[5], software should first LCR[7] temporarily remove guard. Once FCR[5] set, software should clear LCR[7] normal operation. 16C750 additional features available long UART into Enhanced mode; i.e. ensure EFR[4] `0'. These features are: Deeper FIFOs Automatic RTS/CTS out-of-band flow control Sleep mode
6.1.1
Mode
After hardware reset, FIFO Control Register (`FCR') cleared, hence UARTs compatible with 16C450. transmitter receiver FIFOs (referred `Transmit Holding Register' `Receiver Holding Register' respectively) have depth one. This referred `Byte mode'. When FCR[0] cleared, other mode selection parameters ignored.
6.1.2
Mode
Connect FIFOSEL GND. After hardware reset, writing FCR[0] will increase FIFO size providing compatibility with 16C550 devices.
6.1.5
Mode
6.1.3
Extended Mode
Connect FIFOSEL VDD. Writing FCR[0] will increase FIFO size 128, thus providing device with deep FIFOs.
6.1.4
Mode
UART compatible with 16C650 when EFR[4] set, i.e. device Enhanced mode. software drivers usually device Enhanced mode, running drivers UART channels will result compatibility with deep FIFOs, long FCR[0] set. This regardless state FIFOSEL pin. Note that emulation mode OXuPCI954 provides 128-deep FIFOs rather than provided legacy 16C654.
compatibility with 16C750, connect FIFOSEL GND. Writing FCR[0] will increase FIFO size similar fashion 16C750, FIFO size further DS-0058 External-Free Release Page
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Enhanced (650) mode device following features available over those provided generic 550. (Note: some these similar those provided mode, enabled using different registers.) Deeper FIFOs Sleep mode Automatic in-band flow control Special character detection Infra-red "IrDA-format" transmit receive mode Transmit trigger levels Optional clock prescaler
OXuPCI954
trigger levels enabled when ACR[5] where bits ignored. Then arbitrary trigger levels defined RTL, TTL, registers (see Section 6.11). Additional Status Register (`ASR') offers flow control status local remote transmitters. FIFO levels readable using registers. UART flexible prescaler capable dividing system clock value between 31.875 steps 0.125. divides system clock arbitrary value "M+N/8" format, where 3-bit binary numbers programmed CPR[7:3] CPR[2:0] respectively. This arrangement offers great deal flexibility when choosing input clock frequency synthesize arbitrary baud rates. default division value provide backward compatibility with 16C650 devices. user apply external clock transmitter receiver DSR# respectively. transmitter clock instead asserted DTR# pin. external clock options selected through register (offset 0x02 ICR). also possible define over-sampling rate used transmitter receiver clocks. 16C450/16C550 compatible devices employ over-sampling, where there clock cycles bit. However, UART channels employ over-sampling rate from programming register. This allows data rates increased 460.8 Kbps using 1.8432 clock, Mbps using clock. default value after reset this register 0x00, which corresponds cycle sampling clock. Writing 0x01, 0x02 0x03 will also result cycle sampling clock. program value value from necessary write this value into i.e. device cycle sampling clock would necessary write 0x0D TCR. further information, Section 6.10.3. UARTs also offer 9-bit data frames multi-drop industrial applications.
6.1.6
Mode
additional features offered mode generally only apply when UART Enhanced mode (EFR[4]='1'). Provided FCR[0] set, Enhanced mode FIFO size regardless state FIFOSEL. Note that mode configuration identical that mode, however additional specific features enabled using Additional Control Register `ACR' (see Section 6.11.3). addition larger FIFOs higher baud rates, enhancements mode over emulation mode are: Selectable arbitrary trigger levels receiver transmitter FIFO interrupts Improved automatic flow control using selectable arbitrary thresholds DSR#/DTR# automatic flow control Transmitter receiver optionally disabled Software reset device Readable FIFO fill levels Optional generation RS-485 buffer enable signal Four-byte device identification (0x16C9500A) Readable status automatic in-band out-ofband flow control External clock modes (see Section 6.10.4) Flexible "M+N/8" clock prescaler (see Section 6.10.2) Programmable sample clock allow data rates Mbps (see Section 6.10.3). 9-bit data mode Readable register
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Register Description Tables
Each UART accessed through 8-byte block space through memory space). Since there more than registers, mapping also dependent state Line Control Register `LCR' Additional Control Register `ACR': LCR[7]=1 enables divider latch registers DLM. specifies data format used both transmitter receiver. Writing 0xBF unused format) enables access compatible register set. Writing this value will LCR[7] leaves LCR[6:0] unchanged. Therefore, data format transmitter receiver data affected. Write desired value exit from this selection. ACR[7]=1 enables read access specific status registers. ACR[6]=1 enables read access Indexed Control Register (ICR) registers described page
Register Name 650/950 Mode 550/750 Mode mode mode mode 550/750 Mode 650/950 Mode Normal 9-bit data mode Address interrupt mask interrupt mask
Data transmitted Data received Special Char. Sleep Detect mode Alternate Unused sleep mode Trigger Trigger Level Level Trigger FIFO Unused Level Size Unused FIFOs enabled Divisor latch access break Interrupt priority (Enhanced mode) Force parity Flow Control XON-Any Empty even parity Enable Internal Loop Back Break Parity enable Modem interrupt mask Stat interrupt mask THRE interrupt mask RxRDY interrupt mask
Trigger Enable
Flush
Flush
Enable FIFO
Interrupt priority (All modes) Number stop bits
Interrupt pending Data length
Unused Baud prescale Data Error IrDA mode Empty
OUT2 (Int
OUT1
Framing Error
Parity Error
Overrun Error
RxRDY
Normal 9-bit data Unused mode data Additional Standard Registers These registers require divisor latch access (LCR[7]) Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte)
data Delta Trailing edge Temporary data storage register Indexed control register offset value bits
Delta
Delta
Table Standard Compatible Registers DS-0058 External-Free Release Page
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Register Name XON1 9-bit mode XON2 9-bit mode XOFF1 9-bit mode XOFF2 9-bit mode
Address
access these registers must 0xBF Special Enhance In-band flow control mode flow Flow char mode control control detect Character Special character Character Special Character XOFF Character Special character XOFF Character Special character
Table Compatible Registers
Register Name 1,6,7 3,8,9
Address
Idle
FIFO size
FIFOSEL
Remote Disabled
Disabled
Special Char Detect Number characters receiver FIFO
Number characters transmitter FIFO Data read/written depends value written prior access this register (see Table
Table Specific Registers
Register access notes:
Note Requires LCR[7] Note Requires ACR[7] Note Requires that last value written 0xBF. Note read this register ACR[7] must Note read this register ACR[6] must Note Requires ACR[7] Note Only bits this register written. Note read this register ACR[6] must Note This register acts window through which read write registers Indexed Control Register set.
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Register Name
Offset 0x00
Additional Status Enable
Indexed Control Register definition Read Trigger control Enable Level Enable
RS485_DLYEN RS485_DLYCNT
0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0X0F 0X10 0x12 0x13 0x14 0x15
FCR[7] Mode Unused Unused Unused Unused
Auto Disable Disable Flow Control Enable "integer" part "fractional" part clock prescaler clock prescaler Unused N-times clock selection bits [3:0] BDOUT Receiver Select Mode Clock Sel[1:0] Transmitter Interrupt Trigger Level (0-127) Receiver Interrupt Trigger Level (1-127) Automatic Flow Control Lower Trigger Level (0-127) Automatic Flow Control Higher Trigger level (1-127) Hardwired byte (0x16) Hardwired byte (0xC9) Hardwired byte (0x50) Hardwired revision byte (0x12) Writing 0x00 this register will reset UART (except register) SChar SChar SChar SChar Modem Trailing wakeup Wakeup edge Wakeup disable Disable disable disable FCR[5] FCR[4] FCR[3] FCR[2]
Unused FCR[6]
9th-bit Int. Wakeup disable FCR[1]
Enable Wakeup disable FCR[0] Good data status
Hardwired Port Index 0x00, 0x01, 0x02, 0x03 according which UART Res. Res. Invert Invert Invert Unused Write Write internal internal signal clock clock Unused RS-DEL RS485 Delay Count RS485 Delay Phase Count
Table Indexed Control Register
Note offset column indicates value that must written into prior reading writing Indexed Control Registers ICR. Offset values listed table reserved future must used.
read write Indexed Controlled Registers following procedure: Writing registers: Ensure that last value written 0xBF (reserved compatible register access value). Write desired offset (address 111b). Write desired value (address 101b).
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Reading from registers: Ensure that last value written 0xBF (see above). Write 0x00 offset select ACR. (ICR read enable) writing x1xxxxxxb address 101b. Ensure that other bits changed. (Software drivers should keep copy contents elsewhere since reading involves overwriting ACR!). Write desired offset (address 111b). Read desired value from (address 101b). Write 0x00 offset select ACR. Clear writing x0xxxxxxb ICR, thus enabling access standard registers again.
OXuPCI954
6.3.1
UART Reset Configuration
Hardware Reset 6.3.2 Software Reset
After hardware reset, writable registers reset 0x00, with following exceptions: DLL, which reset 0x01. CPR, which reset 0x20. state read-only registers following hardware reset follows: Indeterminate 00000002 00000002 0x60, signifying that both transmitter transmitter FIFO empty MSR[3:0]: 00002 MSR[7:4]: Dependent modem input lines DCD, respectively ISR[7:0]: 0x01, i.e. interrupts pending ASR[7:0]: 1xx000002 reset state output signals tabulated below: Signal SOUT RTS# DTR# Reset state Inactive High Inactive High Inactive High RHR[7:0]: RFL[6:0]: TFL[6:0]: LSR[7:0]:
additional feature available OX16C950 UART software resetting serial channel. This command same effect single channel hardware reset except does reset clock source selections (i.e. register). reset UART write 0x00 Channel Software Reset register `CSR'.
Table Output Signal Reset State
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Transmitter Receiver FIFOs
Byte mode FIFO mode. This will return zero after clearing FIFOs. FCR[2]: Flush logic change. logic Flushes contents THR, same manner FCR[1] does RHR.
Both transmitter receiver have associated holding registers (FIFOs), referred transmitter holding register (THR) receiver holding register (RHR) respectively. normal operation, when transmitter finishes transmitting byte will remove next data from proceed transmit empty, will wait until data written into empty last character being transmitted been completed (i.e. transmitter shift register empty) transmitter said idle. Similarly, when receiver finishes receiving byte, will transfer bottom RHR. full, overrun condition will occur (Section 6.5.3). Data written into bottom queue read from queue completely asynchronously operation transmitter receiver. size FIFOs dependent setting register. When Byte mode, these FIFOs only accept byte time before indicating that they full; this compatible with 16C450. When FIFO mode, size FIFOs either (compatible with 16C550) 128. Data written when full lost. Data read from when empty invalid. empty full status FIFOs indicated Line Status Register `LSR' (see Section 6.5.3). Interrupts generated when UART ready data transfer to/from FIFOs. number items each FIFO also read back from transmitter FIFO level (TFL) receiver FIFO level (RFL) registers (see Section 6.11.2).
Trigger levels:
FCR[3]: trigger level enable logic Transmit trigger levels enabled logic Transmit trigger levels disabled When FCR[3]=0, transmitter trigger level always thus ignoring FCR[5:4]. Alternatively, 950-mode trigger levels using ACR[5]. FCR[5:4]: Compatible trigger levels 450, extended modes: transmitter interrupt trigger levels FCR[5:4] ignored. mode: mode transmitter interrupt trigger levels following values: FCR[5:4] Transmit Interrupt Trigger level
Table Transmit Interrupt Trigger Levels These levels only apply when Enhanced mode when FCR[3] set, otherwise trigger level transmitter empty interrupt will generated enabled) falls below trigger level. Mode: compatible mode, transmitter trigger level FCR[4] unused FCR[5] defines FIFO depth follows: FCR[5]=0: FIFO size bytes. FCR[5]=1: FIFO size bytes. non-Enhanced mode when FIFOSEL low, FCR[5] writable only when LCR[7] set. Note that Enhanced mode, FIFO size increased bytes when FCR[0] set. Page
6.4.1
FIFO Control Register `FCR'
FIFO setup:
FCR[0]: Enable FIFO mode logic Byte mode. logic FIFO mode. This should enabled before setting FIFO trigger levels. FCR[1]: Flush logic change. logic Flushes contents This only operative when already FIFO mode. automatically flushed whenever changing between DS-0058
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mode: Setting ACR[5]=1 enables 950-mode trigger levels using register (see Section 6.11.4), FCR[5:4] ignored.
OXuPCI954
mode: similar fashion transmitter trigger levels, setting ACR[5]=1 enables 950-mode receiver trigger levels. FCR[7:6] ignored. [7:6] Mode Ext.
FIFO Size
trigger levels:
FCR[7:6]: Compatible Trigger levels 450, 550, extended 550, modes: receiver FIFO trigger levels defined using FCR[7:6]. interrupt trigger level upper flow control trigger level where appropriate defined table below. defines lower flow control trigger level. Separate upper lower flow control trigger levels introduce hysteretic element in-band out-of-band flow control (see Section 6.9). Byte mode (450-mode) trigger levels
FIFO Size
FIFO Size
Table Compatible Receiver Trigger Levels receiver data interrupt will generated enabled) Receiver FIFO Level (`RFL') reaches upper trigger level.
6.5.1
Line Control Status
False Start Detection
affected. Write desired value exit from this selection. LCR[1:0]: Data length LCR[1:0] Determines data length serial characters. Note that these values ignored 9-bit data framing mode, i.e. when NMR[0] set. LCR[1:0] Data length bits bits bits bits
falling edge start bit, receiver will wait re-synchronies receiver's sampling clock onto centre start bit. start valid line still this mid-bit sample receiver will proceed read data character. Verifying start prevents noise generating spurious character generation. Once first stop been sampled, received data transferred receiver will then wait transition (signifying next start bit). receiver will continue receiving data even full receiver been disabled (see Section 6.11.3) order maintain framing synchronization. only difference that received data does transferred RHR.
Table Data Length Configuration LCR[2]: Number stop bits LCR[2] defines number stop bits serial character. LCR[2] Data Length 5,6,7,8 6,7,8 Stop Bits
6.5.2
Line Control Register `LCR'
specifies data format that common both transmitter receiver. Writing 0xBF enables access EFR, XON1, XOFF1, XON2 XOFF2, registers. This value (0xBF) corresponds unused data format. Writing value 0xBF will LCR[7] leaves LCR[6:0] unchanged. Therefore, data format transmitter receiver data
Table Stop Number Configuration
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LCR[5:3]: Parity type selected parity type will generated during transmission checked receiver, which produce parity error result. 9-bit mode parity disabled LCR[5:3] ignored. LCR[5:3] Parity type parity parity Even parity Parity forced Parity forced
OXuPCI954
Parity error flag will when data item error cleared following read LSR. 9-bit mode LSR[2] longer flag corresponds ninth received data RHR. LSR[3]: Received data framing error logic framing error. logic Data been received with invalid stop bit. This status cleared same manner LSR[2]. When framing error occurs, UART will re-synchronies assuming that error sampling start next data item. LSR[4]: Received break error logic receiver break error. logic receiver received break. break condition occurs when line goes (normally signifying start bit) stays throughout start, data, parity first stop bit. (Note that line sampled rate). zero character with associated break flag will transferred receiver will then wait until line returns high. LSR[4] break flag will when this data item gets cleared following read LSR. LSR[5]: empty logic Transmitter FIFO (THR) empty. logic Transmitter FIFO (THR) empty. LSR[6]: Transmitter empty logic transmitter idle logic empty transmitter completed character shift register idle mode. (I.e. whenever transmitter shift register both empty.) LSR[7]: Receiver data error logic Either there receiver data errors FIFO cleared read LSR. logic least parity error, framing error break indication FIFO. mode LSR[7] permanently cleared, otherwise this will when erroneous character transferred from receiver RHR. cleared when read. Note that 16C550 this only cleared when erroneous data removed from FIFO. 9-bit data framing mode parity permanently disabled, this affected LSR[2].
Table Parity Configuration LCR[6]: Transmission break logic Break transmission disabled. logic Forces transmitter data output SOUT alert communication terminal, send zeros IrDA mode. responsibility software driver ensure that break duration longer than character period recognized remotely break rather than data. LCR[7]: Divisor latch enable logic Access registers disabled. logic Access registers enabled.
6.5.3
Line Status Register `LSR'
This register provides status data transfer CPU. LSR[0]: data available logic empty: data available logic empty: data available read. LSR[1]: overrun error logic overrun error. logic Data received when full. overrun error occurred. error flagged when data would normally have been transferred RHR. LSR[2]: Received data parity error logic parity error normal mode ninth received data 9-bit mode. logic Data been received that have correct parity normal mode ninth received data 9-bit mode.
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Interrupts Sleep Mode
9-bit data mode, receiver detect four special characters programmed Special Character Registers (see page 39). When IER[5] set, level interrupt asserted when receiver character matches values programmed. 650/950 modes (non-9-bit data framing): logic Disable special character receive interrupt. logic Enable special character receive interrupt. 16C650 compatible mode when device Enhanced mode (EFR[4]=1), this enables detection special characters. enables both detection XOFF characters (when in-band flow control enabled EFR[3:0]) detection XOFF2 special character (when enabled EFR[5]). mode (non-9-bit data framing): logic Disable alternate sleep mode. logic Enable alternate sleep mode whereby internal clock channel switched off. 16C750 compatible mode (i.e. non-Enhanced mode), this used alternate sleep mode same effect IER[4]. IER[6]: interrupt mask logic Disable interrupt. logic Enable interrupt. This enable only operative Enhanced mode (EFR[4]=1). non-Enhanced mode, interrupt permanently enabled IER[7]: interrupt mask logic Disable interrupt. logic Enable interrupt. This enable only operative Enhanced mode (EFR[4]=1). non-Enhanced mode, interrupt permanently enabled.
serial channel interrupts asserted INTA# pin. interrupts enabled disabled using register interrupt mask (see Section 5.4.8) register. Unlike generic 16C550 devices, interrupt disabled using implementation-specific MCR[3].
6.6.1
Interrupt Enable Register `IER'
Serial channel interrupts enabled using Interrupt Enable Register (`IER'). IER[0]: Receiver data available interrupt mask logic Disable receiver ready interrupt. logic Enable receiver ready interrupt. IER[1]: Transmitter empty interrupt mask logic Disable transmitter empty interrupt. logic Enable transmitter empty interrupt. IER[2]: Receiver status interrupt Normal mode: logic Disable receiver status interrupt. logic Enable receiver status interrupt. 9-bit data mode: logic Disable receiver status address interrupt. logic Enable receiver status address interrupt. 9-bit mode (i.e. when NMR[0] set), reception character with address-bit (i.e. ninth bit) generate level interrupt IER[2] set. IER[3]: Modem status interrupt mask logic Disable modem status interrupt. logic Enable modem status interrupt. IER[4]: Sleep mode logic Disable sleep mode. logic Enable sleep mode whereby internal clock channel switched off. Sleep mode described Section 6.6.4. IER[5]: Special character interrupt mask alternate sleep mode 9-bit data framing mode: logic Disable received special character interrupt. logic Enable received special character interrupt.
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6.6.2
Interrupt Status Register `ISR'
Level
Receiver data available interrupt (ISR[5:0]='000100'): This interrupt active whenever receiver FIFO level above interrupt trigger level.
source highest priority interrupt pending indicated contents Interrupt Status Register `ISR'. There nine sources interrupt levels priority highest) shown Table Level Interrupt source interrupt pending Receiver status error Address-bit detected 9-bit mode Receiver data available Receiver time-out Transmitter empty Modem status change In-band flow control XOFF Special character (XOFF2) Special character 9-bit mode change state ISR[5:0]
note
Level
Receiver time-out interrupt (ISR[5:0]='001100'): receiver time-out event, which cause interrupt, will occur when following conditions true: UART FIFO mode There data RHR. There been read period time greater than time-out period. There been data written into period time greater than time-out period. time-out period four times character period (including start stop bits) measured from centre first stop last data item received. Reading first data item clears this interrupt.
000001 000110 000100 001100 000010 000000 010000
100000
Level
Transmitter empty interrupt (ISR[5:0]='000010'): This interrupt when transmit FIFO level falls below trigger level. cleared read level interrupt writing more data that trigger level exceeded. Note that when 16C950 mode trigger levels enabled (ACR[5]=1) transmitter trigger level zero selected (TTL=0x00), transmitter empty interrupt will only asserted when both transmitter FIFO transmitter shift register empty SOUT line returned idle marking state.
Table Interrupt Status Identification Codes
Note1: Note2: Note3: ISR[0] indicates whether interrupts pending. Interrupts priority levels cannot occur unless UART Enhanced mode. ISR[5] only used modes. mode, when FIFO size when FIFO size 128. other modes permanently
ISR[6] ISR[7] indicated whether FIFOs enabled. When enable FIFOs both bits when either 128, note they also mirror fcr[0].
Level
Modem change interrupt (ISR[5:0]='000000'): This interrupt modem change flag (MSR[0], MSR[1], MSR[2] MSR[3]) becoming active changes input modem lines. This interrupt cleared following read MSR.
6.6.3 Level
Interrupt Description
Receiver status error interrupt (ISR[5:0]='000110'): Normal (non-9-bit) mode: This interrupt active whenever LSR[1], LSR[2], LSR[3] LSR[4] set. These flags cleared following read LSR. This interrupt masked with IER[2]. 9-bit mode: This interrupt active whenever LSR[1], LSR[2], LSR[3] LSR[4] set. receiver error interrupt LSR[1], LSR[3] LSR[4] masked with IER[3]. `address-bit' received interrupt masked with NMR[1]. software driver differentiate between receiver status error received address-bit (ninth data bit) interrupt examining LSR[1] LSR[7]. 9-bit mode LSR[7] only when LSR[3] LSR[4] affected LSR[2] (i.e. ninth data bit).
Level
Receiver in-band flow control (XOFF) detect interrupt, Receiver special character (XOFF2) detect interrupt, Receiver special character interrupt Ninth interrupt 9-bit mode (ISR[5:0]='010000'): level interrupt only occur Enhanced-mode when following conditions met: valid XOFF character received while in-band flow control enabled. received character matches XOFF2 while special character detection enabled, i.e. EFR[5]=1. received character matches special character 9-bit mode (see Section 6.11.9). cleared read level interrupt.
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Level
changed interrupt (ISR[5:0]='100000'): This interrupt whenever CTS# RTS# pins changes state from high. cleared read level interrupt.
UART loopback mode (MCR[4]=0). Changes modem input lines have been acknowledged (i.e. MSR[3:0]=0000). interrupts pending.
6.6.4
Sleep Mode
channel into sleep mode, following conditions must met: Sleep mode enabled (IER[4]=1 650/950 modes, IER[5]=1 mode): transmitter idle, i.e. transmitter shift register FIFO both empty. high. receiver idle. receiver FIFO empty (LSR[0]=0).
read IER[4] IER[5] written that instead) shows whether power-down request successful. UART will retain programmed state whilst power-down mode. channel will automatically exit power-down mode when conditions becomes false. woken manually clearing IER[4] IER[5] alternate sleep mode enabled). Sleep mode operation available IrDA mode.
6.7.1
Modem Interface
Modem Control Register `MCR'
OUT2#) in-active (high), receiver inputs SIN, CTS#, DSR#, DCD#, disabled. Internally transmitter output connected receiver input DTR#, RTS#, OUT1# OUT2# connected modem status inputs DSR#, CTS#, DCD# respectively. this mode, receiver transmitter interrupts fully operational. modem control interrupts also operational, interrupt sources lower four bits Modem Control Register instead four modem status inputs. interrupts still controlled IER. MCR[5]: Enable XON-Any Enhanced mode enable out-of-band flow control non-Enhanced mode 650/950 (Enhanced) modes: logic XON-Any disabled. logic XON-Any enabled. Enhanced mode (EFR[4]=1), this enables XonAny operation. When Xon-Any enabled, received data will accepted valid (see in-band flow control, Section 6.9.3).
MCR[0]: logic Force DTR# output inactive (high). logic Force DTR# output active (low). Note that DTR# used automatic out-of-band flow control when enabled using ACR[4:3] (see Section 6.11.3). MCR[1]: logic Force RTS# output inactive (high). logic Force RTS# output active (low). Note that RTS# used automatic out-of-band flow control when enabled using EFR[6] (see Section 6.9.4). MCR[2]: OUT1 Note OUT1# bonded OXuPCI954. logic Force OUT1# output when loopback mode disabled. logic Force OUT1# output high. MCR[3]: OUT2/Internal interrupt enable Note OUT2# bonded OXuPCI954. logic Force OUT2# output when loopback mode disabled. logic Force OUT2# output high. MCR[4]: Loopback mode logic Normal operating mode. logic Enable local loop-back mode (diagnostics). local loop-back mode, transmitter output (SOUT) four modem outputs (DTR#, RTS#, OUT1# DS-0058
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(normal) mode: logic CTS/RTS flow control disabled. logic CTS/RTS flow control enabled. non-enhanced mode, this enables CTS/RTS outof-band flow control. MCR[6]: IrDA mode logic Standard serial receiver transmitter data format. logic Data will transmitted received IrDA format. This function only available Enhanced mode. requires clock function correctly. MCR[7]: Baud rate prescaler select logic Normal (divide baud rate generator prescaler selected. logic Divide-by-"M+N/8" baud rate generator prescaler selected. where programmed (ICR offset 0x01). After hardware reset, defaults 0x20 (divide-by-4) MCR[7] reset. User writes this flag will only take effect Enhanced mode. Section 6.9.1.
OXuPCI954
6.7.2
Modem Status Register `MSR'
MSR[0]: Delta CTS# Indicates that CTS# input changed since last time read. MSR[1]: Delta DSR# Indicates that DSR# input changed since last time read. MSR[2]: Trailing edge Indicates that input changed from high since last time read. MSR[3]: Delta DCD# Indicates that DCD# input changed since last time read. MSR[4]: This complement CTS# input. equivalent (MCR[1]) internal loop-back mode. MSR[5]: This complement DSR# input. equivalent (MCR[0]) internal loop-back mode. MSR[6]: This complement input. internal loopback mode equivalent internal OUT1. MSR[7]: This complement DCD# input. internal loop-back mode equivalent internal OUT2.
6.8.1
Other Standard Registers
Divisor Latch Registers `DLL DLM'
Where divisor given (256 DLM). More flexible baud rate generation options also available. Section 6.10 details.
divisor latch registers used program baud rate divisor. This value between 65535 which input clock divided order generate serial baud rates. After hardware reset, baud rate used transmitter receiver given
6.8.2
Scratch Register `SPR'
Baudrate
InputClock Divisor
scratch register does affect operation rest UART used temporary data storage. register also used define offset value access registers Indexed Control Register set. more information Indexed Control registers Sections 6.11.
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OXuPCI954
Automatic Flow Control
EFR[3:2]: In-band transmit flow control mode When in-band transmit flow control enabled, XON/XOFF character(s) inserted into data stream whenever passes upper trigger level falls below lower trigger level respectively. automatic in-band flow control, must set. combinations software transmit flow control then selected programming EFR[3:2] follows: logic [00] In-band transmit flow control disabled. logic [01] Single character in-band transmit flow control enabled, using XON2 character XOFF2 XOFF character. logic [10] Single character in-band transmit flow control enabled, using XON1 character XOFF1 XOFF character. logic[11] value EFR[3:2] "11" reserved future should used. EFR[4]: Enhanced mode logic Non-Enhanced mode. Disables bits 4-7, bits 4-5, bits 4-5, bits inband flow control. Whenever this cleared, settings other bits ignored. logic Enhanced mode. Enables Enhanced mode functions. These functions include enabling bits 4-7, bits 4-5, bits 5-7. in-band flow control software driver must this first. this set, out-of-band flow control configured with bits 6-7; otherwise out-of-band flow control compatible with 16C750. EFR[5]: Enable special character detection logic Special character detection disabled. logic While Enhanced mode (EFR[4]=1), UART compares incoming receiver data with XOFF2 value. Upon correct match, received data will transferred level interrupt (XOFF special character) will asserted level interrupts enabled (IER[5] EFR[6]: Enable automatic flow control. logic flow control disabled (default). logic flow control enabled Enhanced mode (i.e. EFR[4] where RTS# will forced inactive high reaches upper flow control threshold. This will released when drops below lower threshold. 950-mode drivers should this enable flow control. Page
Automatic in-band flow control, automatic out-of-band flow control special character detection features used when Enhanced mode (flow control software compatible with 16C654). Alternatively, 750-compatible automatic out-of-band flow control enabled when non-Enhanced mode. mode, in-band out-ofband flow controls compatible with 16C654 with addition fully programmable flow control thresholds.
6.9.1
Enhanced Features Register `EFR'
Writing 0xBF enables access other Enhanced mode registers. This value corresponds unused data format. Writing 0xBF will LCR[7] leaves LCR[6:0] unchanged. Therefore, data format transmitter receiver data affected. Write desired value exit from this selection. Note: In-band transmit receive flow control disabled 9-bit mode. EFR[1:0]: In-band receive flow control mode When in-band receive flow control enabled, UART compares received data with programmed XOFF character(s). When this occurs, UART will disable transmission soon current character transmission complete. UART then compares received data with programmed character(s). When match occurs, UART will re-enable transmission (see Section 6.11.6). automatic in-band flow control, must set. combinations software receive flow control selected programming EFR[1:0] follows: logic [00] In-band receive flow control disabled. logic [01] Single character in-band receive flow control enabled, recognizing XON2 character XOFF2 XOFF character. logic [10] Single character in-band receive flow control enabled, recognizing XON1 character XOFF1 XOFF character. logic [11] behavior receive flow control dependent configuration EFR[3:2]. Single character in-band receive flow control enabled, accepting XON1 XON2 valid characters XOFF1 XOFF2 valid XOFF characters when EFR[3:2] "01" "10". EFR[1:0] should "11" when EFR[3:2] `00'. DS-0058
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EFR[7]: Enable automatic flow control. logic flow control disabled (default). logic flow control enabled Enhanced mode (i.e. EFR[4] where data transmission prevented whenever CTS# held inactive high. 950-mode drivers should this enable flow control. 750-mode driver should MCR[5] enable RTS/CTS flow control.
OXuPCI954
transmitter will re-enabled. received data will transferred RHR. When in-band transmit flow control enabled, will sampled whenever transmitter idle (briefly, between characters, when empty) XON/XOFF character will inserted into data stream needed. Initially, remote transmissions enabled hence ASR[1] clear. ASR[1] clear passed upper trigger level (i.e. above trigger level), XOFF will sent ASR[1] will set. ASR[1] falls below lower trigger level, will sent ASR[1] will cleared. transmit flow control disabled after XOFF been sent, will sent automatically.
6.9.2
Special Character Detection
Enhanced mode (EFR[4]=1), when special character detection enabled (EFR[5]=1) receiver matches received data with XOFF2, 'received special character' flag ASR[4] will level interrupt asserted, enabled IER[5]. This flag will cleared following read ASR. received status (i.e. parity framing) special characters does have valid these characters accepted valid matches.
6.9.4
Automatic Out-of-band Flow Control
6.9.3
Automatic In-band Flow Control
When in-band receive flow control enabled, UART will compare received data with XOFF1 XOFF2 characters detect XOFF condition. When this occurs, UART will disable transmission soon current character transmission complete. Status bits ISR[4] ASR[0] will set. level interrupt will occur enabled IER[5]). UART will then compare received data with XON1 XON2 characters detect condition. When this occurs, UART will re-enable transmission status bits ISR[4] ASR[0] will cleared. valid XON/XOFF characters will written into RHR. exception this rule occurs special character detection enabled XOFF2 character received that valid XOFF. this instance, character will written into RHR. received status (i.e. parity framing) XON/XOFF characters does have valid these characters accepted valid matches. When 'XON Any' flag (MCR[5]) set, received character accepted valid condition
Automatic RTS/CTS flow control selected different means, depending whether UART Enhanced non-Enhanced mode. When non-Enhanced mode, MCR[5] enables both flow control. When Enhanced mode, EFR[6] enables automatic flow control EFR[7] enables automatic flow control. This allows software compatibility with both 16C650 16C750 drivers. When automatic flow control enabled CTS# input becomes active, UART will disable transmission soon current character transmission complete. Transmission resumed whenever CTS# input becomes inactive. When automatic flow control enabled, RTS# will forced inactive when reaches upper trigger level will return active when falls below lower trigger level. automatic RTS# flow control ANDed with MCR[1] hence only operational when MCR[1]=1. This allows software driver override automatic flow control disable remote transmitter regardless setting MCR[1]=0 time. Automatic DTR/DSR flow control behaves same manner RTS/CTS flow control enabled ACR[3:2], regardless whether UART Enhanced mode.
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OXuPCI954
6.10 Baud Rate Generation
6.10.1 General Operation
UART contains programmable baud rate generator that capable taking clock input from 1.8432 dividing 16-bit divisor number from 65535 written into (MSB) (LSB) registers. addition this, clock prescaler register provided which further divide clock values range 31.875 steps 0.125. Also, further feature Times Clock Register `TCR' which allows sampling clock value between These clock options allow highly flexible baud rate generation capabilities from almost input clock frequency MHz). actual transmitter receiver baud rate calculated follows:
6.10.2 Clock Prescaler Register `CPR'
register located offset 0x01 ICR. prescaler divides system clock value range 7/8" steps 1/8. divisor takes form "M+N/8", where value defined CPR[7:3] value defined CPR[2:0]. prescaler by-passed prescaler value selected default when MCR[7] Note that since access MCR[7] restricted Enhanced mode only, EFR[4] should first then MCR[7] cleared required. higher baud rates higher frequency clock, e.g. 14.7456 MHz, 18.432 MHz, MHz, 60.0 MHz. flexible prescaler allows system designers clocks that integer multiples popular baud rates; when using non-standard clock frequency, compatibility with existing 16C550 software drivers maintained with minor software patch program on-board prescaler divide high frequency clock down 1.8432 MHz. Table following page gives prescaler values required operate UARTs compatible baud rates with various different crystal frequencies. Also given maximum available baud rates modes with
InputClock BaudRate Divisor prescaler
Where: Sample clock values defined TCR[3:0] Divisor Prescaler when MCR[7] else: where: CPR[7:3] (Integer part CPR[2:0] (Fractional part 0.000 0.875 After hardware reset, prescaler bypassed (set 0x00 (i.e. 16). Assuming this default configuration, following table gives divisors required programmed into registers order obtain various standard baud rates: DLM:DLL Divisor Word 0x0900 0x0300 0x0180 0x00C0 0x0060 0x0030 0x0018 0x000C 0x0006 0x0004 0x0003 0x0002 0x0001 Baud Rate (bits second) 1,200 2,400 4,800 9,600 19,200 28,800 38,400 57,600 115,200
6.10.3 Times Clock Register `TCR'
register located offset 0x02 ICR. 16C550 other compatible devices such 16C650 16C750 times (16x) over-sampling channel clock. over-sampling clock means that channel clock runs times selected serial rate. limits highest baud rate 1/16 system clock when using divisor latch value unity. However, 16C950 UART designed manner enable accept other multiplications rate clock. values from clock programmed long clock (oscillator) frequency error, stability jitter within reasonable parameters. Upon hardware reset reset 0x00 which means that clock will used, compatibility with 16C550 compatibles. maximum baud-rates available various system clock frequencies allowable values Page
Table Standard Port Baud Rate Divisors (assuming 1.8432 crystal) DS-0058
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indicated Table following page. These values bits-per-second (bps) that obtained divisor latch 0x01 Prescaler OXuPCI954 facility operate baud-rates Mbps normal mode. Table indicates value register corresponds number clock cycles bit. TCR[3:0] used program clock. TCR[7:4] unused will return "0000" read. TCR[3:0] 0000 0011 0100 1111 Clock Cycles 4-15
OXuPCI954
does require device mode although only drivers that have been written take advantage mode features will able access this register. Writing 0x01 will switch device into isochronous mode this explained following section. (TCR effect isochronous mode). 0x01, 0x10 0x11 written device will operate mode. Reading will always return last value that written irrespective mode operation.
Table Sample Clock Configuration Clock Frequency (MHz) 1.8432 7.3728 14.7456 18.432 32.000 33.000 40.000 50.000 60.000 value 0x08 0x20 0x40 0x50 (10) 0x8B (17.375) 0x8F (17.875) 0xAE (21.75) 0xD9 (27.125) 0xFF (31.875) Effective crystal frequency 1.8432 1.8432 1.8432 1.8432 1.8417 1.8462 1.8391 1.8433 1.8824 Error from 1.8432 0.00 0.00 0.00 0.00 0.08 0.16 0.22 0.01 2.13 Max. Baud rate with 115,200 460,800 921,600 1,152,000 2,000,000 2,062,500 2,500,000 3,125,000 3,750,000 Max. Baud rate with 460,800 1,843,200 3,686,400 4,608,000 8,000,000 8,250,000 10,000,000 12,500,000 15,000,000
Table Example clock options their associated maximum baud rates
Sampling Clock Value System Clock (MHz) 1.8432 7.372 14.7456 18.432
0x00 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0
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