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Volume Connected Media Processor Rev. March 2006 Philip


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PNX15xx Series Data Book
Volume
Connected Media Processor
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Connected Media Processor
Table Contents
Chapter Integrated Circuit Data
2.3.1 2.3.2
Introduction. Description
Boundary Scan Notice Circuit Summary Signal List Power List 1-19 Reference Voltage 1-20
PCIT5V type circuit 1-32
7.10 7.11 7.12 7.13
Timing Specification
1-32
Absolute Maximum Ratings 1-20 PNX15xx Series Operating Conditions 1-21
PNX1500 Device PNX1501 Device PNX1502 Device PNX1503 Device
1-21 1-22 1-22 1-23 1-23 1-24 1-24 1-24
5.4.1 5.4.2
Power Considerations 1-23
Power Supply Sequencing Leakage current Power Consumption Standby Power Consumption Power Consumption Typical Power Consumption Typical Applications1-24 Expected Maximum Currents
Reset 1-33 DRAM Interface 1-33 Interface 1-34 QVCP, FGPO Interfaces 1-36 FGPI Interfaces 1-37 10/100 Mode 1-38 10/100 RMII Mode 1-38 Audio Input Interface 1-39 Audio Output Interface 1-40 SPDIF Interface 1-41 Interface 1-42 GPIO Interface 1-43 JTAG Interface. 1-44
10.1 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 10.4
Package Outline 1-45 Ball Assignment 1-46 Board Design Guidelines 1-48
Power Supplies Decoupling 1-48 Analog Supplies. 1-49 Analog Supply 1-49 Core, VDDA, Analog Supply 1-49 SDRAM interface 1-50 Devices Require Termination? 1-51 What really want termination PNX1500?1-51 Package Handling, Soldering Thermal Properties1-52
1-25
DC/AC Characteristics 1-25
Input Clock Specification 1-26 SSTL_2 type Circuit 1-26 BPX2T14MCP Type Circuit 1-28 BPTS1CHP BPTS1CP Type Circuit 1-29 BPTS3CHP BPTS3CP Type Circuit 1-30 IPCHP IPCP Type Circuit 1-31 BPT3MCHDT5V BPT3MCHT5V Type Circuit1-31 IIC3M4SDAT5V IIC3M4SCLT5V type circuit1-32
Miscellaneous 1-52 Soft Errors Radiation 1-52 Ordering Information. 1-53
Chapter Overview
Introduction.
PNX15xx Series Functional Overview PNX15xx Series Features Summary
De-scrambler 2-12
7.5.1
Image Processing 2-12
Pixel Format 2-12 Video Input Processor 2-13 Memory Based Scaler 2-14 Drawing Engine 2-15 Quality Video Composition Processor 2-15 External Video Improvement Post Processing
PNX15xx Series Functional Block Diagram
System Resources.
System Reset System Booting Clock System Power Management Semaphores Interface
Audio processing Input/Output
2-17
Audio Processing 2-17 Audio Inputs Outputs 2-17
System Memory
General Purpose Interfaces 2-18
Video/Data Input Router 2-18 Video/Data Output Router 2-19 Fast General Purpose Input 2-20 Fast General Purpose Output 2-21
Main Memory Interface Flash
TM3260 VLIW Media Processor Core 2-10 MPEG Decoding 2-12
2-12
Peripheral Interface 2-21
Koninklijke Philips Electronics N.V. 2006. rights reserved.
PNX15XX_SER_3
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
10.3 10.3.1 10.3.2 10.3.3 10.4 PCI-2.2 XIO-16 Interface Unit 2-23 Capabilities 2-23 Simple Peripheral Capabilities (`XIO-8/16') 2-24 Drive Interface 2-26 10/100 Ethernet 2-26
10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.2
GPIO General Purpose Software Flexible Serial Interface2-21 software 2-21 timestamping 2-22 event sequence monitoring signal generation
2-22
GPIO reset value 2-22 Remote Control Receiver Blaster 2-23
Endian Modes 2-26 System Debug 2-27
Chapter System Chip Resources
2.4.1
Introduction. System Memory
View View. View System View Programmable Apertures DRAM Aperture Control MMIO Registers Aperture Boundaries
Usage Notes 3-10 Semaphore MMIO Registers. 3-11
6.3.1
System Related Information TM3260 3-12
Interrupts 3-12 Timers 3-14 System Parameters TM3260 3-15 TM3260 System Parameters MMIO Registers
System Principles
Module Powerdown bit. System Module MMIO registers
Video Input Output Routers 3-16
MMIO Registers Input/Output Video/Data Router3-17
Miscellaneous 3-26
Miscellaneous System MMIO registers 3-27
System Endian Mode
System Endian Mode MMIO registers
System Semaphores
Semaphore Specification Construction 12-bit Master Semaphore 3-10
System Registers Summary 3-29 Simplified Internal Infrastructure 3-30 MMIO Memory 3-31 References 3-32
Chapter Reset
2.2.1 2.2.2
Introduction. Functional Description
RESET_IN_N POR_IN_N? watchdog Timer Interrupt Mode Interrupt Mode Software Reset
External Software Reset
Timing Description
Hardware Timing Software Timing
Register Definitions References 4-10
Chapter Clock Module
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5
PNX15XX_SER_3
Introduction. Functional Description
Modules their Clocks Clock Sources PNX15xx Series. Specification Clock Dividers 5-10 Clocks 5-11 Assignment Summary 5-11 External Clocks 5-11 Clock Control Logic 5-13 Bypass Clock Sources 5-14 Power-up Reset sequence 5-15 Clock Stretching 5-15 Clock Frequency Determination 5-16 Power Down 5-17
2.8.1 2.10 2.11 2.11.1 2.11.2 2.12 2.12.1 2.12.2 2.12.3 2.12.4 2.12.5 2.12.6
Wake-Up from Power Down 5-17 Clock Detection 5-18 Clocks 5-19 GPIO Clocks 5-20 Setting GPIO[14:12]/GCLOCK[2:0] Clock Outputs5-20 GPIO[6:4]/CLOCK[6:4] Clock Outputs 5-20 Clock Block Diagrams 5-20 TM3260, QVCP clocks 5-21 Clock Dividers 5-23 Internal PNX15xx Series Clock from Dividers 5-24 GPIO Clocks 5-26 External Clocks 5-27 SPDO 5-31
Registers Definition 5-31
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Registers Description 5-34
Registers Summary 5-31
Chapter Boot Module
2.2.1 2.2.2 2.2.3
Introduction. Functional Description
Boot Modes Boot Module Operation MMIO Interface Master Boot Control/State Machine Boot Command Language
3.2.1
Specifics Boot From Flash Memory Devices6-10 Binary Sequence Section Flash Boot
6-12
Specifics Host-Assisted Mode 6-12
Boot From EEPROM
6-14
3.1.1
PNX15xx Series Boot Scripts Content.
Common Behavior Binary Sequence Common Boot Script
External Boot EEPROM Types 6-14 Boot Commands Endian Mode 6-15 Details Operation 6-15
References 6-16
Chapter PCI-XIO Module
Introduction. Functional Description
Document title variable Block Level Diagram Architecture
4.3.1 4.3.2 4.3.3 4.3.4
Application Notes 7-19
Interface 7-19 System Memory Interface, 7-19 Interface 7-20 Motorola Interface 7-20 NAND-Flash Interface 7-20 Flash Interface 7-20 Interface 7-21 Endian Support 7-21 General Notes 7-21
3.1.1 3.1.2 3.1.3 3.1.4
Operation
Overview NAND-Flash Interface Operation Motorola Style Interface 7-10 Flash Interface 7-12 Description 7-13 Interrupt Enable Register 7-18
Register Descriptions 7-21
Register Summary 7-22
Chapter General Purpose Input Output Pins
2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.3.1 2.3.2 2.4.1
Introduction. Functional Description
GPIO: Basic Behavior GPIO Mode settings GPIO Data Settings MMIO Registers GPIO Status Reading GPIO: Event Monitoring Mode Timestamp Reference clock Timestamp format. GPIO: Signal Monitoring Pattern Generation Modes8-7 Signal Monitoring Mode. Signal Pattern Generation Mode 8-11 GPIO Error Behaviour 8-14 GPIO Frequency Restrictions. 8-15 GPIO Clock Pins 8-17 GPIO Interrupts 8-17 Timer Sources 8-18 Wake-up Interrupt 8-18 External Watchdog 8-18
Duty-cycle programming 8-19 Spike Filtering 8-20
4.10 4.11 4.12 4.13 4.14 4.15
MMIO Registers 8-21
GPIO Mode Control Registers 8-24 GPIO Data Control 8-26 Readable Internal PNX15xx Series Signals 8-26 Sampling Pattern Generation Control Registers FIFO Queues8-27 Signal Event Monitoring Control Registers Timestamp Units8-34 Timestamp Unit Registers 8-34 GPIO Time Counter 8-34 GPIO TM3260 Timer Input Select 8-35 GPIO Interrupt Status 8-35 Clock Select 8-36 GPIO Interrupt Registers FIFO Queues (One each FIFO Queue)8-37 GPIO Module Status Register Timestamp Units8-38 GPIO POWERDOWN 8-43 GPIO Module 8-43 GPIO IO_SEL Selection Values 8-43
Applications
8-18
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Chapter Controller
2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.3.1 2.3.2 2.5.1 2.5.2 2.5.3 2.5.4
Introduction. Functional Description
Start Warm Start Start Mode Warm Start Observing Start State Arbitration First Level Arbitration: Between CPU9-3 Second Level Arbitration. Dynamic Ratios Pre-Emption Back Buffer (BLB) PMAN (Hub) versus Controller Interaction
2.5.5
Sequence Actions 9-16
Application Notes 9-16
Memory Configurations 9-16 Error Signaling 9-17 Latency 9-17 Data Coherency. 9-18 Programming Internal Arbiter 9-18 Controller Memory Devices9-20
4.0.1
Timing Diagrams Tables. 9-20
Tcas Timing Parameter 9-21 Trrd Timing Parameters 9-21 Trfc Timing Parameter 9-21 Timing Parameter 9-22 Tras Timing Parameter 9-22 Timing Parameter 9-22 Trcd_rd Timing Parameter. 9-23 Trcd_wr Timing Parameter 9-23
Addressing Memory Region Mapping Scheme Memory Rank Locations Clock Programming Power Management Halting Unhalting MMIO Directed Halt Auto Halt Observing Halt Mode
9-10 9-10 9-12 9-13 9-13 9-14 9-14 9-14 9-15
Register Descriptions 9-23
Register Summary 9-24 Register Table 9-25
References 9-32
Chapter Controller
Introduction. 10-1
Controller Features 10-1
Functional Description
10-1
Overview 10-1 Power Sequencing 10-2
Operation 10-3
Overview 10-3 Power Sequencing State Machine 10-3
3.2.1 3.2.2 3.2.3 3.2.4
IDLE state 10-4 DCEN state 10-4 BLEN state 10-5 PEPED state 10-5 Counter 10-5 Gating Logic 10-5
Register Descriptions 10-6
MMIO Registers 10-7
Chapter QVCP
Introduction. 11-1
Features 11-2
2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.6.1 2.6.2 2.7.1 2.7.2 2.7.3 2.7.4
2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.4.1
Functional Description
11-4 11-4 11-5 11-6 11-6 11-7 Chroma Undither (CKEY/UDTH) Unit Chroma Upsample Filter (CUPS) 11-11 Linear Interpolator (LINT) 11-11
QVCP Block Diagram Architecture Layer Resources Functions Memory Access Control (DMA CTRL) Pixel Formatter Unit (PFU)
DCTI (Digital Chroma/Color Transient Improvement)11-13 HSRU (Horizontal Sample Rate Upconverter). 1113
Video/Graphics Contrast Brightness Matrix (VCBM)11-11 Layer Fetch Control 11-12 Pool Resources Functions 11-13 CLUT (Color Look Table) 11-13
HIST (Histogram Modification) Unit 11-14 LSHR (Luminance/Luma Sharpening) Unit 11-14 Color Features (CFTR) Unit 11-14 PLAN (Semi Planar DMA) Unit 11-15 Screen Timing Generator 11-15 Mixer Structure 11-16 Generation 11-18 Alpha Blending. 11-19 Output Pipeline Structure. 11-19 Supported Output Formats 11-20 Layer Selection 11-20 Chrominance Downsampling (CDNS) 11-20 Gamma Correction Noise Shaping (GNSH& ONSH)11-20
Koninklijke Philips Electronics N.V. 2006. rights reserved.
PNX15XX_SER_3
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
4.1.1 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.10 Special Features 11-37 Signature Analysis 11-37 Programming Help 11-37 LINT Parameters 11-38 HSRU Parameters 11-38 LSHR Parameters 11-39 DCTI Parameters 11-40 CFTR Parameters 11-40 Underflow Behavior 11-40 Layer Underflow 11-41 Underflow Symptom 11-41 Underflow Recovery 11-41 Underflow Trouble-shooting 11-41 Underflow Handling 11-41 Setting QVCP External VSYNC 11-41 Clock Calculations. 11-42
2.7.5 2.7.6
Output Interface Modes 11-21 Auxiliary Pins 11-22
3.2.1 3.2.2 3.3.1 3.3.2 3.3.3 3.3.4 3.4.1
Programming Resource Assignment
11-23
MMIO Task Based Programming 11-23 Setup Order QVCP 11-24 Shadow Registers 11-25 Fast Access Registers 11-29 Programming Layer Pool Resources 11-30 Resource Assignment Selection 11-30 Aperture Assignment 11-30 Data Flow Selection 11-32 Pool Resource Assignment Example 11-34 Programming 11-35 Changing Timing. 11-36 Programming QVCP Different Output Formats
11-36
Register Descriptions 11-43
Register Summary 11-43 Register Tables 11-46
Application Notes. 11-37
Chapter Video Input Processor
Introduction. 12-1
Features 12-1
2.2.1 2.2.2 2.5.1
Functional Description
Block Level Diagram Chip Connections Data Routing Video Modes Input Timing Test Pattern Generator Input Formats Video Data Path Video Data Flow
12-2 12-2 12-3 12-3 12-4 12-4 12-5 12-8 12-8
2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8
Video Data Acquisition 12-8 Internal Timing 12-9 Field Identifier Generation 12-9 Horizontal Video Filters (Sampling, Scaling, Color Space Conversion)12-12 Video Data Write Memory 12-13 Auxiliary Data Path 12-15 Interrupt Generation 12-19
Register Descriptions 12-19
Register Summary 12-19 Register Table 12-21
Chapter FGPO: Fast General Purpose Output
Introduction. 13-1
FGPO Overview FGPO mapping MMIO Interface Header Initiator Data Initiator Record Output Mode Message Passing Mode
13-2 13-3 13-3 13-3 13-3 13-3 13-4
2.10 2.11 2.12 2.13
Record Message Counters 13-9 Timestamp 13-10 Variable Length 13-10 Output Time Registers 13-10 Double Buffer Operation 13-10 Single Buffer Operation 13-11
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.4.1 3.4.2
Operation
13-11
2.7.1 2.7.2 2.7.3 2.7.4
Functional Description
Reset. Base Addresses Sample (data) Size Record Message Size Records Messages Buffer Stride. Interrupt Events. BUF1DONE BUF2DONE Interrupts THRESH1_REACHED THRESH2_REACHED Interrupts13-7 UNDERRUN Interrupt Interrupt
13-5 13-6 13-6 13-6 13-7 13-7 13-7 13-7 13-7
Both Operating Modes 13-11 Setup 13-11 Interrupt Service Routines 13-12 Optimized Transfers 13-12 Terminating Transfers 13-12 Signal Edge Definitions 13-12 Message Passing Mode. 13-13 PNX1300 Series Message Passing Mode 13-13 Record Output Mode 13-13 Record Synchronization Events 13-14 Buffer Synchronization Events 13-14
13-8 13-8
Register Descriptions 13-15
Mode Register Setup 13-15 Status Registers 13-20
Koninklijke Philips Electronics N.V. 2006. rights reserved.
PNX15XX_SER_3
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Chapter FGPI: Fast General Purpose Interface
1.4.1 1.4.2 1.4.3
Introduction. 14-1
FGPI Overview FGPI mapping MMIO Interface Data Packer 8-Bit Sample Packing Mode 16-bit Sample Packing Mode 32-bit Sample Mode Record Capture Mode Message Passing Mode
14-2 14-3 14-3 14-3 14-4 14-4 14-4 14-4 14-4
2.10 2.11 2.12 2.13
Record Message Counters 14-9 Timestamp 14-9 Variable Length 14-10 Double Buffer Operation 14-10 Single Buffer Operation 14-11 Buffer Synchronization 14-12
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2.1 3.4.1 3.4.2 3.4.3
Operation
14-12
2.7.1 2.7.2 2.7.3 2.7.4 2.7.5
Functional Description
14-6
Reset. 14-6 Base Addresses 14-7 Sample (data) Size 14-7 Record Message Size 14-7 Records Messages Buffer 14-8 Stride. 14-8 Interrupt Events. 14-8 BUF1FULL BUF2FULL Interrupts 14-8 THRESH1_REACHED THRESH2_REACHED Interrupts14-8 OVERRUN Interrupt 14-8 Interrupt 14-9 OVERFLOW Interrupt (Message Passing Mode Only)14-9
Both Operating Modes 14-12 Setup 14-12 Interrupt Service Routines 14-13 Optimized Transfers 14-13 Terminating Transfers 14-13 Signal Edge Definitions 14-13 Message Passing Mode. 14-14 Minimum Message/Record Size 14-14 PNX1300 Series Message Passing Mode 14-15 Record Capture Mode 14-15 Record Synchronization 14-15 Buffer Synchronization 14-15 Setup Operation with Input Router VDI_MODE[7] 114-16
Register Descriptions 14-18
Mode Registers 14-18 Status Registers 14-21
Chapter Audio Output
Introduction. 15-1
Features 15-1
2.2.1 2.3.1 2.4.1 2.6.1 2.6.2
Functional Description
External Interface Memory Data Formats Endian Control Audio Data Operation TRANS_ENABLE Interrupts Interrupt Latency Timestamp Events Serial Data Framing Serial Frame Limitations Characteristics
15-1 15-2 15-4 15-4 15-5 15-5 15-6 15-6 15-6 15-6 15-8 15-8
2.6.3
Serial Framing Example 15-8 Codec Control 15-9 Data Latency HBE. 15-10 Error Behavior 15-11
3.1.1 3.1.2
Operation
15-12
Clock Programming 15-12 Sample Clock Generator 15-12 Clock System Operation 15-13 Reset-Related Issues 15-14 Register Programming Guidelines 15-14 Power Management 15-14
Register Descriptions 15-15
Register Summary 15-15 Register Table 15-15
Chapter Audio Input
Introduction. 16-1
Features 16-1
Functional Description
16-2
Chip Level External Interface 16-3 General Operations 16-4
3.1.1
Operation 16-5
Clock Programming Clock System Operation Reset-Related Issues Register Programming Guidelines
16-5 16-5 16-6 16-7
3.5.1 3.10 3.11 3.12 3.13
Serial Data Framing 16-7 Memory Data Formats 16-10 Endian Control 16-10 Memory Buffers Capture 16-11 Data Latency HBE. 16-11 Error Behavior 16-12 Interrupts 16-12 Timestamp Events 16-13 Diagnostic Mode 16-13 Software Reset 16-14 Mode 16-15
Koninklijke Philips Electronics N.V. 2006. rights reserved.
PNX15XX_SER_3
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
16-15
Register Descriptions
Register Table 16-15
Chapter SPDIF Output
Introduction. 17-1
Features 17-1
Functional Description
17-2
Architecture 17-2 General Operations 17-2
3.1.1 3.3.1 3.3.2
Operation 17-2
Clock Programming Sample Rate Programming Register Programming Guidelines Data Formatting IEC-60958 Serial Format Transparent Mode
17-2 17-2 17-3 17-4 17-4 17-6
3.4.1 3.4.2 3.4.3 3.4.4
Errors Interrupts 17-6 Error Conditions 17-6 Latency 17-7 Interrupts 17-7 Timestamp Events 17-7 Endian Mode 17-8
Signal Description
17-8
External Interface 17-8
Register Descriptions 17-8
Register Summary 17-8 Register Table 17-9
Chapter SPDIF Input
Introduction. 18-1
Features 18-1
2.2.1 2.3.1 2.3.2 2.3.3 2.3.4
Functional Description
SPDIF Input Block Level Diagram Architecture Functional Modes General Operations Received Serial Format Memory Formats. SPDIF Input Endian Mode Bandwidth Latency Requirements
18-1 18-1 18-2 18-2 18-3 18-3 18-3 18-4 18-5
3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12
LOCK UNLOCK State Behavior 18-8 UNLOCK Error Behavior 18-8 SPDI_CTL Functions 18-9 SPDI_CBITSx Channel Status Bits 18-10 SPDI_UBITSx User Bits 18-11 SPDI_BASEx SPDI_SIZE Registers Memory Buffers18-12 SPDI_SMPMASK Sample Size Masking 1812
SPDI_BPTR Start IEC60958 Block
18-12
3.1.1 3.1.2 3.1.3 3.1.4 3.2.1 3.2.2
Operation 18-6
Clock Programming 18-6 SPDIF Input Clock Domains 18-6 SPDIF Receiver Sample Rate Tolerance IEC6095818-6 SPDIF Input Receiver Jitter Tolerance 18-6 SPDIF Input Oversampling Clock 18-7 Register Programming Guidelines 18-7 SPDIF Input Register 18-7 SPDI_STATUS Register Functions. 18-8
Interrupts 18-13 Event Timestamping 18-13
4.1.1
Signal Descriptions 18-14
External Interface Pins 18-14 System Interface Requirements 18-14
5.1.1
Register Descriptions 18-15
Register Summary 18-15 SPDIF Input Interrupt Registers 18-15 Register Table 18-17
Chapter Memory Based Scaler
2.2.1 2.2.2 2.4.1 2.4.2 2.4.3
Introduction. 19-1 Functional Description 19-3
Block Level Diagram Data Flow Horizontal Processing Pipeline Vertical Processing Pipeline Data Processing General Operations Task Control Video Source Controls Horizontal Video Filters
19-3 19-3 19-4 19-4 19-5 19-6 19-6 19-7 19-8
2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11
Vertical Video Filters 19-10 De-Interlacing 19-10 Color-Key Processing 19-10 Alpha Processing 19-11 Video Data Output. 19-11 Address Generation 19-12 Interrupt Generation 19-12 Measurement Functions 19-13
Register Descriptions 19-14
Register Summary 19-14 Register Table 19-16
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Chapter Drawing Engine
Introduction. 20-1
Features 20-1
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14
Functional Description
Drawing Engine Block Level Diagram Architecture Registers Host Interface Color Expand. Rotator Source FIFO Pattern FIFO Destination FIFO. Write Datapath Source State Destination State Address Stepper Engine Vector Engine Memory Interface
20-1 20-2 20-2 20-2 20-2 20-2 20-3 20-3 20-3 20-3 20-3 20-3 20-3 20-3 20-4 20-4 20-4
2.2.15 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6
Byte Masking 20-4 General Operations 20-4 Raster Operations 20-4 Alpha Blending. 20-5 Source Data Location Type 20-5 Patterns 20-6 Transparency 20-6 Block Writes 20-6
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6
Operation
20-6
Register Programming Guidelines 20-6 Alpha Blending. 20-6 Mono Expand 20-9 Mono Register Setup 20-10 Solid Fill Setup 20-11 Color Setup 20-11 PatRam 20-12
Register Descriptions 20-13
Register Summary 20-14 Register Tables 20-15
Chapter MPEG-1 MPEG-2 Variable Length Decoder
Introduction. 21-1
Features 21-1
Functional Description
21-3
Block Level Diagram 21-3
3.2.1 3.2.2 3.2.3 3.2.4
Operation 21-3
Reset-Related Issues MMIO Registers Status (VLD_MC_STATUS) Interrupt Enable (VLD_IE) Control (VLD_CTL) Current Read Address (VLD_INP_ADR) Read Count (VLD_INP_CNT)21-6 Macroblock Header Current Write Address (VLD_MBH_ADR)21-6 Macroblock Header Current Write Count21-6 Run-Level Current Write Address (VLD_RL_ADR)21-7 Run-Level Current Write Count Command (VLD_COMMAND)
21-3 21-4 21-4 21-5 21-5
3.2.10 3.2.11 3.2.12 3.2.13 3.3.1 3.3.2 3.3.3 3.4.1 3.4.2 3.4.3
Shift Register (VLD_SR) 21-9 Quantizer Scale (VLD_QS) 21-9 Picture Info (VLD_PI). 21-9 Count (VLD_BIT_CNT) 21-9 Operation 21-9 Input 21-10 Output 21-10 Restart Parsing 21-13 Error Handling 21-13 Unexpected Start Code 21-14 Overflow 21-14 Flush 21-14
4.0.1
Application Notes 21-15
PNX1300 Series versus PNX15xx Series 2115
3.2.5 3.2.6 3.2.7 3.2.8 3.2.9
Register Descriptions 21-15
PNX1300 Series PNX15xx Series Register Differences21-15 Register Summary 21-15 Register Table 21-16
21-7 21-7
Chapter Digital Video Disc Descrambler
Introduction. 22-1
Functional Description 22-1
Introduction 23-1
Chapter LAN100 Ethernet Media Access Controller
Features 23-1 Description 23-4
Functional Description
23-2 Chip System Interconnections 23-2 Functional Block Diagram 23-3
Register Descriptions 23-5
Register Summary 23-5 Register Definitions 23-8
Koninklijke Philips Electronics N.V. 2006. rights reserved.
PNX15XX_SER_3
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
5.8.2 5.8.3 5.10 5.10.1 5.10.2 5.10.3 5.11 5.12 5.12.1 5.12.2 5.12.3 5.12.4 5.12.5 5.12.6 5.12.7 5.13 5.13.1 5.13.2 5.13.3 5.14 5.14.1 5.14.2 5.15 5.16 5.17 5.18 5.19 5.19.1 5.19.2 Real-time/non-real-time transmission mode 23-54 Quality-of-service Transmission Mode 23-57 Duplex Modes 23-58 IEEE 802.3/Clause Flow Control 23-59 Overview 23-59 Receive Flow Control 23-59 Transmit Flow Control 23-59 Half-duplex Mode Back Pressure 23-61 Receive filtering 23-62 Overview 23-62 Unicast, Broadcast Multicast 23-64 Perfect Address Match 23-64 Imperfect Hash Filtering 23-64 Pattern Match Filtering Logic Functions 23-65 Enabling Disabling Filtering 23-66 Runt Frames 23-66 Wake-up 23-66 Overview 23-66 Filtering 23-67 Magic Packet 23-67 Enabling Disabling Receive Transmit 2368
Pattern Matching Join Register 23-25
Descriptor Status Formats 23-27
Receive Descriptors Status 23-27 Transmit Descriptors Status 23-30
5.1.1 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.8.1
LAN100 Functions 23-33
MMIO Interface 23-33 Overview 23-33 Direct Memory Access 23-34 Descriptor FIFOs 23-34 Ownership Descriptors 23-34 Sequential Order with Wrap-around 23-35 Full Empty State FIFOs 23-35 Interrupt 23-36 Packet Fragments 23-36 Initialization 23-37 Transmit process 23-38 Overview 23-38 Device Driver Sets Descriptors Data23-38 Tx(Rt) Manager Reads Tx(Rt) Descriptor Arrays23-39 Tx(Rt) manager transmits data 23-39 Update ConsumeIndex 23-40 Write Transmission Status 23-40 Transmission Error Handling 23-40 Transmit Triggers Interrupts 23-41 Transmit example 23-42 Receive process 23-45 Device Driver Sets Descriptors 23-46 Manager Reads Descriptor Arrays
23-46
Manager Receives Data Update ProduceIndex Write Reception Status Reception Error Handling Receive Triggers Interrupts Device Driver Processes Receive Data Receive example Transmission Retry time-stamps Transmission modes Overview
23-46 23-47 23-47 23-47 23-48 23-49 23-49 23-53 23-53 23-53 23-53
Enabling Disabling Reception 23-68 Enabling Disabling Transmission 23-69 Transmission Padding 23-69 Huge Frames Frame Length Checking 23-70 Statistics Counters 23-71 Status Vectors 23-71 Reset 23-71 Hard Reset 23-71 Soft Reset 23-71
6.2.1 6.2.2
System Integration 23-73
Interface 23-73 Power Management 23-74 Sleep Mode 23-74 Coma Mode 23-74 Disabling LAN100 23-75 Little/big Endian 23-75 Interrupts 23-75 Errors Aborts 23-75 Cache coherency 23-76
Chapter TM3260 Debug
Introduction. 24-1
Features 24-1
3.1.1
Operation
24-4
2.1.1 2.1.2 2.1.3
Functional Description
General Operations Test Access Port (TAP) Controller. PNX15xx Series JTAG Instruction
24-1 24-1 24-1 24-2 24-4
Register Programming Guidelines 24-4 Handshaking Communication Protocol 24-5 Debug Settings 24-6
Register Descriptions 24-7
Register Summary 24-9
Chapter Interface
Introduction. 25-1
Features 25-2
Functional Description
25-2
2.1.1 2.1.2
General Operations 25-2 Arbitration Control Logic 25-2 Serial Clock Generator 25-3
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Volume
PNX15xx Series
25-3 25-3 25-3 25-3 25-3 25-4
2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8
Counter Control Register Status Decoder Register Input Filter Address Register Comparator Data Shift Register
2.1.9 2.1.10
Related Interrupts 25-4 Modes Operation 25-4
Register Descriptions 25-7
Register Tables 25-8
Chapter Memory Arbiter
Introduction. 26-1
Features 26-1
2.3.1
Arbiter Startup Behavior. 26-6
Operation
26-6
2.2.1
Functional Description
Arbiter Features Mapping Gate Arbitration Algorithm
26-1 26-2 26-2 26-3 26-3
Clock Programming 26-6 Register Programming Guidelines 26-6
Register Descriptions 26-7
Register Table 26-7
Chapter Power Management
1.1.1
Power Management Mechanisms. 27-1
Clock Management 27-1 Essential Operating Infrastructure During Powerdown27-1
1.1.2 1.1.3 1.1.4 1.1.5
Module Powerdown Sequence 27-1 Peripheral Module Wakeup Sequence 27-2 TM3260 Powerdown Modes 27-2 SDRAM Controller. 27-3
Chapter Pixel Formats
3.5.1
Introduction. 28-1 Summary Native Pixel Formats 28-2 Native Pixel Format Representation 28-3
Indexed Formats 16-Bit Pixel-Packed Formats 32-Bit Pixel-Packed Formats Packed 4:2:2 Formats Planar 4:2:0 4:2:2 Formats Planar Variants
28-3 28-4 28-4 28-5 28-6 28-6
3.5.2 3.5.3
Semi-Planar 10-Bit 4:2:2 4:2:0 Formats
28-9
Packed 10-bit 4:2:2 format 28-10
Universal Converter 28-10 Alpha Value Pixel Transparency 28-11 Values 28-11 Image Storage Format 28-11 System Endian Mode 28-12
Chapter Endian Mode
Introduction. 29-1
Features 29-1
6.2.1 6.2.2
Example: Audio In-Programmer's View
Functional Description Endian Mode Theory
29-2
Implementation Details
29-10
Endian Mode System Block Diagram 29-2
29-4
"CPU Rule" 29-4 "DMA Convention Rule" 29-6
PNX15xx Series Endian Mode Architecture Details29-7
Global Endian Mode Module Control Module SIMD Programming Issues Optional Endian Mode Override
29-7 29-7 29-8 29-8 29-8
PMAN Network Endian Block Diagram 29-10 Across Interface 29-11 Data Ordering Rules 29-11 Address Invariant Data Ordering Rules 29-12 Data Transfers Across Network 29-12 Across 29-13 DTL-to-MTL Adapters 29-14 Interface 29-14
Detailed Example 29-15 Introduction 30-1
Chapter Network
Functional Description
30-1
Error Generation 30-2 Interrupt Generation 30-2
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Philips Semiconductors
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2.3.1
Programmable Timeout 30-2 Arbitration 30-2 Endian Mode 30-3
Register Descriptions
30-3
Register Summary 30-3 Register Tables 30-4
Chapter TM3260 VLIW
Introduction. 31-1 Data sheet status Definitions Disclaimers Licenses Trademarks Contact information
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Chapter Integrated Circuit Data
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Application Diagram Crystal Oscillator 1-26 SSTL_2 Test Load Condition 1-27 SSTL_2 Receiver Signal Conditions. 1-27 BPX2T14MCP Test Load Condition 1-28 BPTS1CHP BPTS1CP Test Load Condition 1-29 BPTS3CHP BPTS3CP Test Load Condition 1-30 BPT3MCHDT5V BPT3MCHT5V Test Load Condition 1-31 Tval(min) Slew Rate Test Load Condition 1-32 Reset Timing 1-33 Output Input Timing Measurement Conditions 1-35 Tval(max) Rising Falling Edge 1-35 QVCP FGPO Timing 1-37 FGPI Timing 1-37 10/100 Timing Mode 1-38 10/100 Timing RMII Mode 1-39 Audio Input Timing. 1-40 Audio Output Timing 1-41 SPDIF Timing 1-41 Timing 1-42 Timing 1-43 Audio Output Timing 1-44 JTAG Timing 1-44 BGA456 Plastic Ball grid Array; Balls; body 1.75 1-45 Bottom View Assignment 1-46 View Assignment 1-47 Digital VCCP Power Supply Analog VCCA/VSSA Power Supply Filter 1-49 Digital Power Supply Analog VDDA/VSSA_1.2 Power Supply Filter 1-50 Digital Power Supply Analog VDDA/VSSA_1.2 Power Supply Filter 1-50
Chapter Overview
Figure Figure Block Diagram PNX15xx Series PNX15xx Series Functional Block Diagram
Chapter System Chip Resources
Figure Figure Figure Operating Modes PNX15xx Series PNX15xx Series System Memory Simplified Internal Infrastructure 3-30
Chapter Reset
Figure Figure Figure Figure Reset Module Block Diagram Watchdog Interrupt Mode Watchdog Interrupt Mode POR_IN_N Timing Reset Sequence
Chapter Clock Module
Figure Figure Figure Figure
PNX15XX_SER_3
Clock Module Block Diagram Block Diagram Block Diagram Clock Control Logic 5-13 Waveforms Blocking Logic 5-14
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Clock Stretcher 5-16 Clock Detection Circuit 5-18 TM3260, QVCP clocks 5-21 QVCP_PROC Clock 5-22 QVCP_PIX Clock 5-22 Clock Dividers 5-23 Internal PNX15xx Series Clock from Dividers. 5-24 Internal PNX15xx Series Clock from Dividers: PCI, SPDI, 5-25 Internal PNX15xx Series Clock from Dividers: Timestamp 5-25 GPIO Clocks 5-26 VDI_CLK1 Block Diagram 5-27 VDI_CLK2 Block Diagram 5-27 VDO_CLK1 Block Diagram 5-28 VDO_CLK2 Block Diagram 5-28 Clocks 5-29 Clocks 5-29 Clock Block Diagram 5-30 Receive Transmit Clocks 5-30 SPDO Clock 5-31
Chapter Boot Module
Figure Figure Figure Boot Block Diagram System Memory Block Diagram Configuration PNX15xx Series Standalone Mode. 6-10 System Memory Block Diagram Configuration PNX15xx Series Host-assisted Mode. 6-13
Chapter PCI-XIO Module
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Document title variable Block Diagram Read Status. Read Data Write Data Block Erase Motorola Write With DSACK 7-10 Motorola Write Without DSACK 7-11 Motorola Read 7-11 Flash Write 7-12 Flash Read 7-13 Interface 7-14 Isolation Translation Logic 7-15 Register Transfer/PIO Data Transfer 7-17 Timings 7-18 Transaction, Flow Controlled Device IORDY 7-18
Chapter General Purpose Input Output Pins
Figure Figure Figure Figure Figure Figure Figure Figure
PNX15XX_SER_3
GPIO Module Block Diagram Functional Block Diagram GPIO 32-bit Timestamp Format 1-bit Signal Sampling. 8-10 4-bit Signal Sampling 8-11 1-bit Pattern Generation 8-13 4-bit Samples FIFO Pattern Generation Mode 8-14 Example Signals with without Sub-Carrier 8-19
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
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Philips Semiconductors
Volume
PNX15xx Series
Figure Figure Figure
IrDA Control with Sub-Carrier Enabled 8-19 Sub-Carrier Multiplexing 8-19 Examples Duty Cycles Signals 8-20
Chapter Controller
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Ports SDRAM Controller Arbitration Controller account Arbitration when priority. account using dynamic ratios Address Mapping: Interleaved Mode 9-10 SDRAM Controller Start Halt State Machine 9-15 Examples Supported Memory Configurations 9-17 Tcas Timing Parameter 9-21 Trrd Timing Parameters 9-21 Trfc Timing Parameter. 9-21 Timing Parameter 9-22 Tras Timing Parameter 9-22 Timing Parameter 9-22 Trcd_rd Timing Parameter 9-23 Trcd_wr Timing Parameter 9-23
Chapter Controller
Figure Figure Figure Figure Block diagram Controller 10-2 Generic Power Sequence Panels 10-2 Power Sequencing State Machine Block Diagram 10-4 Clock Gating Logic 10-5
Chapter QVCP
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure QVCP Level Diagram 11-2 QVCP BLock Diagram. 11-4 Undithering Pedestal Manipulation 11-10 4:2:2 4:4:4 Formats 11-11 Mixer Block Diagram-Pixel Selection 11-18 Mixer Block Diagram-Pixel Processing 11-19 VBI/Programming Data Packet Formats 11-24 Shadow Mechanism 11-27 Shadowing Registers 11-28 Resource Layer 11-31 Resource Layer 11-32 2-Layer Resource Elements Scenario 11-32 Pool Aperture Reassignments 11-34 Video Frame Screen Timing 11-35
Chapter Video Input Processor
Figure Figure Figure Figure Figure Figure
PNX15XX_SER_3
Simplified Block Diagram 12-2 Module Interface 12-3 Digital Video Input Port Timing Relationships Mode 12-4 Test Pattern 12-5 Data Stream 12-6 Dual Data Stream 12-7
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Figure Figure Figure Figure Figure Figure Figure Figure
Video Data Flow 12-8 Source Target Window Parameters 12-9 Acquisition Window Counter Reference 12-9 Field Identifier Timing 12-10 Double Buffer Mode 12-14 Auxiliary Data Flow 12-15 Data Structure 12-16 Masked Checking 12-17
Chapter FGPO: Fast General Purpose Output
Figure Figure Figure Figure Figure Figure Level Block Diagram 13-2 FGPO Module Block Diagram 13-2 Back-to-back Message Passing Example 13-9 Double Buffer Major States 13-11 Signal Edge Definition 13-12 Back-to-back Message Passing Example 13-13
Chapter FGPI: Fast General Purpose Interface
Figure Figure Figure Figure Figure Figure Figure Level Block Diagram 14-2 FGPI Module Block Diagram 14-3 Input data width equal sample size setting 14-7 Double Buffer Major States 14-11 Buffer Sync Actions 14-12 Signal Edge Definition 14-13 Back-to-back Message Passing Example 14-14
Chapter Audio Output
Figure Figure Figure Figure Figure Figure Audio Block Diagram 15-2 Examples Audio Memory Formats 15-4 Definition Serial Frame Positions (POLARITY CLOCK_EDGE 15-7 Serial Frame Bits) 18-Bit Precision Converter 15-8 Example Codec Frame Layout Crystal Semiconductor CS4218 15-10 Audio Clock System Interface 15-12
Chapter Audio Input
Figure Figure Figure Figure Figure Figure Audio Block Diagram 16-2 Audio Clock System Interface 16-5 Audio Serial Frame Position Definition (POLARITY CLOCK_EDGE EARLYMODE 0)16-8 Audio Serial Frame Position Definition (POLARITY CLOCK_EDGE EARLYMODE 1)16-8 Serial Frame SAA7366 18-Bit Converter (Format SWS) 16-9 Audio Memory Formats 16-10
Chapter SPDIF Output
Figure Figure Figure Serial Format IEC-60958 Block 17-4 Bi-Phase Mark Data Transmission 17-5 Suggested External SPDIF Output Interface Circuitry 17-8
Chapter SPDIF Input
Figure
PNX15XX_SER_3
SPDIF Input Block Diagram 18-2
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Figure Figure Figure Figure Figure Figure Figure Figure Figure
Serial Format IEC60958 Block 18-3 SPDIF Input: Mode Format 18-4 SPDIF Input Sample Order View Memory 18-4 Endian Mode Byte Address Memory Format 18-5 SPDIF Input Oversampling Clock Generation 18-7 Lock/Unlock Processing SPDIF Input 18-9 SPDIF Input Consumer interface 18-14 SPDIF Input MMIO Registers 18-15 SPDIF Input MMIO Registers 18-16
Chapter Memory Based Scaler
Figure Figure Figure Figure Figure Figure Block Diagram 19-3 Level 19-3 Horizontal Processing Pipeline 19-4 Vertical Processing Pipeline 19-4 Task FIFO Linked List 19-6 Measurement 19-13
Chapter Drawing Engine
Figure Drawing Engine Block Diagram. 20-2
Chapter MPEG-1 MPEG-2 Variable Length Decoder
Figure Figure Figure Block Diagram 21-3 MPEG-2 Macro Block Header Output Format 21-11 MPEG-1 Macro Block Header Output Format 21-12
Chapter Digital Video Disc Descrambler Chapter LAN100 Ethernet Media Access Controller
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Simplified LAN100 Block Diagram 23-2 LAN100 Functional Block Diagram 23-3 Pattern matching join function 23-26 Receive descriptor memory layout 23-27 Transmit Descriptor Memory Layout. 23-30 Transmit example memory registers 23-42 Transmit example waves 23-45 Receive example memory registers 23-49 Receive example waves 23-52 Real-time/non-real-time transmit example 23-56 transmission example 23-58 Transmit flow control 23-61 Receive filter block diagram 23-63 Receive Active/Inactive state machine 23-68 Transmit Active/Inactive state machine 23-69
Chapter TM3260 Debug
Figure Figure Figure
PNX15XX_SER_3
State Diagram Controller 24-3 System with JTAG Access 24-6 Additional JTAG Data Control Registers 24-8
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Chapter Interface
Figure First Transmitted Byte 25-5
Chapter Memory Arbiter
Figure Arbitration Scheme 26-4
Chapter Power Management Chapter Pixel Formats
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Native Pixel Format Unit Layout 28-3 Indexed Formats 28-4 16-Bit Pixel-Packed Formats 28-4 32-Bit/Pixel Packed Formats 28-5 UYVY Packed 4:2:2 Format 28-5 YUY2/2vuy Packed 4:2:2 Format 28-6 Spatial Sampling Structure Packed Planar 4:2:2 Data 28-6 Spatial Sampling Structure 4:2:0 Data 28-6 Planar 4:2:0 4:2:2 Formats 28-7 Semi-Planar 4:2:0 4:2:2 Formats 28-8 Semi-Planar 10-bit 4:2:0 4:2:2 Formats 28-9 Packed 10-bit 4:2:2 Format. 28-10 Image Storage Format 28-12
Chapter Endian Mode
Figure Figure Figure Figure Figure Figure Figure System Block Diagram: Endian-Related Blocks 29-3 Big-Endian Layout DMA_Descriptor 29-4 Little-Endian Layout DMA_Descriptor 29-5 Memory Content Created Program. 29-6 Audio Memory Data Structure (Programmer's View) 29-9 Audio Control/Status MMIO Registers 29-10 Big-Endian External Drawing RGB-565 Pixels 29-16
Chapter Network Chapter TM3260 VLIW
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. March 2006
Philips Semiconductors
Volume
PNX15xx Series
Chapter Integrated Circuit Data
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table PNX1500 Types PNX1500 Modes PNX1500 Special I/Os. PNX1500 Interface Power List 1-19 Reference Voltage 1-20 Absolute Maximum Ratings 1-21 PNX1500 Operating Range Thermal Characteristics 1-21 PNX1500 Maximum Operating Speeds 1-22 PNX1501 Operating Range Thermal Characteristics 1-22 PNX1501 Maximum Operating Speeds 1-22 PNX1502 Operating Range Thermal Characteristics 1-22 PNX1502 Maximum Operating Speeds 1-23 PNX1503 Operating Range Thermal Characteristics 1-23 PNX1503 Maximum Operating Speeds 1-23 MPEG-2 Decoding with 720x480P Output PNX1502 1-24 Estimated PNX15xx Series Maximum Peak current 1-25 Specification HC-49U 27.00000 Crystal 1-26 Specification Oscillator Mode 1-26 SSTL_2 AC/DC Characteristics 1-26 BPX2T14MCP Characteristics 1-28 BPTS1CHP BPTS1CP Characteristics 1-29 BPTS3CHP BPTS3CP Characteristics 1-30 IPCHP IPCP Characteristics 1-31 BPT3MCHDT5V BPT3MCHT5V Characteristics 1-31 IIC3M4SDAT5V IIC3M4SCLT5V Characteristics 1-32 PCIT5V Characteristics 1-32 Reset Timing 1-33 DRAM Interface Timing 1-33 Timing 1-34 QVCP, FGPO Timing With Internal Clock Generation 1-36 QVCP, FGPO Timing With External Clock Generation 1-36 FGPI Timing. 1-37 10/100 Timing 1-38 10/100 RMII Timing. 1-38 Audio Input Timing 1-39 Audio Output Timing 1-40 SPDIF Timing 1-41 Timing 1-42 GPIO Timing 1-43 JTAG Timing 1-44 Recommended Trance Length 1-51 Ordering Information 1-53
Chapter Overview
Table Table Table Table Table Table
PNX15XX_SER_3
Partitioning Functions Resources PNX15xx Series Boot Options Footprints 32-bit 16-bit Interface TM3260 Characteristics 2-11 Native Pixel Format Summary 2-13 Video/Data Input Operating Modes. 2-18
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Product data sheet
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Philips Semiconductors
Volume
PNX15xx Series
Table Table Table
Video/Data Output Operating Modes 2-20 PNX15xx Series capabilities 2-24 PCI/XIO-16 Interface Unit Capabilities 2-25
Chapter System Chip Resources
Table Table Table Table Table Table Table Table Table Table Table SYSTEM Registers SYSTEM Registers SYSTEM Registers Semaphore MMIO Registers 3-11 Interrupt Source Assignments 3-12 TM3260 Timer Source Selection 3-14 TM3260 System Parameters MMIO Registers 3-16 Global Registers 3-18 Miscellaneous System MMIO registers 3-27 System Registers Summary 3-29 MMIO Memory 3-31
Chapter Reset
Table RESET Module
Chapter Clock Module
Table Table Table Table Table Table Table Table Table Table Table PNX15xx Series Module Clocks Current Adjustment Values Based Settings Characteristics 5-10 Internal Clock Dividers 5-10 Clock Assignment. 5-11 External Clocks 5-11 Bypass Clock Sources 5-14 Advantages Centralized Clock Gating Control 5-17 Registers Summar 5-31 CLOCK MODULE REGISTERS 5-34
Chapter Boot Module
Table Table Table Table Table Table Table Table Table Table Boot Modes Boot Commands. Default SDRAM Timing Parameters Latency Related SDRAM Timing Parameters Setup Command register Content Binary Sequence Common Boot Script Flash TIming Parameters Used Default Boot Scripts 6-11 Binary Sequence Section Flash Boot 6-12 Host Configuration Sequence 6-13 Examples EEPROM Devices 6-14
Chapter PCI-XIO Module
Table Table Table Table
PNX15XX_SER_3
Supported Commands Multiplexing Recommended Settings NAND GPXIO Address Configuration 7-16
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Product data sheet
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Philips Semiconductors
Volume
PNX15xx Series
Table Table Table Table Table
Timing 7-17 PCI-XIO Register Summary 7-22 Configuration Register Summary 7-23 Registers Description 7-24 Configuration Registers 7-44
Chapter General Purpose Input Output Pins
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table GPIO List GPIO Mode Select Settings MASK[xx] IOD[xx] Bits GPIO clock sources 8-17 Example Characteristics 8-18 Register Summary 8-21 GPIO Mode Control Registers 8-24 GPIO Data Control 8-26 Readable Internal PNX1500 Signals 8-26 Sampling Pattern Generation Control Registers FIFO Queues 8-27 Signal Event Monitoring Control Registers Timestamp Units 8-34 Timestamp Unit Registers 8-34 GPIO Time Counter 8-34 GPIO TM3260 Timer Input Select 8-35 GPIO Interrupt Status 8-35 Clock Select 8-36 GPIO Interrupt Registers FIFO Queues (One each FIFO Queue) 8-37 GPIO Module Status Register Timestamp Units 8-38 GPIO POWERDOWN 8-43 GPIO Module 8-43 GPIO IO_SEL Selection Values 8-43
Chapter Controller
Table Table Table Table Table Table Table Table Table Preemption Field. 32-Byte Interleaving, Columns 9-11 32-Byte Interleaving, Columns 9-11 Mapping scheme: 1024-Byte Interleaving, Columns 9-11 1024-Byte Interleaving, Columns 9-12 Timing Parameters 9-20 Commands 9-20 Register Summary 9-24 Register Description 9-25
Chapter Controller
Table Table Controller Register Summary 10-6 CONTROLLER Registers 10-7
Chapter QVCP
Table Table Table Table Table Table
PNX15XX_SER_3
Summary Native Pixel Formats. 11-7 Color Combining ROPs 11-8 Chroma Examples 11-9 Table ROPs 11-17 Data Packet Descriptor 11-23 Shadow Registers 11-28
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
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Philips Semiconductors
Volume
PNX15xx Series
Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Fast Access Registers. 11-29 Resource Assignment 11-30 Register Space Allocation. 11-31 Association 11-31 Resource-Layer Assignment Pool Resource 11-32 Programming Values Supported PNX15xx Series Output Formats 11-37 LINT programming 11-38 HSRU programming 11-38 LSHR Programming Parameters. 11-39 DCTI Programming Parameters 11-40 CFTR Programming Parameters. 11-40 Interface Characteristics Some Target Resolutions. 11-42 Register Module Association 11-43 QVCP Registers 11-46
Chapter Video Input Processor
Table Table Table Table Table Table Table Table Table Table Submodule Descriptions 12-3 Test Pattern Generator Setup 12-5 Video Input Formats 12-7 Relationship Between Input Formats Video Data Capture 12-8 Field Identifier Generation Modes 12-10 Output Pixel Formats 12-13 Relationship Between Input Formats Data Capture. 12-15 Relationship Between Input Formats Data Capture. 12-19 MMIO Register Summary 12-19 Video Input Processor (VIP) Registers 12-21
Chapter FGPO: Fast General Purpose Output
Table Table Table Table Module signal pins 13-5 Register Summary 13-15 Fast general purpose output (FGPO) 13-15 Status Registers 13-21
Chapter FGPI: Fast General Purpose Interface
Table Table Table Table Module signal pins 14-6 Register Summary 14-18 Fast general purpose INput (FGPI). 14-18 Status Registers 14-22
Chapter Audio Output
Table Table Table Table Table Table Table Table Table Audio Unit External Signals 15-3 Operating Modes Memory Formats

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