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PDIUSBD12
Universal Serial peripheral controller with parallel
Rev. 2006 Product data sheet
PDIUSBD12 cost- feature-optimized peripheral controller. normally used microcontroller-based systems communicates with system microcontroller over high-speed general-purpose parallel interface. also supports local transfer. This modular approach implementing interface allows designer choose optimum system microcontroller from wide variety available. This flexibility cuts down development time, risks costs, allowing existing architecture, minimizing firmware investments. This results fastest develop most cost-effective peripheral solution. PDIUSBD12 fully conforms Universal Serial Specification Rev. 2.0, supporting data transfer full-speed Mbit/s). also designed compliant with most device class specifications: imaging class, mass storage devices, communication devices, printing devices human interface devices. PDIUSBD12 ideally suited many peripherals, such printer, scanner, external mass storage (Zip drive) digital still camera. offers immediate cost reduction applications that currently SCSI implementations. PDIUSBD12 suspend power consumption along with LazyClock output allows easy implementation equipment that compliant ACPI, OnNow power management requirements. operating power allows implementation powered peripherals. also incorporates features, such SoftConnect, GoodLink, programmable clock output, frequency crystal oscillator, integration termination resistors. these features contribute significant cost savings system implementation same time ease implementation advanced functionality into peripherals.
Features
Complies with Universal Serial specification Rev. Supports data transfer full-speed Mbit/s) High performance peripheral controller with integrated SIE, FIFO memory, transceiver voltage regulator Compliant with most device class specifications High-speed MB/s) parallel interface external microcontroller microprocessor Fully autonomous operation Integrated multi-configuration FIFO memory
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Double buffering scheme main endpoint increases throughput eases real-time data transfer Data transfer rates: MB/s achievable bulk mode, Mbit/s achievable isochronous mode Bus-powered capability with very good performance Controllable LazyClock output during suspend Software-controllable connection (SoftConnect) Good connection indicator that blinks with traffic (GoodLink) Programmable clock frequency output Complies with ACPI, OnNow power management requirements Internal Power-On Reset (POR) low-voltage reset circuit Available SO28 TSSOP28 packages Full industrial grade operation from Full-scan design with high fault coverage ensures high quality Operation with dual voltages: extended supply range Multiple interrupt modes facilitate both bulk isochronous transfers
Ordering information
Table Ordering information North America PDIUSBD12D Package Name SO28 Description Temperature range Version Outside North America PDIUSBD12D
plastic small outline package; leads; SOT136-1 body width SOT361-1
PDIUSBD12PW PDIUSBD12PW TSSOP28 plastic thin shrink small outline package; leads; body width
PDIUSBD12_9
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Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Block diagram
UPSTREAM PORT
CLOCK RECOVERY
INTEGRATED
SoftConnect
ANALOG TX/RX
PHILIPS
MEMORY MANAGEMENT UNIT
VOLTAGE REGULATOR
PARALLEL INTERFACE
004aaa796
This conceptual block diagram does include each individual signal.
Block diagram
Pinning information
Pinning
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
VOUT3.3 XTAL2 XTAL1 GL_N RESET_N EOT_N DMACK_N DMREQ WR_N RD_N
004aaa532
PDIUSBD12
CS_N SUSPEND CLKOUT INT_N
configuration
PDIUSBD12_9
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Product data sheet
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PDIUSBD12
peripheral controller with parallel
description
Table Symbol DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 description Type[1] Description bidirectional data; slew-rate controlled bidirectional data; slew-rate controlled bidirectional data; slew-rate controlled bidirectional data; slew-rate controlled ground bidirectional data; slew-rate controlled bidirectional data; slew-rate controlled bidirectional data; slew-rate controlled bidirectional data; slew-rate controlled Address Latch Enable: falling edge used close latch address information multiplexed address data bus. Permanently tied separate address data configuration. chip select (active LOW) When CS_N LOW, ensure that RESET_N inactive state; otherwise, device will enter test mode. SUSPEND CLKOUT INT_N RD_N WR_N DMREQ DMACK_N EOT_N device suspend state programmable output clock (slew-rate controlled) interrupt (active LOW) read strobe (active LOW) write strobe (active LOW). request acknowledge (active LOW) transfer (active LOW); double VBUS sensing. EOT_N only valid when asserted together with DMACK_N either RD_N WR_N. reset (active asynchronous); built-in power-on reset circuit present on-chip, tied HIGH When RESET_N LOW, ensure that CS_N inactive state; otherwise, device will enter test mode. GL_N XTAL1 XTAL2 GoodLink indicator (active LOW) crystal connection MHz) crystal connection MHz); external clock signal, instead crystal, connected XTAL1, then XTAL2 should floated voltage supply (4.0 operate supply both VOUT3.3 pins. data line
CS_N
RESET_N
PDIUSBD12_9
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PDIUSBD12
peripheral controller with parallel
description .continued Type[1] Description data line regulated output; operate supply both VOUT3.3 pins address Selects command instruction selects data phase This don't care multiplexed address data configuration should tied HIGH.
Table Symbol VOUT3.3
power ground; analog; input; Output; Output with drive; OD4: Output open-drain with drive; OD8: Output open-drain with drive; IO2: Input output with drive; Output with drive.
PDIUSBD12_9
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PDIUSBD12
peripheral controller with parallel
Functional description
Analog transceiver
integrated transceiver directly interfaces cables through termination resistors.
Voltage regulator
regulator integrated on-chip supply analog transceiver. This voltage also provided output connect external pull-up resistor. Alternatively, PDIUSBD12 provides SoftConnect technology with integrated pull-up resistor.
MHz-to-48 clock multiplier Phase-Locked Loop (PLL) integrated on-chip. This allows low-cost crystal. ElectroMagnetic Interference (EMI) also minimized because lower frequency crystal. external components needed operation PLL.
clock recovery
clock recovery circuit recovers clock from incoming data stream using over-sampling principle. track jitter frequency drift specified Universal Serial Specification Rev. 2.0.
Philips Serial Interface Engine (PSIE)
Philips implements full protocol layer. completely hardwired speed needs firmware intervention. functions this block include: synchronization pattern recognition, parallel serial conversion, stuffing discarding stuffed bits, checking generation, verification generation, address recognition, handshake evaluation generation.
SoftConnect
connection accomplished connecting (for full-speed device) HIGH through pull-up resistor. PDIUSBD12, pull-up resistor integrated on-chip connected default. connection established through command sent external system microcontroller. This allows system microcontroller complete initialization sequence before deciding establish connection USB. Re-initialization connection also performed without requiring pull cable. PDIUSBD12 will check VBUS availability before connection established. VBUS sensing provided using EOT_N. details, Section 5.2. Sharing VBUS sensing EOT_N easily accomplished using VBUS voltage pull-up voltage normally open-drain output controller pin. Remark: tolerance internal resistors higher than that specified Universal Serial Specification Rev. overall voltage specification connection, however, still with good margin. decision make sure this feature lies with users.
PDIUSBD12_9 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
GoodLink
good connection indication provided through GoodLink technology. During enumeration, indicator will momentarily blink corresponding enumeration traffic. When PDIUSBD12 successfully enumerated configured, indicator will permanently Subsequent successful (with acknowledgment) transfer from PDIUSBD12 will blink LED. During suspend, will off. This feature provides user-friendly indication status device, connected traffic. useful field diagnostics tool isolate faulty equipment. This feature helps lower field support hotline costs.
Memory Management Unit (MMU) integrated
difference between integrated buffer lies speed between USB, running bursts Mbit/s parallel interface microcontroller. This allows microcontroller read write packets speed.
Parallel interface
generic parallel interface defined ease-of-use speed, allows direct interfacing major microcontrollers. microcontroller, PDIUSBD12 appears memory device with 8-bit data 1-bit address line (occupying locations). PDIUSBD12 supports both multiplexed non-multiplexed address data bus. PDIUSBD12 also supports Direct Memory Access (DMA) transfer that allows main endpoint (endpoint directly transfer from local shared memory. Both single-cycle burst mode transfers supported.
6.10 Example parallel interface 80C51 microcontroller
example shown Figure permanently tied signify separate address data configuration. PDIUSBD12 connects 80C51 ports. This port controls command data phase PDIUSBD12. multiplexed address data 80C51 directly connected data PDIUSBD12. address phase will ignored PDIUSBD12. clock input signal 80C51 (pin XTAL1) provided output CLKOUT PDIUSBD12.
PDIUSBD12
INT_N DATA[7:0] WR_N RD_N CLKOUT CS_N
80C51 INTO/P3.2 PORT (for example, P3.3) P[0.7:0.0] /AD[7:0] WR/P3.6 RD/P3.7 XTAL1 PORT
004aaa155
Example parallel interface 80C51 microcontroller
PDIUSBD12_9 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Direct Memory Access (DMA) transfer
allows efficient transfer block data between host local shared memory. Using Controller (DMAC), data transfer between main endpoint (endpoint PDIUSBD12 local shared memory occur autonomously, without local intervention. Preceding transfer, local receives from host necessary setup information accordingly programs controller. Typically, controller demand transfer mode, Byte Count register address counter programmed with correct values. this mode, transfers occur only when PDIUSBD12 requests them terminated when Byte Count register reaches zero. After controller programmed, ENABLE PDIUSBD12 local initiate transfer. PDIUSBD12 programmed single-cycle burst mode DMA. single-cycle DMA, DMREQ deactivated every single acknowledgment DMACK_N before being re-asserted. burst mode DMA, DMREQ kept active number bursts programmed device before going inactive. This process continues until PDIUSBD12 receives termination notice through EOT_N. This will generate interrupt notify local that operation completed. read operation, DMREQ will only activated whenever buffer full, signaling that host successfully transferred packet PDIUSBD12. With double buffering scheme, host start filling second buffer while first buffer being read out. This parallel processing increases effective throughput. When host does completely fill buffer (less than single direction configuration), DMREQ will deactivated last byte buffer, regardless current burst count. will re-asserted next packet with refreshed burst count. Similarly, write operations, DMREQ remains active whenever buffer full. When buffer filled packet sent over host next token DMREQ will reactivated transfer successful. Also, double buffering scheme here will improve throughput. non-isochronous transfer (bulk interrupt), buffer needs completely filled write operation before data sent host. only exception transfer, when reception EOT_N will stop write operation buffer content will sent host next token. isochronous transfers, local controller have guarantee that they sink source maximum packet size frame ms). assertion DMACK_N automatically selects main endpoint (endpoint regardless current selected endpoint. operation PDIUSBD12 interleaved with normal access other endpoints. operation terminated resetting ENABLE register assertion EOT_N together with DMACK_N either RD_N WR_N.
PDIUSBD12_9
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Product data sheet
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Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
PDIUSBD12 supports transfer single address mode also work dual address mode controller. single address mode, transfer done using DREQ, DMACK_N, EOT_N, WR_N RD_N control lines. dual address mode, pins DMREQ, DMACK_N EOT_N used; instead CS_N, WR_N RD_N control signals used. mode transfer protocol PDIUSBD12 needs followed. source DMAC accessed during read cycle destination during write cycle. Transfer needs done separate cycles, temporarily storing data DMAC.
Endpoint description
PDIUSBD12 endpoints sufficiently generic used various device classes ranging from imaging, printer, mass storage communication device classes. PDIUSBD12 endpoints configured four operating modes, depending Mode command. four modes are: Mode Mode Mode Mode Non-isochronous transfer (Non-ISO mode) Isochronous output only transfer (ISO-OUT mode) Isochronous input only transfer (ISO-IN mode) Isochronous input output transfer (ISO-I/O mode)
PDIUSBD12_9
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Product data sheet
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Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Endpoint configuration Endpoint index Transfer type Direction[1] control generic[2] generic[2][3] control generic[2] isochronous[3] control generic[2] isochronous[3] control generic[2] isochronous[3] Max. Packet size (bytes) 64[4]
Table
Endpoint number
Mode (Non-ISO mode)
Mode (ISO-OUT mode)
input host; OUT: output from host. Generic endpoints used either bulk interrupt endpoint. main endpoint (endpoint number double-buffered ease synchronization with real-time applications increase throughput. This endpoint supports access. Denotes double buffering. size shown single buffer.
Mode (ISO-IN mode)
Mode (ISO-I/O mode)
PDIUSBD12_9
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Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Main endpoint
main endpoint (endpoint number primary endpoint sinking sourcing relatively large amounts data. implements following features ease this task:
Double buffering. This allows parallel operation between access
local access, increasing throughput. Buffer switching automatically handled. This results transparent buffer operation.
operation. This interleaved with normal operation other endpoints. Automatic pointer handling during operation. local intervention
necessary when `crossing' buffer boundary.
Configurable endpoint either isochronous transfer non-isochronous (bulk
interrupt) transfer.
Command summary
Table Name Initialization commands Address/Enable Endpoint Enable Mode Data flow commands Read Interrupt register Select Endpoint device control control endpoint endpoint endpoint endpoint Read Last Transaction Status control control endpoint endpoint endpoint endpoint Read Buffer Write Buffer selected endpoint selected endpoint read read (optional) read (optional) read (optional) read (optional) read (optional) read (optional) read read read read read read read write device device device device write write write write read Command summary Destination Code (Hex) Transaction
PDIUSBD12_9
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PDIUSBD12
peripheral controller with parallel
Command summary .continued Destination control control endpoint endpoint endpoint endpoint Code (Hex) Transaction write write write write write write none none none none read
Table Name
Endpoint Status
Acknowledge Setup Clear Buffer Validate Buffer General commands Send Resume Read Current Frame Number
selected endpoint selected endpoint selected endpoint
Command description
11.1 Command procedure
There three basic types commands: initialization, data flow general. Respectively, these used initialize function; data flow between function host; some general commands.
11.2 Initialization commands
Initialization commands used during enumeration process network. These commands used enable function endpoints. They also used assigned address.
11.2.1 Address/Enable
Code (Hex) Transaction write This command used assigned address enable function.
Power-on value ADDRESS ENABLE
004aaa797
ADDRESS: value written becomes address. ENABLE: Logic enables this function.
Address/Enable command: allocation
PDIUSBD12_9
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PDIUSBD12
peripheral controller with parallel
11.2.2 Endpoint Enable
Code (Hex) Transaction write generic isochronous endpoints only enabled when function enabled using Address/Enable command.
Power-on value GENERIC/ISOCHRONOUS ENDPOINTS reserved; write
004aaa798
GENERIC ISOCHRONOUS ENDPOINTS: Logic indicates that generic isochronous endpoints enabled.
Endpoint Enable command: allocation
11.2.3 Mode
Code (Hex) Transaction write Mode command followed data writes. first byte contains configuration bits. second byte clock division factor byte.
Power-on value reserved LAZYCLOCK CLOCK RUNNING INTERRUPT MODE SoftConnect reserved; write ENDPOINT CONFIGURATION
004aaa799
allocation, Table
Mode command, configuration byte: allocation
PDIUSBD12_9
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Product data sheet
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Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Mode command, configuration byte: allocation Description These bits endpoint configurations follows: Mode (Non-ISO mode) Mode (ISO-OUT mode) Mode (ISO-IN mode) Mode (ISO-I/O mode) details, Section
Table
Symbol
ENDPOINT CONFIGURATION
SoftConnect
Logic indicates that upstream pull-up resistor will connected VBUS available. Logic means that upstream resistor will connected. programmed value will changed reset. Logic indicates that errors `NAK' reported will generate interrupt. Logic indicates that only reported. programmed value will changed reset. Logic indicates that internal clocks always running even during suspend state. Logic indicates that internal clock, crystal oscillator stopped, whenever needed. meet strict suspend current requirement, this must logic programmed value will changed reset. Logic indicates that CLKOUT will switch LazyClock. Logic indicates that CLKOUT switches LazyClock after SUSPEND goes HIGH. LazyClock frequency programmed value will changed reset.
INTERRUPT MODE CLOCK RUNNING
LAZYCLOCK
Power-on value CLOCK DIVISION FACTOR reserved SET_TO_ONE SOF-ONLY INTERRUPT MODE
004aaa800
allocation, Table
Mode command, clock division factor byte: allocation
PDIUSBD12_9
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PDIUSBD12
peripheral controller with parallel
Mode command, clock division factor byte: allocation Description Setting this logic will cause interrupt line activated because Start-Of-Frame (SOF) clock only, regardless setting PIN-INTERRUPT MODE, DMA. This must logic before read write operation. This should always logic after power. zero after power-on reset. value indicates clock division factor CLKOUT. output frequency where clock division factor. reset value This will produce output frequency that then programmed down user. minimum value giving frequency range MHz. minimum value giving maximum frequency MHz. maximum value giving minimum frequency MHz. PDIUSBD12 design ensures glitching during frequency change. programmed value will changed reset.
Table
Symbol SOF-ONLY INTERRUPT MODE SET_TO_ONE
CLOCK DIVISION FACTOR
11.2.4
Code (Hex) Transaction read write command followed data write read from Configuration register. 11.2.4.1 Configuration register During operation, buffer header (status byte length information) transferred from local CPU. This allows data continuous interleaved chunks these headers. read operations, header will skipped PDIUSBD12. Section 11.3.5 command. write operations, header will automatically added PDIUSBD12. This provides clean simple data transfer.
Power-on value BURST ENABLE DIRECTION AUTO RELOAD INTERRUPT MODE ENDPOINT INDEX INTERRUPT ENABLE ENDPOINT INDEX INTERRUPT ENABLE
004aaa801
allocation, Table
command: allocation
PDIUSBD12_9
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PDIUSBD12
peripheral controller with parallel
command: allocation Symbol ENDPOINT INDEX INTERRUPT ENABLE Description Logic allows interrupt generated whenever endpoint buffer validated (see Section 11.3.8 command). Normally turned operation reduce unnecessary servicing. Logic allows interrupt generated whenever endpoint buffer contains valid packet. Normally turned operation reduce unnecessary servicing. Logic signifies normal interrupt mode which interrupt generated logical bits interrupt registers. Logic signifies that interrupt will occur when clock seen upstream bus. other normal interrupts still active. When this logic operation will automatically restart. This determines direction data flow during transfer. Logic means from external shared memory PDIUSBD12 (DMA write); logic means from PDIUSBD12 external shared memory (DMA read). Writing logic this will start operation through assertion DMREQ. main endpoint buffer must full (for read) empty (for write), before DMREQ asserted. single cycle mode, DMREQ deactivated receiving DMACK_N. burst mode DMA, DMREQ deactivated after number burst exhausted. then asserted again next burst. This process continues until EOT_N asserted together with DMACK_N either RD_N WR_N, which will reset this logic terminate operation. operation also terminated writing logic this bit. Selects burst length operation: Single-cycle Burst (4-cycle) Burst (8-cycle) Burst (16-cycle)
Table
ENDPOINT INDEX INTERRUPT ENABLE
INTERRUPT MODE
AUTO RELOAD DIRECTION
ENABLE
BURST
11.3 Data flow commands
Data flow commands used manage data transmission between endpoints external microcontroller. Much data flow initiated using interrupt microcontroller. microcontroller utilizes these commands access determine whether endpoint FIFOs have valid data.
11.3.1 Read Interrupt register
Code (Hex) Transaction read
PDIUSBD12_9
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peripheral controller with parallel
This command indicates origin interrupt. endpoint interrupt bits (bits cleared reading Endpoint Last Transaction Status register through Read Last Transaction Status command. other bits cleared after reading Interrupt registers.
Power-on value CONTROL ENDPOINT CONTROL ENDPOINT ENDPOINT ENDPOINT MAIN ENDPOINT MAIN ENDPOINT RESET SUSPEND CHANGE
004aaa802
allocation, Table
Interrupt register, byte allocation
Power-on value reserved
004aaa803
EOT: This signifies that operation completed.
Interrupt register, byte allocation Table Read Interrupt register, byte allocation Description When PDIUSBD12 does receive three SOFs, will into suspend state SUSPEND CHANGE will HIGH. change suspend awake state will this HIGH generate interrupt. After reset, interrupt will generated this will logic reset identical hardware reset through RESET_N pin, except reset generates interrupt notification device enabled default address
Symbol SUSPEND CHANGE
RESET
PDIUSBD12_9
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peripheral controller with parallel
11.3.2 Select Endpoint
Code (Hex) Transaction read (optional) Select Endpoint command initializes internal pointer start selected buffer. Optionally, this command followed data read, which returns this byte.
Power-on value FULL/EMPTY STALL reserved
004aaa804
FULL/EMPTY: Logic indicates that buffer full, logic indicates empty buffer. STALL: Logic indicates that selected endpoint stall state.
Select Endpoint command: allocation
11.3.3 Read Endpoint Status
Code (Hex) Transaction read
reserved SETUP PACKET reserved BUFFER FULL BUFFER FULL ENDPOINT STALLED
004aaa056
Read Endpoint Status: allocation
11.3.4 Read Last Transaction Status register
Code (Hex) Transaction read Read Last Transaction Status command followed data read that returns status last transaction endpoint. This command also resets corresponding interrupt flag Interrupt register, clears status, indicating that read. This command useful debugging purposes. status information overwritten each transaction because keeps track every transaction.
PDIUSBD12_9
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PDIUSBD12
peripheral controller with parallel
Power-on value DATA RECEIVE/TRANSMIT SUCCESS ERROR CODE (see table) SETUP PACKET DATA PACKET PREVIOUS STATUS READ
004aaa805
allocation, Table
Read Last Transaction Status register: allocation Table Read Last Transaction Status register: allocation Symbol PREVIOUS STATUS READ DATA0/1 PACKET SETUP PACKET ERROR CODE Description Logic indicates second event occurred before previous status read. Logic indicates last successful received sent packet DATA1 PID. Logic indicates last successful received packet SETUP token (this will always read buffers). Table
DATA RECEIVE/TRANSMIT Logic indicates that data been successfully received SUCCESS transmitted. Error codes Description error encoding error; bits inversion bits unknown; encoding valid, does exist unexpected packet; packet type expected token, data acknowledge), SETUP token non-control endpoint token error data error time-out error never happens unexpected End-Of-Packet (EOP) sent received sent stall, token received, endpoint stalled overflow error, received packet longer than available buffer space stuff error wrong DATA PID; received DATA what expected
Table Error code (binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1111
PDIUSBD12_9
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peripheral controller with parallel
11.3.5 Read Buffer
Code (Hex) Transaction read multiple bytes (max. 130) Read Buffer command followed number data reads that return contents selected endpoint data buffer. After each read, internal buffer pointer incremented buffer pointer reset buffer Read Buffer command. This means that reading writing buffer interrupted other command (except Select Endpoint). data buffer organized follows:
Byte reserved; have value Byte number length data bytes Byte data byte Byte data byte
first bytes will skipped read operation. Therefore, first read will data byte second read will data byte PDIUSBD12 determine last byte this packet through termination packet.
11.3.6 Write Buffer
Code (Hex) Transaction write multiple bytes (max. 130) Write Buffer command followed number data writes that load endpoints buffer. Data must organized same described Read Buffer command. first byte (reserved) should always During write operation, first bytes will bypassed. Therefore, first write will write into data byte second write will write into data byte non-isochronous transfer (bulk interrupt), buffer must completely filled before data sent host switch next buffer occurs. exception transfer indicated activation EOT_N, when current buffer content (completely full not) will sent host. Remark: There protection against writing reading over buffer's boundary, against writing into buffer reading from buffer. these actions could cause incorrect operation. Data buffer only meaningful after successful transaction. exception during operation main endpoint (endpoint which case pointer automatically pointed second buffer after reaching boundary (double buffering scheme).
11.3.7 Clear Buffer
Code (Hex) Transaction none
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peripheral controller with parallel
When packet completely received, internal endpoint buffer full flag set. subsequent packets will refused returning NAK. When microcontroller read data, should free buffer using Clear Buffer command. When buffer cleared, packets will accepted.
11.3.8 Validate Buffer
Code (Hex) Transaction none When microprocessor written data into buffer, should buffer full flag using Validate Buffer command. This indicates that data buffer valid sent host when next token received.
11.3.9 Endpoint Status
Code (Hex) Transaction write stalled control endpoint automatically un-stalled when receives SETUP token, regardless content packet. endpoint should stay stalled state, microcontroller re-stall When stalled endpoint un-stalled (either Endpoint Status command receiving SETUP token), also re-initialized. This flushes buffer buffer waits DATA0 PID, buffer writes DATA0 PID. Even when un-stalled, writing logic Endpoint Status initializes endpoint.
Power-on value STALLED reserved
004aaa806
STALLED: Logic indicates endpoint stalled.
Endpoint Status: allocation
11.3.10 Acknowledge Setup
Code (Hex) Transaction none arrival SETUP packet flushes buffer, disables Validate Buffer Clear Buffer commands both endpoints. microcontroller needs re-enable these commands using Acknowledge Setup command. This ensures that last SETUP packet stays buffer packet sent back host, until microcontroller acknowledged explicitly that seen SETUP packet.
PDIUSBD12_9
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PDIUSBD12
peripheral controller with parallel
microcontroller must send Acknowledge Setup command both endpoints.
11.4 General commands
11.4.1 Send Resume
Code (Hex) Transaction none Sends upstream resume signal This command normally issued when device suspend. Resume command followed data read write.
11.4.2 Read Current Frame Number
Code (Hex) Transaction read This command followed data reads returns frame number last successfully received SOF. frame number returned least significant byte first.
least significant byte
most significant byte
004aaa807
Read Current Frame Number
Interrupt modes
Table
Interrupt modes INTERRUPT MODE[2] Interrupt types Normal[3] Normal only
SOF-ONLY INTERRUPT MODE[1]
clock division factor byte Mode command (see Table command (see Table Normal interrupts from Interrupt register.
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peripheral controller with parallel
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Vesd Tstg Ptot
Parameter supply voltage input voltage latch-up current electrostatic discharge voltage storage temperature total power dissipation
Conditions
-0.5 -0.5
+6.0 +2000 +150
Unit
-2000
Equivalent discharging capacitor through resistor.
Recommended operating conditions
Table VCC1 VCC2 VI/O VIA(I/O) Tamb Recommended operating conditions Conditions apply VCC1 only apply VCC2 both VOUT3.3 pins
Symbol Parameter supply voltage supply voltage input voltage voltage input/output input voltage analog pins output voltage ambient temperature
Unit
Section Section device
Supply voltage (main mode). Supply voltage (alternate mode). Operating ambient temperature free air.
Static characteristics
Table Symbol Vhys Static characteristics (digital pins) Parameter LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage Schmitt trigger pins rated drive Conditions Unit
Input levels
Output levels
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peripheral controller with parallel
Table Symbol
Static characteristics (digital pins) .continued Parameter HIGH-level output voltage Conditions rated drive Unit
Leakage current Table Symbol IL(dl) ZDRV
off-state output current leakage current suspend current supply current Static characteristics (AI/O pins) Parameter data line leakage current differential input sensitivity differential common mode range single-ended receiver threshold LOW-level output voltage HIGH-level output voltage input capacitance driver output impedance pull-up resistance
open-drain pins oscillator stopped inputs GND/VCC
Conditions hi-Z; |(D+) (D-)| includes range
Unit
Leakage current Input levels
Output levels steady state drive SoftConnect
Capacitance Output resistance Pull-up resistance
Includes external resistors
Dynamic characteristics
Table Dynamic characteristics (AI/O pins; full-speed) VCC; unless otherwise specified.[1] Symbol Parameter Driver characteristics tRFM VCRS tEOPT tDEOP
PDIUSBD12_9
Conditions
Unit
rise time fall time rise time/fall time matching (tR/tF) output signal crossover voltage source width differential data transition skew
Driver timing Figure Figure
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peripheral controller with parallel
Table Dynamic characteristics (AI/O pins; full-speed) .continued VCC; unless otherwise specified.[1] Symbol Parameter Receiver timing: tJR1 tJR2 tEOPR1 tEOPR2 receiver data jitter tolerance next transition receiver data jitter tolerance paired transition width receiver width receiver must reject EOP; Figure must accept EOP; Figure
Conditions
Unit
-18.5
+18.5
Test circuit, Figure Characterized implemented production test. Guaranteed design.
tPERIOD
CROSSOVER POINT EXTENDED CROSSOVER POINT
DIFFERENTIAL DATA LINES
DIFFERENTIAL DATA SEO/EOP SKEW tPERIOD tDEOP
SOURCE WIDTH: tEOPT
RECEIVER WIDTH: tEOPR1, tEOPR2
004aaa808
tPERIOD duration corresponding with data rate.
Differential data-to-EOP transition skew width Table Symbol tAVLL tLLAX tCLWL tWHCH tAVWL tWHAX tWDSU tWDH
PDIUSBD12_9
Dynamic characteristics (parallel interface) Parameter HIGH pulse width address valid time address transition time CS_N (DMACK_N) WR_N time WR_N HIGH CS_N (DMACK_N) HIGH time valid WR_N time WR_N HIGH transition time WR_N pulse width write data setup time write data hold time write cycle time Conditions 130[2] 500[3] Unit
timing
Write timing
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Table Symbol
Dynamic characteristics (parallel interface) .continued Parameter Conditions 130[2] 500[3] Unit
t(WC write command write data Read timing tCLRL tRHCH tAVRL tRLDD tRHDZ t(WC
CS_N (DMACK_N) RD_N time RD_N HIGH CS_N (DMACK_N) HIGH time valid RD_N time RD_N pulse width RD_N data driven time RD_N HIGH data Hi-Z time read cycle time write command read data
negative. access only module 64th byte second last (EOT byte. timing valid back-to-back data access only.
tAVLL tLLAX
DATA[7:0]
ADDRESS
DATA
004aaa809
timing
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
CS_N DMACK_N
tCLRL tCLWL
tRHCH tWHCH
tAVRL tAVWL
tWHAX COMMAND DATA
WR_N
t(WC t(WC tWDSU DATA[7:0] RD_N tRHNDV tRLDD DATA[7:0] tRHDZ VALID DATA tRLDD VALID DATA
004aaa058
tWDH
VALID DATA
Parallel interface timing (I/O DMA) Table Symbol tAHRH tSHAH tRHSH Dynamic characteristics (DMA) Parameter DMACK_N HIGH DMREQ HIGH time RD_N/WR_N HIGH DMACK_N HIGH time DMREQ HIGH RD_N/WR_N HIGH time EOT_N pulse width simultaneous DMACK_N, RD_N/WR_N EOT_N time Conditions Unit
Single-cycle timing
Burst timing tSLRL tRHNDV tELRL RD_N/WR_N DMREQ time RD_N (only) HIGH next data valid EOT_N DMREQ time
timing
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
tRHSH
tAHRH
DMREQ DMACK_N
tSHAH
RD_N/WR_N
EOT_N(1)
004aaa810
EOT_N considered valid when DMACK_N, RD_N/WR_N EOT_N LOW.
Single-cycle timing
tRHSH DMREQ tSLRL DMACK_N
tSHAH RD_N/WR_N
004aaa811
Burst timing
DMREQ tELRL DMACK_N
RD_N/WR_N
EOT_N
004aaa812
terminated
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Test information
dynamic characteristics analog ports listed Table were determined using circuit shown Figure
internal
test point
004aaa813
Load
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Package outline
SO28: plastic small outline package; leads; body width SOT136-1
index detail
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT inches max. 2.65 2.45 2.25 0.25 0.01 0.49 0.36 0.32 0.23 18.1 17.7 0.71 0.69 0.30 0.29 1.27 0.05 10.65 10.00 0.043 0.039 0.25 0.01 0.25 0.01
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
Note Plastic metal protrusions 0.15 (0.006 inch) maximum side included. OUTLINE VERSION SOT136-1 REFERENCES 075E06 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Package outline SOT136-1 (SO28)
PDIUSBD12_9 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
TSSOP28: plastic thin shrink small outline package; leads; body width
SOT361-1
index
detail
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13
Notes Plastic metal protrusions 0.15 maximum side included. Plastic interlead protrusions 0.25 maximum side included. OUTLINE VERSION SOT361-1 REFERENCES JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Package outline SOT361-1 (TSSOP28)
PDIUSBD12_9 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Soldering
19.1 Introduction soldering surface mount packages
This text gives very brief insight complex technology. more in-depth account soldering found Data Handbook IC26; Integrated Circuit Packages (document order number 9398 90011). There soldering method that ideal surface mount packages. Wave soldering still used certain surface mount ICs, suitable fine pitch SMDs. these situations reflow soldering recommended.
19.2 Reflow soldering
Reflow soldering requires solder paste suspension fine solder particles, flux binding agent) applied printed-circuit board screen printing, stencilling pressure-syringe dispensing before package placement. Driven legislation environmental forces worldwide lead-free solder pastes increasing. Several methods exist reflowing; example, convection convection/infrared heating conveyor type oven. Throughput times (preheating, soldering cooling) vary between seconds seconds depending heating method. Typical reflow peak temperatures range from depending solder paste material. top-surface temperature packages should preferably kept:
below (SnPb process) below (Pb-free process)
BGA, HTSSON.T SSOP.T packages packages with thickness packages with thickness volume called thick/large packages.
below (SnPb process) below (Pb-free process) packages with
thickness volume called small/thin packages. Moisture sensitivity precautions, indicated packing, must respected times.
19.3 Wave soldering
Conventional single wave soldering recommended surface mount devices (SMDs) printed-circuit boards with high component density, solder bridging non-wetting present major problems. overcome these problems double-wave soldering method specifically developed. wave soldering used following conditions must observed optimal results:
double-wave soldering method comprising turbulent wave with high upward
pressure followed smooth laminar wave.
packages with leads sides pitch (e):
larger than equal 1.27 footprint longitudinal axis preferred parallel transport direction printed-circuit board;
PDIUSBD12_9 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
smaller than 1.27 footprint longitudinal axis must parallel transport direction printed-circuit board. footprint must incorporate solder thieves downstream end.
packages with leads four sides, footprint must placed angle
transport direction printed-circuit board. footprint must incorporate solder thieves downstream side corners. During placement before soldering, package must fixed with droplet adhesive. adhesive applied screen printing, transfer syringe dispensing. package soldered after adhesive cured. Typical dwell time leads wave ranges from seconds seconds depending solder material applied, SnPb Pb-free respectively. mildly-activated flux will eliminate need removal corrosive residues most applications.
19.4 Manual soldering
component first soldering diagonally-opposite leads. voltage less) soldering iron applied flat part lead. Contact time must limited seconds When using dedicated tool, other leads soldered operation within seconds seconds between
19.5 Package related soldering information
Table Package[1] BGA, HTSSON.T[3], LBGA, LFBGA, SQFP, SSOP.T[3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, PLCC[5], LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN.L[8], PMFP[9], WQCCN.L[8]
Suitability surface mount packages wave reflow soldering methods Soldering method Wave suitable suitable[4] Reflow[2] suitable suitable
suitable recommended[5][6] recommended[7]
suitable suitable suitable suitable
suitable
more detailed information packages refer (LF)BGA Application Note (AN01026); order copy from your Philips Semiconductors sales office. surface mount (SMD) packages moisture sensitive. Depending upon moisture content, maximum temperature (with respect time) body size package, there risk that internal external package cracks occur vaporization moisture them (the called popcorn effect). details, refer Drypack information Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages extremely sensitive reflow soldering conditions must account processed through more than soldering cycle subjected infrared reflow soldering with peak temperature exceeding measured atmosphere reflow oven. package body peak temperature must kept possible.
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
These packages suitable wave soldering. versions with heatsink bottom side, solder cannot penetrate between printed-circuit board heatsink. versions with heatsink side, solder might deposited heatsink surface. wave soldering considered, then package must placed angle solder wave direction. package footprint must incorporate solder thieves downstream side corners. Wave soldering suitable LQFP, TQFP packages with pitch larger than definitely suitable packages with pitch equal smaller than 0.65 Wave soldering suitable SSOP, TSSOP, VSSOP packages with pitch equal larger than 0.65 definitely suitable packages with pitch equal smaller than Image sensor packages principle should soldered. They mounted sockets delivered pre-mounted flex foil. However, image sensor package mounted client flex foil using soldering process. appropriate soldering profile provided request. soldering manual soldering suitable PMFP packages.
Abbreviations
Table Acronym ACPI DMAC FIFO PSIE SCSI Abbreviations Description Advanced Configuration Power Interface Central Processing Unit Cyclic Redundancy Code Direct Memory Access Direct Memory Access Controller ElectroMagnetic Interference First First Isochronous Memory Management Unit Acknowledged Open-Drain Packet Identifier Phase-Locked Loop Power-On Reset Philips Serial Interface Engine Random Access Memory Small Computer System Interface Serial Interface Engine Start-Of-Frame Universal Serial
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Revision history
Table Revision history Release date 20060511 Data sheet status Product data sheet Change notice Supersedes PDIUSBD12-08 Document PDIUSBD12_9 Modifications:
Updated following:
PDIUSBD12-08 (9397 08969) PDIUSBD12-07 (9397 08117) PDIUSBD12-06 (9397 04979)
format this data sheet been redesigned comply with presentation information standard Philips Semiconductors. symbols parameters have been changed, wherever applicable, comply with presentation information standard Philips Semiconductors. Changed terminology interface device peripheral controller. Section "Features": removed circuit protection from list. Figure "Pin configuration" updated name Added additional description Modified Figure "Example parallel interface 80C51 microcontroller". Section 11.3.5 "Read Buffer": updated second paragraph. Table "Limiting values": removed table note Product data Product data Product data PDIUSBD12-07 PDIUSBD12-06
20011220 20011127 20010423
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Legal information
22.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet
22.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Philips Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Philips Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
result personal injury, death severe property environmental damage. Philips Semiconductors accepts liability inclusion and/or Philips Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Philips Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Philips Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Philips Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
22.3 Disclaimers
General Information this document believed accurate reliable. However, Philips Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Philips Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Philips Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Philips Semiconductors product reasonably expected
22.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. GoodLink trademark Koninklijke Philips Electronics N.V. SoftConnect trademark Koninklijke Philips Electronics N.V.
Contact information
additional information, please visit: sales office addresses, send email
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Ordering information description Endpoint configuration Command summary Mode command, configuration byte: allocation Mode command, clock division factor byte: allocation command: allocation Read Interrupt register, byte allocation Read Last Transaction Status register: allocation Error codes Interrupt modes Limiting values Recommended operating conditions Static characteristics (digital pins) Static characteristics (AI/O pins) Dynamic characteristics (AI/O pins; full-speed) Dynamic characteristics (parallel interface) Dynamic characteristics (DMA) Suitability surface mount packages wave reflow soldering methods Abbreviations Revision history
continued
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Figures
Block diagram configuration Example parallel interface 80C51 microcontroller Address/Enable command: allocation Endpoint Enable command: allocation Mode command, configuration byte: allocation Mode command, clock division factor byte: allocation command: allocation Interrupt register, byte allocation Interrupt register, byte allocation Select Endpoint command: allocation Read Endpoint Status: allocation Read Last Transaction Status register: allocation Endpoint Status: allocation Read Current Frame Number Differential data-to-EOP transition skew width. timing Parallel interface timing (I/O DMA) Single-cycle timing Burst timing terminated Load Package outline SOT136-1 (SO28) Package outline SOT361-1 (TSSOP28).
continued
PDIUSBD12_9
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. 2006
Philips Semiconductors
PDIUSBD12
peripheral controller with parallel
Contents
General description Features Ordering information Block diagram Pinning information Pinning description Functional description Analog transceiver Voltage regulator. clock recovery Philips Serial Interface Engine (PSIE) SoftConnect GoodLink Memory Management Unit (MMU) integrated RAM. Parallel interface 6.10 Example parallel interface 80C51 microcontroller Direct Memory Access (DMA) transfer Endpoint description Main endpoint. Command summary Command description 11.1 Command procedure 11.2 Initialization commands 11.2.1 Address/Enable 11.2.2 Endpoint Enable 11.2.3 Mode 11.2.4 11.2.4.1 Configuration register 11.3 Data flow commands 11.3.1 Read Interrupt register 11.3.2 Select Endpoint. 11.3.3 Read Endpoint Status. 11.3.4 Read Last Transaction Status register 11.3.5 Read Buffer. 11.3.6 Write Buffer. 11.3.7 Clear Buffer. 11.3.8 Validate Buffer 11.3.9 Endpoint Status 11.3.10 Acknowledge Setup 11.4 General commands 11.4.1 Send Resume 11.4.2 Read Current Frame Number 19.1 19.2 19.3 19.4 19.5 22.1 22.2 22.3 22.4 Interrupt modes Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Test information. Package outline Soldering Introduction soldering surface mount packages Reflow soldering. Wave soldering. Manual soldering Package related soldering information Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers. Trademarks Contact information Tables Figures Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
Koninklijke Philips Electronics N.V. 2006.
rights reserved.
more information, please visit: sales office addresses, email Date release: 2006 Document identifier: PDIUSBD12_9
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