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Am29DL640G
RETIRED PRODUCT
This product been retired recommended designs. current designs, S29JL064H (for TSOP packages) S29PL064J (for FBGA packages) supersede AM29DL640G factory-recommended migration path. Please refer each respective datasheets specifications ordering information. Availability this document retained reference historical purposes only.
April 2005
following document specifies Spansion memory products that offered both Advanced Micro Devices Fujitsu. Although document marked with name company that originally developed specification, these products will offered customers both Fujitsu.
Continuity Specifications
There change this datasheet result offering device Spansion product. changes that have been made result normal datasheet improvement noted document revision summary, where supported. Future routine revisions will occur when appropriate, changes will noted revision summary.
More Information
Please contact your local Fujitsu sales office additional information about Spansion memory solutions.
Publication Number 25693
Revision
Amendment
Issue Date June 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29DL640G
Megabit 8-Bit/4 16-Bit) CMOS Volt-only, Simultaneous Read/Write Flash Memory
This product been retired recommended designs. current designs, S29JL064H (for TSOP packages) S29PL064J (for FBGA packages) supersede AM29DL640G factory-recommended migration path. Please refer each respective datasheets specifications ordering information. Availability this document retained reference historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations Data continuously read from bank while executing erase/program functions another bank. Zero latency between read write operations Flexible Bank architecture Read occur three banks being written erased. Four banks grouped customer achieve desired bank divisions.
Ultra power consumption (typical values) active read current active read current standby automatic sleep mode Minimum million erase cycles guaranteed sector year data retention 125°C Reliable operation life system
SOFTWARE FEATURES
Data Management Software (DMS) AMD-supplied software manages data programming, enabling EEPROM emulation Eases historical sector erase flash limitations Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume Suspends erase operations allow reading from other sectors same bank Data# Polling Toggle Bits Provides software method detecting status program erase cycles Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences
Boot Sectors bottom boot sectors same device combination sectors erased Manufactured 0.17 process technology SecSi(Secured Silicon) Sector: Extra Byte sector Factory locked identifiable: bytes available secure, random factory Electronic Serial Number; verifiable factory locked through autoselect function. ExpressFlash option allows entire sector available factory-secured data Customer lockable: One-time programmable only. Once locked, data cannot changed Zero Power Operation Sophisticated power management circuits reduce power consumed during inactive periods nearly zero. Compatible with JEDEC standards Pinout software compatible with single-power-supply flash standard
HARDWARE FEATURES
Ready/Busy# output (RY/BY#) Hardware method detecting program erase cycle completion Hardware reset (RESET#) Hardware method resetting internal state machine read mode WP#/ACC input Write protect (WP#) function protects sectors 140, 141, regardless sector protect status Acceleration (ACC) function accelerates program timing Sector protection Hardware method locking sector, either in-system using programming equipment, prevent program erase operation within that sector Temporary Sector Unprotect allows changing data protected sectors in-system
Publication# 25693 Rev: Amendment Issue Date: June 2005
PACKAGE OPTIONS
63-ball Fine Pitch 64-ball Fortified 48-pin TSOP
PERFORMANCE CHARACTERISTICS
High performance Access time fast Program time: µs/word typical utilizing Accelerate function
Refer AMD's Website (www.amd.com) latest information.
GENERAL DESCRIPTION
Am29DL640G megabit, volt-only flash memory device, organized 4,194,304 words bits each 8,388,608 bytes bits each. Word mode data appears DQ15-DQ0; byte mode data appears DQ7-DQ0. device designed programmed in-system with standard volt supply, also programmed standard EPROM programmers. device available with access time offered 48-pin TSOP, 63-ball Fine-Pitch BGA, 64-ball Fortified packages. Standard control pins-chip enable (CE#), write enable (WE#), output enable (OE#)-control normal read write operations, avoid contention issues. device requires only single volt power supply both read write functions. Internally generated regulated voltages provided program erase operations. Factory locked parts provide several options. SecSi Sector store secure, random byte (Electronic Serial Number), customer code (programmed through AMD's ExpressFlash service), both. Customer Lockable parts utilize SecSi Sector bonus space, reading writing like other flash sector, permanently lock their code there. (Data Management Software) allows systems easily take advantage advanced architecture simultaneous read/write product line allowing removal EEPROM devices. will also allow system software simplified, will perform functions necessary modify data file structures, opposed single-byte modifications. write update particular piece data phone number configuration data, example), user only needs state which piece data updated, where updated data located system. This user-written software must keep track data location, status, logical physical translation data onto Flash memory device memory devices), more. Using DMS, user-written software does need interface with Flash memory directly. Instead, user's software accesses Flash memory calling only functions. provides this software simplify system design software integration efforts. device offers complete compatibility with JEDEC single-power-supply Flash command standard. Commands written command register using standard microprocessor write timings. Reading data device similar reading from other Flash EPROM devices. host system detect whether program erase operation complete using device status bits: RY/BY# pin, (Data# Polling) DQ6/DQ2 (toggle bits). After program erase cycle been completed, device automatically returns read mode. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device fully erased when shipped from factory. Hardware data protection measures include detector that automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memory. This achieved in-system programming equipment. device offers power-saving features. When addresses have been stable specified amount time, device enters automatic sleep mode. system also place device into standby mode. Power consumption greatly reduced both modes.
Simultaneous Read/Write Operations with Zero Latency
Simultaneous Read/Write architecture provides simultaneous operation dividing memory space into four banks, banks with small large sectors, banks large sectors. Sector addresses fixed, system software used form user-defined bank groups. During Erase/Program operation, three non-busy banks read from. Note that only banks operate simultaneously. device improve overall system performance allowing host system program erase bank, then immediately simultaneously read from other bank, with zero latency. This releases system from waiting completion program erase operations. Am29DL640G organized both bottom boot sector configuration.
Bank Bank Bank Bank Bank Megabits Sector Sizes Eight Kbyte/4 Kword, Fifteen Kbyte/32 Kword Forty-eight Kbyte/32 Kword Forty-eight Kbyte/32 Kword Eight Kbyte/4 Kword, Fifteen Kbyte/32 Kword
Am29DL640G Features
SecSi(Secured Silicon) Sector extra byte sector capable being permanently locked customers. SecSi Indicator (DQ7) permanently part factory locked, customer lockable. This way, customer lockable parts never used replace factory locked part.
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TABLE CONTENTS
Product Selector Guide Block Diagram Connection Diagrams Connection Diagrams Special Handling Instructions Packages Description. Logic Symbol Ordering Information Device Operations
Table Am29DL640G Device Operations
Erase Suspend/Erase Resume Commands
Table Am29DL640G Command Definitions
Write Operation Status DQ7: Data# Polling
Figure Data# Polling Algorithm
RY/BY#: Ready/Busy#. DQ6: Toggle
Figure Toggle Algorithm.
Word/Byte Configuration Requirements Reading Array Data Writing Commands/Command Sequences Accelerated Program Operation Autoselect Functions Simultaneous Read/Write Operations with Zero Latency Standby Mode Automatic Sleep Mode RESET#: Hardware Reset Output Disable Mode
Table Am29DL640G Sector Architecture Table Bank Address Table SecSiSector Addresses
DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Table Write Operation Status
Absolute Maximum Ratings.
Figure Maximum Negative Overshoot Waveform Figure Maximum Positive Overshoot Waveform.
Characteristics
Figure ICC1 Current Time (Showing Active Automatic Sleep Currents) Figure Typical ICC1 Frequency
Test Conditions.
Figure Test Setup. Figure Input Waveforms Measurement Levels
Autoselect Mode.
Table Am29DL640G Autoselect Codes, (High Voltage Method)
Characteristics Read-Only Operations
Figure Read Operation Timings
Sector/Sector Block Protection Unprotection
Table Am29DL640G Boot Sector/Sector Block Addresses Protection/Unprotection
Hardware Reset (RESET#)
Figure Reset Timings
Write Protect (WP#)
Table WP#/ACC Modes
Word/Byte Configuration (BYTE#)
Figure BYTE# Timings Read Operations. Figure BYTE# Timings Write Operations.
Temporary Sector Unprotect
Figure Temporary Sector Unprotect Operation. Figure In-System Sector Protect/Unprotect Algorithms
Erase Program Operations
Figure Program Operation Timings. Figure Accelerated Program Timing Diagram. Figure Chip/Sector Erase Operation Timings Figure Back-to-back Read/Write Cycle Timings Figure Data# Polling Timings (During Embedded Algorithms). Figure Toggle Timings (During Embedded Algorithms). Figure DQ6.
SecSi(Secured Silicon) Sector Flash Memory Region
Figure SecSi Sector Protect Verify.
Hardware Data Protection Write Inhibit Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit Common Flash Memory Interface (CFI)
Table Query Identification String Table System Interface String.22 Table Device Geometry Definition Table Primary Vendor-Specific Extended Query
Temporary Sector Unprotect
Figure Temporary Sector Unprotect Timing Diagram Figure Sector/Sector Block Protect Unprotect Timing Diagram
Alternate Controlled Erase Program Operations
Figure Alternate Controlled Write (Erase/Program) Operation Timings.
Command Definitions Reading Array Data Reset Command Autoselect Command Sequence Enter SecSiSector/Exit SecSi Sector Command Sequence Byte/Word Program Command Sequence Unlock Bypass Command Sequence
Figure Program Operation
Chip Erase Command Sequence Sector Erase Command Sequence
Figure Erase Operation.
Erase Programming Performance. Latchup Characteristics TSOP Capacitance. Data Retention. Physical Dimensions FBE063-63-Ball Fine-Pitch Ball Grid Array (FBGA) package LAA064-64-Ball Fortified Ball Grid Array (FBGA) package 048-48-Pin Standard TSOP Revision Summary
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Am29DL640G
PRODUCT SELECTOR GUIDE
Part Number Speed Option Standard Voltage Range: 2.7-3.6 Am29DL640G
Access Time (ns), tACC Access (ns), Access (ns),
BLOCK DIAGRAM
BYTE#
A21-A0
Bank Address
Bank Y-gate X-Decoder
A21-A0
RY/BY#
Bank Address
Bank X-Decoder DQ15-DQ0
A21-A0 RESET# BYTE# WP#/ACC DQ0-DQ15 A21-A0 X-Decoder
Bank Address
STATE CONTROL COMMAND REGISTER
Status DQ15-DQ0 Control DQ15-DQ0
Bank Y-gate
X-Decoder A21-A0
Bank Address
Bank
Am29DL640G
DQ15-DQ0
DQ15-DQ0
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CONNECTION DIAGRAMS
RESET# WP#/ACC RY/BY# BYTE# DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10
48-Pin Standard TSOP
RESET#
63-Ball Fine-Pitch (FBGA) View, Balls Facing Down
BYTE# DQ15/A-1 DQ14 DQ12 DQ10 DQ13 DQ11
RY/BY# WP#/ACC
Balls shorted together substrate connected die.
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Am29DL640G
CONNECTION DIAGRAMS
64-Ball Fortified View, Balls Facing Down
RESET#
BYTE# DQ14 DQ12 DQ10
DQ15 DQ13 DQ11
RY/BY# WP#/ACC
Special Handling Instructions Packages
Special handling required Flash Memory products molded packages (TSOP BGA). package
and/or data integrity compromised package body exposed temperatures above 150°C prolonged periods time.
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DESCRIPTION
A21-A0 Addresses DQ14-DQ0 Data Inputs/Outputs (x16-only devices) DQ15/A-1 DQ15 (Data Input/Output, word mode) (LSB Address Input, byte mode) WP#/ACC RESET# BYTE# RY/BY# Chip Enable Output Enable Write Enable Hardware Write Protect/ Acceleration Hardware Reset Pin, Active Selects 8-bit 16-bit mode Ready/Busy Output volt-only single power supply (see Product Selector Guide speed options voltage supply tolerances) Device Ground Connected Internally
LOGIC SYMBOL
A21-A0 DQ15-DQ0 (A-1) WP#/ACC RESET# BYTE# RY/BY#
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Am29DL640G
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination following: Am29DL640G
OPTIONAL PROCESSING Blank Standard Processing 16-byte devices (Contact representative more information) TEMPERATURE RANGE Industrial (-40°C +85°C) Extended (-55°C +125°C) PACKAGE TYPE 48-Pin Thin Small Outline Package (TSOP) Standard Pinout 048) 64-Ball Fortified Ball Grid Array pitch, package (LAA064) 63-Ball Fine-Pitch Ball Grid Array 0.80 pitch, package (FBE063) SPEED OPTION Product Selector Guide Valid Combinations DEVICE NUMBER/DESCRIPTION Am29DL640G Megabit 8-Bit/4 16-Bit) CMOS Flash Memory Volt-only Read, Program, Erase
Valid Combinations TSOP Packages Am29DL640G70 Am29DL640G90 Am29DL640G120 Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Valid Combinations Packages Order Number Am29DL640G70 Am29DL640G90 PCI, PCE, Package Marking D640G70P D640G70V D640G90P D640G90V D640G12P D640G12V
Am29DL640G120
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DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. contents Table register serve inputs internal state machine. state machine outputs dictate function device. Table lists device operations, inputs control levels they require, resulting output. following subsections describe each these operations further detail.
Am29DL640G Device Operations
DQ15-DQ8
Operation Read Write Standby Output Disable Reset Sector Protect (Note Sector Unprotect (Note Temporary Sector Unprotect
RESET#
WP#/ACC (Note (Note (Note
Addresses (Note
BYTE# DOUT High-Z High-Z High-Z
BYTE# DQ8-DQ14 High-Z, DQ15 High-Z High-Z High-Z High-Z
DQ7- DOUT High-Z High-Z High-Z
Legend: Logic VIL, Logic High VIH, 11.5-12.5 Don't Care, Sector Address, Address Data DOUT Data Notes: Addresses A21:A0 word mode (BYTE# VIH), A21:A-1 byte mode (BYTE# VIL). sector protect sector unprotect functions also implemented programming equipment. "Sector/Sector Block Protection Unprotection" section. WP#/ACC VIL, sectors 140, remain protected. WP#/ACC VIH, protection sectors 140, depends whether they were last protected unprotected using method described "Sector/Sector Block Protection Unprotection". WP#/ACC VHH, sectors will unprotected.
Word/Byte Configuration
BYTE# controls whether device data pins operate byte word configuration. BYTE# logic `1', device word configuration, DQ15-DQ0 active controlled OE#. BYTE# logic `0', device byte configuration, only data pins DQ7-DQ0 active controlled OE#. data pins DQ14-DQ8 tri-stated, DQ15 used input (A-1) address function.
Requirements Reading Array Data
read array data from outputs, system must drive pins VIL. power control selects device. output control gates array data output pins. should remain BYTE# determines whether device outputs array data words bytes. internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid
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Am29DL640G
addresses device address inputs produce valid data device data outputs. Each bank remains enabled read access until command register contents altered. Refer Read-Only Operations table timing specifications Figure timing diagram. ICC1 Characteristics table represents active current specification reading array data.
required Unlock Bypass mode. Removing from WP#/ACC returns device normal operation. Note that must asserted WP#/ACC operations other than accelerated programming, device damage result. addition, WP#/ACC must left floating unconnected; inconsistent behavior device result. "Write Protect (WP#)" page related information. Autoselect Functions system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ15-DQ0. Standard read cycle timings apply this mode. Refer Autoselect Mode Autoselect Command Sequence sections more information.
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing sectors memory), system must drive VIL, VIH. program operations, BYTE# determines whether device accepts program data bytes words. Refer "Word/Byte Configuration" more information. device features Unlock Bypass mode facilitate faster programming. Once bank enters Unlock Bypass mode, only write cycles required program word byte, instead four. "Byte/Word Program Command Sequence" section details programming data device using both standard Unlock Bypass command sequences. erase operation erase sector, multiple sectors, entire device. Table indicates address space that each sector occupies. Similarly, "sector address" address bits required uniquely select sector. "Command Definitions" section details erasing sector entire chip, suspending/resuming erase operation. device address space divided into four banks. "bank address" address bits required uniquely select bank. ICC2 Characteristics table represents active current specification write mode. Characteristics section contains timing specification tables timing diagrams write operations. Accelerated Program Operation device offers accelerated program operations through function. This functions provided WP#/ACC pin. This function primarily intended allow faster manufacturing throughput factory. system asserts this pin, device automatically enters aforementioned Unlock Bypass mode, temporarily unprotects protected sectors, uses higher voltage reduce time required program operations. system would two-cycle program command sequence
Simultaneous Read/Write Operations with Zero Latency
This device capable reading data from bank memory while programming erasing other bank memory. erase operation also suspended read from program another location within same bank (except sector being erased). Figure shows read write cycles initiated simultaneous operation with zero latency. ICC6 ICC7 Characteristics table represent current specifications read-while-program read-while-erase, respectively.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input. device enters CMOS standby mode when RESET# pins both held (Note that this more restricted voltage range than VIH.) RESET# held VIH, within device will standby mode, standby current will greater. device requires standard access time read access when device either these standby modes, before ready read data. device deselected during erasure programming, device draws active current until operation completed. Characteristics table represents standby current specification.
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Automatic Sleep Mode
automatic sleep mode minimizes Flash device energy consumption. device automatically enables this mode when addresses remain stable automatic sleep mode independent CE#, WE#, control signals. Standard address access timings provide data when addresses changed. While sleep mode, output data latched always available system. Characteristics table represents automatic sleep mode current specification.
draws CMOS standby current (ICC4). RESET# held within VSS±0.3 standby current will greater. RESET# tied system reset circuitry. system reset would thus also reset Flash memory, enabling system read boot-up firmware from Flash memory. RESET# asserted during program erase operation, RY/BY# remains (busy) until internal reset operation complete, which requires time tREADY (during Embedded Algorithms). system thus monitor RY/BY# determine whether reset operation complete. RESET# asserted when program erase operation executing (RY/BY# "1"), reset operation completed within time tREADY (not during Embedded Algorithms). system read data after RESET# returns VIH. Refer Characteristics tables RESET# parameters Figure timing diagram.
RESET#: Hardware Reset
RESET# provides hardware method resetting device reading array data. When RESET# driven least period tRP, device immediately terminates operation progress, tristates output pins, ignores read/write commands duration RESET# pulse. device also resets internal state machine reading array data. operation that interrupted should reinitiated once device ready accept another command sequence, ensure data integrity. Current reduced duration RESET# pulse. When RESET# held VSS±0.3 device Table
Bank Sector SA10 Bank SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Sector Address A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001101xxx 0001111xxx
Output Disable Mode
When input VIH, output from device disabled. output pins placed high impedance state.
Am29DL640G Sector Architecture
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh (x16) Address Range 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh
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Am29DL640G
Table
Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 Bank SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
Am29DL640G Sector Architecture (Continued)
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 100000h-00FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh (x16) Address Range 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh F9000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
Sector Address A21-A12 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011000xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0101011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0100100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx
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Table
Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 Bank SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
Am29DL640G Sector Architecture (Continued)
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh (x16) Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-28FFFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2FFFFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh
Sector Address A21-A12 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx
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Am29DL640G
Table
Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
Am29DL640G Sector Architecture (Continued)
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7F1FFFh 7F2000h-7F3FFFh 7F4000h-7F5FFFh 7F6000h-7F7FFFh 7F8000h-7F9FFFh 7FA000h-7FBFFFh 7FC000h-7FDFFFh 7FE000h-7FFFFFh (x16) Address Range 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
Sector Address A21-A12 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Note: address range A21:A-1 byte mode (BYTE#=VIL) A21:A0 word mode (BYTE#=VIH).
Table
Bank
Bank Address
A21-A19 001, 010, 100, 101,
Table
Device Am29DL640G
SecSiSector Addresses
Sector Size bytes (x8) Address Range 000000h-0000FFh (x16) Address Range 00000h-0007Fh
Autoselect Mode
autoselect mode provides manufacturer device identification, sector protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programm algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires address Address pins must shown Table addition, when verifying sector protection, sector address must appear appropriate highest order address bits (see
Table Table shows remaining address bits that don't care. When necessary bits have been required, programming equipment then read corresponding identifier code DQ7-DQ0. However, autoselect codes also accessed in-system through command register, instances when Am29DL640 erased programmed system without access high voltage pin. command sequence illustrated Table Note that Bank Address (BA) address bits A21, A20, asserted during third write cycle autoselect command, host system read autoselect data from that bank then immediately read array data from other bank, without exiting autoselect mode.
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access autoselect codes in-system, host system issue autoselect command command register, shown Table This method Table
does require Refer Autoselect Command Sequence section more information.
Am29DL640G Autoselect Codes, (High Voltage Method)
DQ15 BYTE# BYTE# (protected), (unprotected) (factory locked), (not factory locked)
Description Manufacturer Device Read Cycle Read Cycle Read Cycle
Sector Protection Verification SecSi Indicator (DQ7)
Legend: Logic VIL, Logic High VIH, Bank Address, Sector Address, Don't care.
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Sector/Sector Block Protection Unprotection
(Note: following discussion, term "sector" applies both sectors sector blocks. sector block consists more adjacent sectors that protected unprotected same time (see Table hardware sector protection feature disables both program erase operations sector. hardware sector unprotection feature re-enables both program erase operations previously protected sectors. Sector protection/unprotection implemented methods. Table Am29DL640G Boot Sector/Sector Block Addresses Protection/Unprotection
Sector SA8-SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX, 0000010XXX, 0000011XXX, 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX Sector/ Sector Block Size Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes (3x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes
Sector SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 SA131-SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
A21-A12 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX, 1111101XXX, 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111101 1111111111
Sector/ Sector Block Size (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (3x64) Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
Sector protection/sector unprotection requires RESET# only, implemented either in-system programming equipment. Figure shows algorithms Figure shows timing diagram. sector unprotect, unprotected sectors must first protected prior first sector unprotect write cycle. Note that sector unprotect algorithm unprotects sectors parallel. previously protected sectors must individually re-protected. change data protected sectors efficiently, temporary sector unprotect function available. "Temporary Sector Unprotect". device shipped with sectors unprotected. offers option programming protecting sectors factory prior shipping device through AMD's ExpressFlashService. Contact representative details. possible determine whether sector protected unprotected. Autoselect Mode section details.
Write Protect (WP#)
Write Protect function provides hardware method protecting without using VID. This function provided WP#/ACC pin. system asserts WP#/ACC pin, device disables program erase functions sectors 140, 141, independently whether those sectors were protected unprotected using method described "Sector/Sector Block Protection Unprotection".
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system asserts WP#/ACC pin, device reverts whether sectors 140, were last protected unprotected. That sector protection unprotection these sectors depends whether they were last protected unprotected using method described "Sector/Sector Block Protection Unprotection". Note that WP#/ACC must left floating unconnected; inconsistent behavior device result. Table
Input Voltage
Temporary Sector Unprotect
(Note: following discussion, term "sector" applies both sectors sector blocks. sector block consists more adjacent sectors that protected unprotected same time (see Table This feature allows temporary unprotection previously protected sectors change data in-system. Sector Unprotect mode activated setting RESET# VID. During this mode, formerly protected sectors programmed erased selecting sector addresses. Once removed from RESET# pin, previously protected sectors protected again. Figure shows algorithm, Figure shows timing diagrams, this feature. WP#/ACC sectors 140, will remain protected during Temporary sector Unprotect mode.
WP#/ACC Modes
Device Mode
Disables programming erasing SA0, SA1, SA140, SA141 Enables programming erasing SA0, SA1, SA140, SA141 Enables accelerated programming (ACC). "Accelerated Program Operation" page
START
RESET# (Note Perform Erase Program Operations
RESET#
Temporary Sector Unprotect Completed (Note
Notes: protected sectors unprotected WP#/ACC VIL, sectors 140, will remain protected). previously protected sectors protected once again.
Figure
Temporary Sector Unprotect Operation
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Am29DL640G
START PLSCNT RESET# Wait Protect sectors: indicated portion sector protect algorithm must performed unprotected sectors prior issuing first sector unprotect address
START PLSCNT RESET# Wait
Temporary Sector Unprotect Mode
First Write Cycle 60h? sector address Sector Protect: Write sector address with Wait Verify Sector Protect: Write sector address with Read from sector address with
First Write Cycle 60h? sectors protected? first sector address Sector Unprotect: Write sector address with
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT
Wait Verify Sector Unprotect: Write sector address with
PLSCNT Data 01h?
Increment PLSCNT
Read from sector address with next sector address
Device failed
Protect another sector? Remove from RESET#
PLSCNT 1000?
Data 00h?
Device failed Write reset command
Last sector verified?
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove from RESET#
Write reset command Sector Unprotect complete
Figure
In-System Sector Protect/Unprotect Algorithms
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SecSi(Secured Silicon) Sector Flash Memory Region
SecSi (Secured Silicon) Sector feature provides Flash memory region that enables permanent part identification through Electronic Serial Number (ESN). SecSi Sector bytes length, uses SecSi Sector Indicator (DQ7) indicate whether SecSi Sector locked when shipped from factory. This permanently factory cannot changed, which prevents cloning factory locked part. This ensures security once product shipped field. offers device with SecSi Sector either ocke tory-locked version always protected when shipped from factory, SecSi (Secured Silicon) Sector Indicator permanently "1." customer-lockable version shipped with SecSi Sector unprotected, allowing customers utilize that sector manner they choose. customer-lockable version SecSi (Secured Silicon) Sector Indicator permanently "0." Thus, SecSi Sector Indicator prevents customer-lockable devices from being used replace devices that factory locked. system accesses SecSi Sector Secure through command sequence (see "Enter SecSiSector/Exit SecSi Sector Command Sequence"). After system written Enter SecSi Sector command sequence, read SecSi Sector using addresses normally occupied boot sectors. This mode operation continues until system issues Exit SecSi Sector command sequence, until power removed from device. power-up, following hardware reset, device reverts sending commands first bytes Sector Note that function unlock bypass modes available when SecSi Sector enabled. Factory Locked: SecSi Sector Programmed Protected Factory factory locked device, SecSi Sector protected when device shipped from factory. SecSi Sector cannot modified way. device preprogrammed with both random number secure ESN. 8-word random number addresses 000000h-000007h word mode 000000h-00000Fh byte mode). secure
programmed next words addresses 000008h-00000Fh 000010h-00001Fh byte mode). device available preprogrammed with following: random, secure only Customer code through ExpressFlash service Both random, secure customer code through ExpressFlash service. Customers have their code programmed through ExpressFlash service. programs customer's code, with without random ESN. devices then shipped from AMD's factory with SecSi Sector permanently locked. Contact representative details using AMD's ExpressFlash service. Customer Lockable: SecSi Sector Programmed Protected Factory security feature required, SecSi Sector treated additional Flash memory space. SecSi Sector read number times, programmed locked only once. Note that accelerated programming (ACC) unlock bypass functions available when programming SecSi Sector. SecSi Sector area protected using following procedures: Write three-cycle Enter SecSi Sector Region command sequence, then follow in-system sector protect algorithm shown Figure except that RESET# either VID. This allows in-system protection SecSi Sector Region without raising device high voltage. Note that this method only applicable SecSi Sector. verify protect/unprotect status SecSi Sector, follow algorithm shown Figure Once SecSi Sector locked verified, system must write Exit SecSi Sector Region command sequence return reading writing remainder array. SecSi Sector lock must used with caution since, once locked, there procedure available unlocking SecSi Sector area none bits SecSi Sector memory space modified way.
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must logical zero while logical one.
START RESET# Wait Write address data 00h, SecSi Sector unprotected. data 01h, SecSi Sector protected.
Power-Up Write Inhibit during power device does accept commands rising edge WE#. internal state machine automatically reset read mode power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
Common Flash Interface (CFI) specification outlines device host system software interrogation handshake, which allows specific vendor-specified software algorithms used entire families devices. Software support then device-independent, JEDEC ID-independent, forward- backward-compatible specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. This device enters Query mode when system writes Query command, 98h, address word mode address byte mode), time device ready read array data. system read information addresses given Tables 8-11. terminate reading data, system must write reset command.The Query mode accessible when device executing Embedded Program embedded Erase algorithm. system also write query command when device autoselect mode. device enters query mode, system read data addresses given Tables 8-11. system must write reset command return device reading array data. further information, please refer Specification Publication 100, available World Wide http://www.amd.com/flash/cfi. Alternatively, contact representative copies these documents.
Remove from RESET#
Write SecSi Sector address with Read from SecSi Sector address with
Write reset command SecSi Sector Protect Verify complete
Figure
SecSi Sector Protect Verify
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes (refer Table command definitions). addition, following hardware data protection measures prevent accidental erasure programming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise. Write Inhibit When less than VLKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets read mode. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins prevent unintentional writes when greater than VLKO. Write Pulse "Glitch" Protection Noise pulses less than (typical) OE#, initiate write cycle. Logical Inhibit Write cycles inhibited holding VIL, VIH. initiate write cycle,
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Table
Addresses (Word Mode) Addresses (Byte Mode) Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
Query Identification String
Description Query Unique ASCII string "QRY"
Primary Command Address Primary Extended Table Alternate Command (00h none exists) Address Alternate Extended Table (00h none exists)
Table
Addresses (Word Mode) Addresses (Byte Mode) Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
System Interface String
Description Min. (write/erase) D7-D4: volt, D3-D0: millivolt Max. (write/erase) D7-D4: volt, D3-D0: millivolt Min. voltage (00h present) Max. voltage (00h present) Typical timeout single byte/word write Typical timeout Min. size buffer write (00h supported) Typical timeout individual block erase Typical timeout full chip erase (00h supported) Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical (00h supported)
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Table
Addresses (Word Mode) Addresses (Byte Mode) Data 0017h 0002h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 007Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description Device Size byte Flash Device Interface description (refer publication 100) Max. number byte multi-byte write (00h supported) Number Erase Block Regions within device Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
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Table
Addresses (Word Mode) Addresses (Byte Mode)
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications silicon) Minor version number, ASCII (reflects modifications table) Address Sensitive Unlock (Bits 1-0) Required, Required Silicon Revision Number (Bits 7-2) Erase Suspend Supported, Read Only, Read Write Sector Protect Supported, Number sectors group Sector Temporary Unprotect Supported, Supported Sector Protect/Unprotect scheme =29F040 mode, 29F016 mode, 29F400, 29LV800 mode Simultaneous Operation Supported, Number Sectors (excluding Bank Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page, Word Page (Acceleration) Supply Minimum Supported, D7-D4: Volt, D3-D0: (Acceleration) Supply Maximum Supported, D7-D4: Volt, D3-D0: Top/Bottom Boot Sector Flag Uniform device, Kbyte Sectors, Bottom Boot with Write Protect, Bottom Boot Device, Boot Device, Both Bottom Program Suspend supported, Supported, tested Bank Organization Data zero, Number Banks Bank Region Information Number Sectors Bank Bank Region Information Number Sectors Bank Bank Region Information Number Sectors Bank Bank Region Information Number Sectors Bank
Data 0050h 0052h 0049h 0031h 0033h 0004h
0002h 0001h 0001h
0004h
0077h 0000h 0000h 0085h 0095h
0004h
0001h 0004h 0017h 0030h 0030h 0017h
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Am29DL640G
COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Table defines valid register command sequences. Writing incorrect address data values writing them improper sequence place device unknown state. reset command required return device read array data. addresses latched falling edge CE#, whichever happens later. data latched rising edge CE#, whichever happens first. Refer Characteristics section timing diagrams. before programming begins. This resets bank which system writing read mode. program command sequence written bank that Erase Suspend mode, writing reset suspend-read mode. Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return read mode. bank entered autoselect mode while Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. goes high during program erase operation, writing reset command returns banks read mode erase-suspend-read mode that bank Erase Suspend).
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. Each bank ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, corresponding enters eras e-suspend-read mode, after which system read data from non-erase-suspended sector within same bank. system read array data using standard read timing, except that reads address within erase-suspended sectors, device outputs status data. After completing programming operation Erase Suspend mode, system once again read array data with same exception. Erase Suspend/Erase Resume Commands section more information. system must issue reset command return bank read erase-suspend-read) mode goes high during active program erase operation, bank autoselect mode. next section, Reset Command, more information. also Requirements Reading Array Data Device Operations section more information. Read-Only Operations table provides read parameters, Figure shows timing diagram.
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer device codes, determine whether sector protected. autoselect command sequence written address within bank that either read erase-suspend-read mode. autoselect command written while device actively programming erasing other bank. autoselect command sequence initiated first writing unlock cycles. This followed third write cycle that contains bank address autoselect command. bank then enters autoselect mode. system read number autoselect codes without reinitiating command sequence. Table shows address data requirements. determine sector protection information, system must write appropriate bank address (BA) sector address (SA). Table shows address range bank number associated with each sector. system must write reset command return read mode erase-suspend-read mode bank previously Erase Suspend).
Reset Command
Writing reset command resets banks read erase-suspend-read mode. Address bits don't cares this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets bank which system writing read mode. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence
Enter SecSiSector/Exit SecSi Sector Command Sequence
SecSi Sector region provides secured data area containing random, sixteen-byte electronic serial number (ESN). system access SecSi Sector region issuing three-cycle Enter SecSi Sector command sequence. device continues access SecSi Sector region until system
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sues four-cycle Exit SecSi Sector command sequence. Exit SecSi Sector command sequence returns device normal operation. SecSi Sector accessible when device executing Embedded Program embedded Erase algorithm. Table shows address data requirements both command sequences. also "SecSi(Secured Silicon) Sector Flash Memory Region" further information. Note that function unlock bypass modes available when SecSi Sector enabled.
status bits indicate operation successful. However, succeeding read will show that data still "0." Only erase operations convert "1." Unlock Bypass Command Sequence unlock bypass feature allows system program bytes words bank faster than using standard program command sequence. unlock bypass command sequence initiated first writing unlock cycles. This followed third write cycle containing unlock bypass command, 20h. That bank then enters unlock bypass mode. two-cycle unlock bypass program command sequence that required program this mode. first cycle this sequence contains unlock bypass program command, A0h; second cycle contains program address data. Additional data programmed same manner. This mode dispenses with initial unlock cycles required standard program command sequence, resulting faster total programming time. Table shows requirements command sequence. During unlock bypass mode, only Unlock Bypass Program Unlock Bypass Reset commands valid. exit unlock bypass mode, system must issue two-cycle unlock bypass reset command sequence. Table device offers accelerated program operations through WP#/ACC pin. When system asserts WP#/ACC pin, device automatically enters Unlock Bypass mode. system then write two-cycle Unlock Bypass program command sequence. device uses higher voltage WP#/ACC accelerate operation. Note that WP#/ACC must operation other than accelerated programming, device damage result. addition, WP#/ACC must left floating unconnected; inconsistent behavior device result. Figure illustrates algorithm program operation. Refer Erase Program Operations table Characteristics section parameters, Figure timing diagrams.
Byte/Word Program Command Sequence
system program device word byte, depending state BYTE# pin. Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verifies programmed cell margin. Table shows address data requirements byte program command sequence. When Embedded Program algorithm complete, that bank then returns read mode addresses longer latched. system determine status program operation using DQ7, DQ6, RY/BY#. Refer Write Operation Status section information these status bits. commands written device during Embedded Program Algorithm ignored. Note that hardware reset immediately terminates program operation. SecSi sector, autoselect, allowed. program command sequence should reinitiated once that bank returned read mode, ensure data integrity. Note that SecSi Sector, autoselect, functions unavailable when program operation progress. Programming allowed sequence across sector boundaries. cannot programmed from back "1." Attempting cause that bank cause
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START
commands written during chip erase operation ignored. However, note that hardware reset immediately terminates erase operation. that occurs, chip erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
Write Program Command Sequence
Embedded Program algorithm progress
Data Poll from System
Sector Erase Command Sequence
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock cycles written, then followed address sector erased, sector erase command. Table shows address data requirements sector erase command sequence. device does require system preprogram prior erase. Embedded Erase algorithm automatically programs verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase time-out tSEA occurs. During time-out period, additional sector addresses sector erase commands written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than otherwise erasure begin. sector erase address command following exceeded time-out accepted. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. command other than time-out period resets that bank read mode. SecSi sector, autoselect, available. system must rewrite command sequence additional addresses commands. system monitor determine sector erase timer timed (See section DQ3: Sector Erase Timer.). time-out begins from rising edge final pulse command sequence. When Embedded Erase algorithm complete, bank returns reading array data addresses longer latched. Note that while Embedded Erase operation progress, system read data from non-erasing bank. system
Verify Data?
Increment Address
Last Address?
Programming Completed
Note: Table program command sequence.
Figure
Program Operation
Chip Erase Command Sequence
Chip erase cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Table shows address data requirements chip erase command sequence. When Embedded Erase algorithm complete, that bank returns read mode addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2, RY/BY#. Refer Write Operation Status section information these status bits. Note that SecSi Sector, autoselect, functions unavailable when program operation progress.
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termine status erase operation reading DQ7, DQ6, DQ2, RY/BY# erasing bank. Refer Write Operation Status section information these status bits. Once sector erase operation begun, only Erase Suspend command valid. other commands ignored. However, note that hardware reset immediately terminates erase operation. that occurs, sector erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
erasure. bank address required when writing this command. This command valid only during sector erase operation, including tSEA time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. When Erase Suspend command written during sector erase operation, device requires maximum tSEL suspend erase operation. However, when Erase Suspend command written during sector erase time-out, device immediately terminates time-out period suspends erase operation. Addresses "don't-cares" when writing Erase suspend command. After erase operation been suspended, bank enters erase-suspend-read mode. system read data from program data sector selected erasure. (The device "erase suspends" sectors selected erasure.) Reading address within erase-suspended sectors produces status information DQ7-DQ0. system DQ7, together, determine sector actively erasing erase-suspended. Refer Write Operation Status section information these status bits. After erase-suspended program operation complete, bank returns erase-suspend-read mode. system determine status program operation using status bits, just standard Byte Program operation. Refer Write Operation Status section more information. erase-suspend-read mode, system also issue autoselect command sequence. device allows reading autoselect codes even addresses within erasing sectors, since codes stored memory array. When device exits autoselect mode, device reverts Erase Suspend mode, ready another valid operation. Refer Autoselect Mode Autoselect Command Sequence sections details. resume sector erase operation, system must write Erase Resume command (address bits don't care). bank address erase-suspended bank required when writing this command. Further writes Resume command ignored. Another Erase Suspend command written after chip resumed erasing.
START
Write Erase Command Sequence (Notes
Data Poll Erasing Bank from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
Notes: Table erase command sequence. section information sector erase timer.
Figure
Erase Operation
Erase Suspend/Erase Resume Commands
Erase Suspend command, B0h, allows system interrupt sector erase operation then read data from, program data sector selected
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Am29DL640G
Table
Command Sequence (Note Read (Note Reset (Note Autoselect (Note Manufacturer Device (Note SecSi Sector Factory Protect (Note Sector/Sector Block Protect Verify (Note Word Byte Word Byte Word Byte Word Byte Cycles First Addr Data
Am29DL640G Command Definitions
Second Addr Data Cycles (Notes 2-5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data
(BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA
(BA)X00
(BA)X0F (BA)X1E
(BA)X01 (BA)X0E (BA)X02 (BA)X1C (BA)X03 81/01 (BA)X06 (SA)X02 00/01 (SA)X04
Word Byte Word Exit SecSi Sector Region Byte Word Program Byte Word Unlock Bypass Byte Unlock Bypass Program (Note Unlock Bypass Reset (Note Word Chip Erase Byte Word Sector Erase Byte Erase Suspend (Note Erase Resume (Note Word Query (Note Byte Enter SecSi Sector Region
Legend: Don't care Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge pulse, whichever happens later.
Data programmed location Data latches rising edge pulse, whichever happens first. Address sector verified autoselect mode) erased. Address bits A21-A12 uniquely select sector. Refer Table information sector addresses. Address bank that being switched autoselect mode, bypass mode, being erased. A21-A19 uniquely select bank.
Notes: Table description operations. values hexadecimal. Except read cycle fourth cycle autoselect command sequence, cycles write cycles. Data bits DQ15-DQ8 don't care command sequences, except Unless otherwise noted, address bits A21-A11 don't cares unlock command cycles, unless required. unlock command cycles required when bank reading array data. Reset command required return read mode erase-suspend-read mode previously Erase Suspend) when bank autoselect mode, goes high (while bank providing status information). fourth cycle autoselect command sequence read cycle. system must provide bank address obtain manufacturer device SecSi Sector factory protect information. Data bits DQ15-DQ8 don't care. Autoselect Command Sequence section more information.
device must read across fourth, fifth, sixth cycles. data factory locked factory locked. data unprotected sector/sector block protected sector/sector block. Unlock Bypass command required prior Unlock Bypass Program command. Unlock Bypass Reset command required return read mode when bank unlock bypass mode. system read program non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation, requires bank address. Erase Resume command valid only during Erase Suspend mode, requires bank address. Command valid when device ready read array data when device autoselect mode.
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WRITE OPERATION STATUS
device provides several bits determine status program erase operation: DQ2, DQ3, DQ5, DQ6, DQ7. Table following subsections describe function these bits. each offer method determining whether program erase operation complete progress. device also provides hardware-based output signal, RY/BY#, determine whether Embedded Program Erase operation progress been completed. vice completed program erase operation DQ15-DQ0 DQ7-DQ0 x8-only device) will appear successive read cycles. Table shows outputs Data# Polling DQ7. Figure shows Data# Polling algorithm. Figure Characteristics section shows Data# Polling timing diagram.
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host system whether Embedded Program Erase algorithm progress completed, whether bank Erase Suspend. Data# Polling valid after rising edge final pulse command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. This status also applies programming during Erase Suspend. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within protected sector, Data# Polling active approximately tPSP then that bank returns read mode.
START
Read DQ7-DQ0 Addr
Data?
During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, bank enters Erase Suspend mode, Data# Polling produces DQ7. system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately tASP then bank returns read mode. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. However, system reads address within protected sector, status valid. When system detects changed from complement true data, read valid data DQ15-DQ0 DQ7-DQ0 x8-only device) following read cycles. Just prior completion Embedded Program Erase operation, change asynchronously with DQ15-DQ8 (DQ7-DQ0 x8-only device) while Output Enable (OE#) asserted low. That device change from providing status infor mation valid data DQ7. Depending when system samples output, read status valid data. Even
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address sector address within sector being erased. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure Data# Polling Algorithm
June 2005
Am29DL640G
RY/BY#: Ready/Busy#
RY/BY# dedicated, open-drain output which indicates whether Embedded Algorithm progress complete. RY/BY# status valid after rising edge final pulse command sequence. Since RY/BY# open-drain output, several RY/BY# pins tied together parallel with pull-up resistor VCC. output (Busy), device actively erasing programming. (This includes programming Erase Suspend mode.) output high (Ready), device read mode, standby mode, banks erase-suspend-read mode. Table shows outputs RY/BY#.
also toggles during erase-suspend-program mode, stops toggling once Embedded Program algorithm complete. Table shows outputs Toggle DQ6. Figure shows toggle algorithm. Figure Characteristics" section shows toggle timing diagrams. Figure shows differences between graphical form. also subsection DQ2: Toggle
START
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address, valid after rising edge final pulse command sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address cause toggle. system either control read cycles. When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately tASP then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erase-suspended. When device actively erasing (that Embedded Erase algorithm progress), toggles. When device enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system (see subsection DQ7: Data# Polling). program address falls within protected sector, toggles approximately tPSP after program command sequence written, then returns reading array data.
Read Byte (DQ7-DQ0) Address Read Byte (DQ7-DQ0) Address
Toggle Toggle?
Read Byte Twice (DQ7-DQ0) Address
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Note: system should recheck toggle even because toggle stop toggling changes "1." subsections more information.
Figure
Toggle Algorithm
Am29DL640G
June 2005
DQ2: Toggle
"Toggle DQ2, when used with DQ6, indicates whether particular sector actively erasing (that Embedded Erase algorithm progress), whether that sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when system reads addresses within those sectors that have been selected erasure. (The system either control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. DQ6, comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sector mode information. Refer Table compare outputs DQ6. Figure shows toggle algorithm flowchart form, section "DQ2: Toggle explains algorithm. also DQ6: Toggle subsection. Figure shows toggle timing diagram. Figure shows differences between graphical form.
gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (top Figure
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces "1," indicating that program erase cycle successfully completed. device output system tries program location that previously programmed "0." Only erase operation change back "1." Under this condition, device halts operation, when timing limit been exceeded, produces "1." Under both these conditions, system must write reset command return read mode erase-suspend-read mode bank previously erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing sector erase command sequence, system read determine whether erasure begun. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire time-out also applies after each additional sector erase command. When time-out period complete, switches from "1." time between additional sector erase commands from system assumed less than tSEA system need monitor DQ3. also Sector Erase Command Sequence section. After sector erase command written, system should read status (Data# Polling) (Toggle ensure that device accepted command sequence, then read DQ3. "1," Embedded Erase algorithm begun; further commands (except Erase Suspend) ignored until erase operation complete. "0," device will accept additional sector erase commands. ensure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, last command might have been accepted. Table shows status relative other status bits.
Reading Toggle Bits DQ6/DQ2
Refer Figure following discussion. Whenever system initially begins reading toggle status, must read DQ15-DQ0 DQ7-DQ0 x8-only device) least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ15-DQ0 DQ7-DQ0 x8-only device) following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device completed operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling
June 2005
Am29DL640G
Table
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program
Write Operation Status
(Note DQ7# Data DQ7# Toggle Toggle toggle Data Toggle (Note Data Data (Note toggle Toggle Toggle Data RY/BY#
Standard Mode Erase Suspend Mode
Notes: switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. Refer section more information. require valid address when reading status information. Refer appropriate subsection further details. When reading write operation status bits, system must always provide bank address where Embedded Algorithm progress. device outputs array data system addresses non-busy bank.
Am29DL640G
June 2005
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65°C +150°C Ambient Temperature with Power Applied. -65°C +125°C Voltage with Respect Ground (Note .-0.5 +4.0 OE#, RESET# (Note .-0.5 +12.5 WP#/ACC -0.5 +10.5 other pins (Note -0.5 +0.5 Output Short Circuit Current (Note
Notes: Minimum voltage input pins -0.5 During voltage transitions, input pins overshoot -2.0 periods Maximum voltage input pins +0.5 Figure During voltage transitions, input pins overshoot +2.0 periods Figure Minimum input voltage pins OE#, RESET#, WP#/ACC -0.5 During voltage transitions, OE#, WP#/ACC, RESET# overshoot -2.0 periods Figure Maximum input voltage +12.5 which overshoot +14.0 periods Maximum input voltage WP#/ACC +9.5 which overshoot +12.0 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure device absolute maximum rating conditions extended periods affect device reliability. +0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
+2.0 +0.5
Figure Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial Devices Ambient Temperature (TA) -40°C +85°C Extended Devices Ambient Temperature (TA) -55°C +125°C Supply Voltages standard voltage range
Operating ranges define those limits between which functionality device guaranteed.
June 2005
Am29DL640G
CHARACTERISTICS CMOS Compatible
Parameter Symbol ILIT Parameter Description Input Load Current Input Load Current Output Leakage Current Reset Leakage Current Test Conditions VCC, max; 12.5 VOUT VCC, max; RESET= 12.5 VIL, VIH, Byte Mode VIL, VIH, Word Mode Byte Word Byte Word -0.5 -2.0 -100 Lock-Out Voltage (Note 0.85 VCC-0.4 Unit
±1.0
±1.0
ICC1
Active Read Current (Notes
ICC2 ICC3 ICC4 ICC5 ICC6
Active Write Current (Notes VIL, VIH, Standby Current (Note Reset Current (Note Automatic Sleep Mode (Notes Active Read-While-Program Current (Notes Active Read-While-Erase Current (Notes Active Program-While-Erase-Suspended Current (Notes Input Voltage Input High Voltage Voltage WP#/ACC Sector Protect/Unprotect Program Acceleration Voltage Autoselect Temporary Sector Unprotect Output Voltage Output High Voltage CE#, RESET# RESET# VIL,
ICC7
VIL,
ICC8
VIL,
VOH1 VOH2 VLKO
11.5
12.5 0.45
Notes: current listed typically less than mA/MHz, with VIH. Maximum specifications tested with VCCmax. active while Embedded Erase Embedded Program progress. Automatic sleep mode enables power mode when addresses remain stable tACC Typical sleep mode current 100% tested.
Am29DL640G
June 2005
CHARACTERISTICS Zero-Power Flash
Supply Current
1000 1500 2000 Time 2500 3000 3500 4000
Note: Addresses switching
Figure
ICC1 Current Time (Showing Active Automatic Sleep Currents)
Supply Current
Note:
Frequency Figure Typical ICC1 Frequency
June 2005
Am29DL640G
TEST CONDITIONS
Table
Test Condition Output Load Output Load Capacitance, (including capacitance) Input Rise Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 0.0-3.0
Test Specifications
gate Unit
Device Under Test
Note: Diodes IN3064 equivalent
Figure
Test Setup
SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from Changing from Don't Care, Change Permitted Does Apply Changing, State Unknown Center Line High Impedance State (High OUTPUTS
Input
Measurement Level
Output
Figure
Input Waveforms Measurement Levels
Am29DL640G
June 2005
CHARACTERISTICS Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std. tACC Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Notes Output Enable Output High (Notes Output Hold Time From Addresses, OE#, Whichever Occurs First Read tOEH Output Enable Hold Time (Note Toggle Data# Polling CE#, Test Setup Speed Options Unit
Notes: 100% tested. Figure Table test specifications Measurements performed placing termination data with bias VCC/2. time from high data driven VCC/2 taken
Addresses tOEH HIGH Outputs RESET# RY/BY# Output Valid HIGH Addresses Stable tACC
Figure
Read Operation Timings
June 2005
Am29DL640G
CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC tReady tReady tRPD Description RESET# (During Embedded Algorithms) Read Mode (See Note) RESET# (NOT During Embedded Algorithms) Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Standby Mode RY/BY# Recovery Time Speed Options Unit
Note: 100% tested.
RY/BY#
CE#, RESET# tReady
Reset Timings during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# CE#,
RESET#
Figure
Reset Timings
Am29DL640G
June 2005
CHARACTERISTICS Word/Byte Configuration (BYTE#)
Parameter JEDEC Std. tELFL/tELFH tFLQZ tFHQV Description BYTE# Switching High BYTE# Switching Output HIGH BYTE# Switching High Output Active Speed Options Unit
BYTE# tELFL DQ14-DQ0
BYTE# Switching from word byte mode
Data Output (DQ14-DQ0)
Data Output (DQ7-DQ0) Address Input
DQ15/A-1
DQ15 Output tFLQZ tELFH
BYTE# BYTE# Switching from byte word mode
DQ14-DQ0
Data Output (DQ7-DQ0) Address Input tFHQV
Data Output (DQ14-DQ0) DQ15 Output
DQ15/A-1
Figure
BYTE# Timings Read Operations
falling edge last signal
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer Erase/Program Operations table specifications.
Figure
BYTE# Timings Write Operations
June 2005
Am29DL640G
CHARACTERISTICS Erase Program Operations
Parameter JEDEC tAVAV tAVWL tASO tWLAX tAHT tDVWH tWHDX tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tWPH tSR/W tWHWH1 tWHWH1 Description Write Cycle Time (Note Address Setup Time Address Setup Time during toggle polling Address Hold Time Address Hold Time From high during toggle polling Data Setup Time Data Hold Time Output Enable High during toggle polling Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Latency Between Read Write Operations Byte Programming Operation (Note Word Accelerated Programming Operation, Word Byte (Note Sector Erase Operation (Note Setup Time (Note Write Recovery Time from RY/BY# Program/Erase Valid RY/BY# Delay Sector Erase Accept Time-Out Erase Suspend Latency Toggle Time During Programming Within Protected Sector Toggle Time During Sector Protection Speed Options Unit
tWHWH1 tWHWH2
tWHWH1 tWHWH2 tVCS tBUSY tSEA tESL tPSP tASP
Notes: 100% tested. "Erase Programming Performance" section more information.
Am29DL640G
June 2005
CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h Data tBUSY RY/BY# Status DOUT tWPH tWHWH1 Read Status Data (last cycles)
tVCS
Notes: program address, program data, DOUT true data program address. Illustration shows device word mode.
Figure
Program Operation Timings
WP#/ACC
tVHH tVHH
Figure
Accelerated Program Timing Diagram
June 2005
Am29DL640G
CHARACTERISTICS
Erase Command Sequence (last cycles) Addresses 2AAh
555h chip erase
Read Status Data
tWPH
tWHWH2
Data
Chip Erase Progress Complete
tBUSY RY/BY# tVCS
Notes: sector address (for Sector Erase), Valid Address reading status data (see "Write Operation Status". These waveforms word mode.
Figure
Chip/Sector Erase Operation Timings
Am29DL640G
June 2005
CHARACTERISTICS
Addresses
Valid
Valid
Valid
Valid
tACC tOEH tWPH Data
Valid
tCPH
tGHWL
Valid Valid Valid
tSR/W
Controlled Write Cycle Read Cycle CE2# Controlled Write Cycles
Figure
Back-to-back Read/Write Cycle Timings
Addresses tACC tOEH
High
Complement
Complement
True
Valid Data
High
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Data# Polling Timings (During Embedded Algorithms)
June 2005
Am29DL640G
CHARACTERISTICS
tAHT Addresses tAHT tASO tOEH tOEPH DQ6/DQ2 Valid Data
Valid Status
tCEPH
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle
Figure
Toggle Timings (During Embedded Algorithms)
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Note: toggles only when read address within erase-suspended sector. system toggle DQ6.
Figure
Am29DL640G
June 2005
CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC tVIDR tVHH tRSP tRRB Description Rise Fall Time (See Note) Rise Fall Time (See Note) RESET# Setup Time Temporary Sector Unprotect RESET# Hold Time from RY/BY# High Temporary Sector Unprotect Speed Options Unit
Note: 100% tested.
RESET# VSS, VIL, tVIDR Program Erase Command Sequence tVIDR
VSS, VIL,
tRSP RY/BY# tRRB
Figure
Temporary Sector Unprotect Timing Diagram
June 2005
Am29DL640G
CHARACTERISTICS
RESET#
Valid* Sector Group Protect/Unprotect
Valid* Verify
Valid*
Data
Status
Sector Group Protect: Sector Group Unprotect:
sector protect, sector unprotect,
Figure Sector/Sector Block Protect Unprotect Timing Diagram
Am29DL640G
June 2005
CHARACTERISTICS Alternate Controlled Erase Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 Std. tGHEL tCPH tWHWH1 Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time Pulse Width Pulse Width High Programming Operation (Note Accelerated Programming Operation, Word Byte (Note Sector Erase Operation (Note Byte Word Speed Options Unit
tWHWH1 tWHWH2
tWHWH1 tWHWH2
Notes: 100% tested. "Erase Programming Performance" section more information.
June 2005
Am29DL640G
CHARACTERISTICS
program erase program sector erase chip erase
Data# Polling
Addresses tGHEL tCPH Data
program erase program sector erase chip erase
tWHWH1
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: Figure indicates last cycles program erase operation. program address, sector address, program data. DQ7# complement data written device. DOUT data written device. Waveforms word mode.
Figure
Alternate Controlled Write (Erase/Program) Operation Timings
Am29DL640G
June 2005
ERASE PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Chip Program Time (Note Byte Mode Word Mode (Note (Note Unit Excludes system level overhead (Note Comments Excludes programming prior erasure (Note
Notes: Typical program erase times assume following conditions: 25°C, VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions 90°C, 1,000,000 cycles. typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum program times listed. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute two- four-bus-cycle sequence program command. Table further information command definitions. device minimum erase program cycle endurance 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect pins except pins (including OE#, RESET#) Input voltage with respect pins Current -1.0 -1.0 -100 12.5 +100
Note: Includes pins except VCC. Test conditions: time.
TSOP CAPACITANCE
Parameter Symbol Parameter Description Input Capacitance Test Setup TSOP Fine-pitch TSOP COUT Output Capacitance VOUT Fine-pitch TSOP CIN2 Notes: Sampled, 100% tested. Test conditions 25°C, MHz. Control Capacitance Fine-pitch Unit
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Unit Years Years
June 2005
Am29DL640G
PHYSICAL DIMENSIONS FBE063-63-Ball Fine-Pitch Ball Grid Array (FBGA) package
10/99
Am29DL640G
June 2005
PHYSICAL DIMENSIONS LAA064-64-Ball Fortified Ball Grid Array (FBGA) package
June 2005
Am29DL640G
PHYSICAL DIMENSIONS 048-48-Pin Standard TSOP
10/99
Am29DL640G
June 2005
REVISION SUMMARY Revision (November 2001)
Initial release. Noted that SecSi Sector, autoselect, functions unavailable when program erase operation progress. Common Flash Memory Interface (CFI) Changed wording last sentence third paragraph from, ".the autoselect mode." ".reading array data." Changed website address. Ordering Information Changed package marking Fortified (ordering designator PC). Command Definitions Changed wording last sentence first paragraph from, ".resets device reading array data." to."may place device unknown state. reset command then required return device reading array data." Table Am29DL640G Command Definitions Changed first address unlock bypass reset command sequence from XXX. CMOS Compatible Added parameter table. Deleted IACC parameter from table. Characteristics Read-Only Operations Changed Chip Enable Output High Output Enable Output High Speed Options from Word/Byte Configuration Changed BYTE# Switching Output High Speed Options from TSOP Capacitance Changed typicals maximums table. Added fine-pitch capacitance. Global SecSi Sector Flash Memory Region, Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that function unlock bypass modes available when SecSi sector enabled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, Chip Erase Command Sequence Removed speed option.
Revision (April 2002)
Global Changed data sheet status from Advance Information Preliminary.
Revision (June 2002)
Global Added speed option.
Revision (September 2002)
Global Removed Preliminary designation from data sheet.
Revision (October 2002)
Connection Diagrams 64-ball Fortified package, changed first last diagram. 48-ball Fine-pitch package, applied note with asterisk left hand balls. Special Handling Instructions Changed wording include TSOP packages. Ordering Information Removed FBGA designation from package type.
Revision (November 2002)
Customer Lockable: SecSi Sector Programmed Protected factory. Added second bullet, SecSi sector-protect.
June 2005
Am29DL640G
Revision (July 2004)
"Am29DL640G Autoselect Codes, (High Voltage Method)" page Replaced "80h (factory locked), (not factory locked)" with "81h (factory locked), (not factory locked)". "Am29DL640G Command Definitions" page SecSI Sector Factory Protect row, Data column Replaced "80/00" with "81/01. (Note Replaced "The data factory locked factory locked" with "The data factory locked factory locked". Global Changes Replaced with "tSEA Replaced with "tSEL Replaced "1µ" with "tPSP Replaced "100 with "tASP Replaced with "tSEA "Erase Program Operations" page Added last four columns table.
Revision (October 2004)
Cover page Title page Added notation superseding documents.
Revision B5(June 2005)
Modified disclaimers
Colophon products described this document designed, developed manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated that includes fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), where chance failure intolerable (i.e., submersible repeater artificial satellite). Please note that Spansion will liable and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, Export Administration Regulations applicable laws other country, prior authorization respective government entity will required export those products.
Trademarks Notice Copyright 2005 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof registered trademarks Advanced Micro Devices, Inc. ExpressFlash trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am29DL640G
June 2005
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